JP3354673B2 - EFM signal generation circuit device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an EFM (Eigh
The present invention relates to a circuit for generating an EFM signal necessary for modulation and demodulation.

[0002]

2. Description of the Related Art For example, in a recording apparatus used for recording original information on an optical disk, a recording pulse generating circuit for setting the operation timing of each component circuit in the recording apparatus at the time of recording the above-mentioned original signal is conventionally known. The circuit shown in FIG. Usually, the system clock of the entire recording apparatus is created by dividing the frequency by a frequency divider 2 connected to the output side of a crystal oscillator 1 for generating a master clock.
As an EFM channel clock used for the EFM modulation, an output signal of a PLL (phase locked loop) circuit having a configuration such as a voltage controlled oscillator (VCO) 6 is used. The PLL circuit includes:
A phase comparator 3 connected to an output side of the frequency divider 2 connected to an output side of the frequency divider 2 and an output side of the VCO 6 to compare phases of output clocks of the frequency divider 2 and the frequency divider 7; 3
, A loop filter 5 connected to the output side of the selector 4, a VCO 6 connected to the output side of the loop filter 5, and an EFM input circuit 9 to which an EFM signal reproduced from the optical disk is supplied. Of the EFM input circuit 9 connected to the output side of the frequency divider 7 and the output side of the frequency divider 7, and compares the phase of the output clock of the frequency divider 7 with the output side. It comprises a vessel 8.

In such a PLL circuit, when the original information is recorded on the optical disk, that is, when the EFM signal is modulated, the selector 4 selects the output clock of the phase comparator 3 and the master oscillator which the crystal oscillator 1 sends out. VC by clock
PL is locked by locking the VCO clock sent by O6.
Construct an L loop. On the other hand, when data is reproduced from the optical disk, that is, when demodulating the reproduced EFM signal, the selector 4 selects the output clock of the phase comparator 8 and the VFM is determined by the clock component transmitted from the EFM input circuit 9.
By locking the VCO clock sent by CO6, P
Construct an LL loop. Note that “locking” refers to a state where the phases and frequencies of both signals to be compared match.

[0004]

At the time of the EFM modulation, the clock transmitted from the VCO 6 is divided and
Although the LL loop is formed, the clock transmitted from the VCO 6 contains jitter. Therefore, at the time of recording, the original information is recorded in a state including the jitter component. Therefore, when the data recorded in this manner is reproduced, the reproduced waveform includes a large amount of jitter, and the so-called eye pattern is closed. The problem arises. The present invention has been made to solve such a problem.
It is an object of the present invention to provide an EFM signal generation circuit device capable of recording original information while reducing jitter in FM modulation.

[0005]

SUMMARY OF THE INVENTION The present invention relates to a circuit for generating an EFM signal for use in EFM encoding of original information, comprising: a crystal oscillator for generating a master clock serving as a reference; A frequency divider which is connected to the output side of the crystal oscillator and divides the output signal of the crystal oscillator to output the resulting signal as an EFM channel clock.

With this configuration, the crystal oscillator and the frequency divider transmit a frequency-divided version of the master clock as the EFM channel clock, so that the crystal oscillator and the frequency divider operate to provide a jitter-free EFM channel clock.

Further, the present invention provides a first crystal oscillator for generating a reference first master clock, a first local oscillator,
A phase comparison is performed between a first frequency-divided master clock transmitted from the first crystal oscillator and divided by a first frequency-divided clock obtained by dividing the first clock transmitted from the first local oscillator. A first phase comparator for sending an output signal to the first local oscillator via a loop filter, wherein at least the first crystal oscillator, the first local oscillator, and the first phase comparator constitute a PLL. Any one of a first loop circuit, a second local oscillator, a second crystal oscillator for generating a reference second master clock, and the first divided master clock and the second clock transmitted by the second local oscillator A third selector for selecting whether
A master clock and the first selector transmitted by the third selector;
A second phase comparator for comparing a phase with either the frequency-divided master clock or the second clock and sending an output signal thereof to the second local oscillator via a loop filter, wherein at least the second crystal oscillator A second loop circuit forming a PLL by the second local oscillator and the second phase comparator, and one of the first divided master clock and the second divided clock obtained by dividing the second clock. A second selector for selecting and transmitting the selected system clock as a system clock; and a frequency divider to which the second master clock is supplied and for transmitting a second frequency-divided master clock obtained by dividing the second master clock as an EFM channel clock. It is characterized by.

[0008] With this configuration, the second selector can control the first master clock transmitted from the first crystal oscillator and the second master clock.
One of a second frequency-divided clock obtained by dividing the second clock transmitted by the local oscillator is selected and transmitted as a system clock. The frequency divider is the second crystal oscillator
The second divided master clock obtained by dividing the master clock is represented by E
It is transmitted as an FM channel clock. Therefore,
The second selector selects the supplied clock,
It works so that a desired clock can be obtained for the system clock. The divider also acts to transmit a jitter-free second divided master clock for the EFM channel clock.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the EFM signal generating circuit device of the present invention will be described below with reference to the drawings. FIG. 1 shows a configuration in the first embodiment. The same components as those in FIG. 3 are denoted by the same reference numerals, and description thereof is omitted. In the first embodiment, the output side of the crystal oscillator 1 is connected to the frequency divider 20, and the output signal of the frequency divider 20 is used as an EFM channel clock. The output signal of the PLL circuit including the phase comparator 3, the loop filter 5, the VCO 6, and the frequency divider 7 to which the output signal of the frequency divider 20 is supplied is used as a system clock.

With this configuration, at the time of the EFM encoding, the output clock of the VCO 6 is locked by the clock transmitted from the crystal oscillator 1, thereby forming a PLL loop and performing the EFM encoding. At this time, EFM
As the channel clock, a clock obtained by dividing the master clock transmitted from the crystal oscillator 1 is used, and as the system clock, a clock obtained by dividing the output clock of the VCO 6 is used. In addition, VCO6 including jitter as system clock
However, since the jitter level is sufficiently included in the permissible range of fluctuation in the system clock, no trouble occurs in system operation. Since the master clock of the crystal oscillator 1 that does not include jitter is used as the EFM channel clock, there is no fluctuation that the eye pattern is closed at the time of reproduction as in the related art.

FIG. 2 shows the configuration of the second embodiment. The same components as those of FIG. 3 are denoted by the same reference numerals, and their description will be omitted. The second sending the system clock
The input side of the selector 21 is connected to the output side of the first crystal oscillator 22 via the frequency divider 33 and the output side of the second VCO 24 as the second local oscillator via the frequency divider 25.
The output side of the first crystal oscillator 22 is also connected to the input side of the first phase comparator 23 via the frequency divider 33. Also, the third
The input side of the selector 26 is connected to the output side of the first crystal oscillator 22 and the output side of the second VCO 24 via the frequency divider 33, and the output side of the third selector is connected to the input side of the second phase comparator 29. Is done. The input side of the fourth selector 27 for transmitting the EFM channel clock is connected to the output side of the first local oscillator VCO 6 and the frequency divider 30 via the frequency divider 7.
The output side of the second crystal oscillator 28 is connected via the.
The output side of the second crystal oscillator 28 is connected to the second phase comparator 2
The output side of the second phase comparator 29 is connected to the loop filter 31. The output side of the loop filter 31 is connected to the second VCO 24 and the switch 32
Is connected to the second crystal oscillator 28 via the.

The operation of the EFM signal generating circuit device according to the second embodiment configured as described above will be described below. First, the operation when performing EFM encoding will be described. In the case of encoding, the following three methods can be selected. First Method By selecting the output signal of the first phase comparator 23 by the selector 4, the first master clock transmitted from the first crystal oscillator 22 is divided by the first divided master clock to generate a VC.
The first clock transmitted by O6 is locked to form a PLL loop. In this case, a first frequency-divided master clock obtained by dividing the first master clock of the first crystal oscillator 22 is selected by the second selector 21 as the system clock, and the fourth selector 2 is used as the EFM channel clock.
At 7, a first frequency-divided clock obtained by dividing the first clock, which is the output clock of the VCO 6, is selected.

Second Method By selecting the second clock, which is the output clock of the second VCO 24, by the third selector 26, the second crystal oscillator 2
8 transmits the second VCO 24 by the second master clock.
Locks the second clock transmitted from the PLL and forms a PLL loop. In this case, as the system clock, the second selector 21 selects a second frequency-divided clock obtained by dividing the second clock of the second VCO 24, and as the EFM channel clock, the fourth selector 27 selects the second crystal oscillator 2.
A second divided master clock obtained by dividing the second master clock as the output clock of No. 8 is selected and used.

Third Method The third selector 26 selects a first divided master clock obtained by dividing the first master clock of the first crystal oscillator 22,
When the switch 32 is turned on, the second master clock transmitted from the second crystal oscillator 28 is locked by the first frequency-divided master clock, thereby forming a PLL loop. And in this case, the system clock is the second
The selector 21 selects a first frequency-divided master clock obtained by dividing the first master clock of the first crystal oscillator 22.
As the M channel clock, the second selector 27 divides the frequency of the second master clock of the second crystal oscillator 28 by the fourth selector 27.
Select and use the divided master clock.

As described above, the selection of the system clock and the EFM channel clock at the time of the EFM encoding can be selected from the above three methods according to the user's system. The second selector 21
When the first frequency-divided master clock transmitted by the frequency divider 33 is selected as the system clock in the step (1) and the first clock transmitted by the VCO 6 is selected in the fourth selector 27 as the EFM channel clock, the conventional EFM is used. It has the same configuration as the signal generation circuit. That is, the EFM channel clock transmitted from the fourth selector includes jitter. Therefore, the fourth selector 27 may be removed from the above-described circuit configuration, and the second frequency-divided master clock transmitted from the second crystal oscillator 28 via the frequency divider 30 may be directly used as the EFM channel clock. In this case,
Since the fourth selector 27 is eliminated, there are two methods for selecting the system clock and the EFM channel clock.

When EFM decoding is performed in the second embodiment, the following operation is performed. By selecting the output signal of the third phase comparator 8 by the selector 4, the EFM
The first clock transmitted from the VCO 6 is locked by the clock component of the output signal of the input 9 to form a PLL loop.
In this case, the second selector 21 selects the first frequency-divided master clock obtained by dividing the first master clock of the first crystal oscillator 22 as the system clock, and the fourth selector 27 uses the fourth frequency divider 27 as the EFM channel clock. VCO
The first divided clock obtained by dividing the first clock of No. 6 is selected and used.

[0017]

As described above in detail, according to the first aspect of the present invention, the crystal oscillator and the frequency divider transmit a frequency-divided version of the master clock as the EFM channel clock, and therefore do not include jitter. An EFM channel clock can be provided.

According to the second aspect of the present invention, the second
The selector selects one of a first master clock transmitted by the first crystal oscillator and a second frequency-divided clock obtained by dividing the second clock transmitted by the second local oscillator, and transmits the selected clock as a system clock. The transmitter transmits the second frequency-divided master clock obtained by dividing the second master clock transmitted from the second crystal oscillator as an EFM channel clock. A desired clock can be obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration in an embodiment of an EFM signal generation circuit device of the present invention.

FIG. 2 is a block diagram showing a configuration of another embodiment of the EFM signal generation circuit device of the present invention.

FIG. 3 is a block diagram showing a configuration of a conventional EFM signal generation circuit device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Crystal oscillator, 3 ... Phase comparator, 5 ... Loop filter, 6 ... VCO, 7 ... Divider, 9 ... EFM input, 20 ...
Frequency divider, 21: second selector, 22: first crystal oscillator,
23 first phase comparator, 24 second VCO, 25 frequency divider, 26 third selector, 27 fourth selector, 28
Second crystal oscillator, 29: second phase comparator, 30: frequency divider, 31: loop filter, 32: switch.

Claims (1)

(57) [Claims] A first crystal oscillator for generating a first master clock serving as a reference; a first local oscillator; a first divided master clock obtained by dividing the first master clock transmitted by the first crystal oscillator; The first local oscillator transmits the first
A first phase comparator for comparing a phase with a first frequency-divided clock obtained by dividing the clock and transmitting an output signal thereof to the first local oscillator via a loop filter, wherein at least the first crystal oscillator; A first loop circuit forming a PLL by the first local oscillator, the first phase comparator, a second local oscillator, a second crystal oscillator for generating a second master clock serving as a reference, and the first frequency divider A third clock for selecting either the master clock or the second clock transmitted by the second local oscillator;
A selector compares the phase of the second master clock with either the first frequency-divided master clock or the second clock transmitted by the third selector, and outputs an output signal of the second local clock via a loop filter to the second local oscillator. A second loop circuit that forms a PLL with at least the second crystal oscillator, the second local oscillator, and the second phase comparator; and the first frequency-divided master clock. A second selector for selecting any one of a second divided clock obtained by dividing the second clock and transmitting the selected system clock as a system clock; and a second selector supplied with the second master clock and dividing the second master clock. A frequency divider for transmitting a frequency-divided master clock as an EFM channel clock. An EFM signal generation circuit device comprising: