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JP3355288B2 - Wiring board for semiconductor mounting - Google Patents
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JP3355288B2 - Wiring board for semiconductor mounting - Google Patents

Wiring board for semiconductor mounting

Info

Publication number
JP3355288B2
JP3355288B2 JP13515297A JP13515297A JP3355288B2 JP 3355288 B2 JP3355288 B2 JP 3355288B2 JP 13515297 A JP13515297 A JP 13515297A JP 13515297 A JP13515297 A JP 13515297A JP 3355288 B2 JP3355288 B2 JP 3355288B2
Authority
JP
Japan
Prior art keywords
wiring board
semiconductor
mounting
wiring
shaped
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP13515297A
Other languages
Japanese (ja)
Other versions
JPH10326848A (en
Inventor
洋 大平
章 米沢
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Yamaichi Electronics Co Ltd
Original Assignee
Yamaichi Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Yamaichi Electronics Co Ltd filed Critical Yamaichi Electronics Co Ltd
Priority to JP13515297A priority Critical patent/JP3355288B2/en
Publication of JPH10326848A publication Critical patent/JPH10326848A/en
Application granted granted Critical
Publication of JP3355288B2 publication Critical patent/JP3355288B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0271Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/0097Processing two or more printed circuits simultaneously, e.g. made from a common substrate, or temporarily stacked circuit boards
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/851Dispositions of multiple connectors or interconnections
    • H10W72/874On different surfaces
    • H10W72/884Die-attach connectors and bond wires
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Structure Of Printed Boards (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、半導体搭載用配線
板に係り、さらに詳しくは配線板の反りが解消・低減さ
れ、信頼性の高い半導体チップの搭載・配置を可能とす
る半導体搭載用配線板に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring board for mounting a semiconductor, and more particularly, to a wiring for mounting a semiconductor, which can eliminate and reduce the warpage of the wiring board and can mount and arrange a highly reliable semiconductor chip. Regarding the board.

【0002】[0002]

【従来の技術】近年、機器の高機能化や小型化および低
コスト化などの要請に応じて、半導体チップを、たとえ
ば50〜 200μm 程度の薄い配線板主面に搭載し、その主
面に形成されている導体パッドを含む配線単位に接続す
る表面実装型の半導体パッケージ方式、もしくは半導体
モジュール方式が知られている。すなわち、図3に要部
構成を断面的に示すごとく、半導体搭載用配線板1の一
主面に、マウント材2を介して半導体チップ3をマウン
トする一方、半導体チップ3の電極と半導体搭載用配線
板1の被接続端子1aとの間をワイヤボンディング4した
構成の半導体パッケージ(もしくは半導体モジュール)
が開発されている。
2. Description of the Related Art In recent years, in response to demands for higher functionality, smaller size, and lower cost of equipment, semiconductor chips are mounted on a main surface of a thin wiring board of, for example, about 50 to 200 μm, and formed on the main surface. There is known a surface-mount type semiconductor package system or a semiconductor module system in which connection is made to a wiring unit including a conductive pad. 3, the semiconductor chip 3 is mounted on one main surface of the wiring board 1 for mounting a semiconductor via the mounting material 2, and the electrodes of the semiconductor chip 3 are connected to the electrodes for mounting the semiconductor. A semiconductor package (or semiconductor module) having a configuration in which wire bonding 4 is performed between the terminal 1a of the wiring board 1 and the connected terminal 1a.
Is being developed.

【0003】ここで、半導体搭載用配線板は、図4に拡
大して平面的に示すごとく、たとえば厚さ 100μm 、幅
20〜50mm程度,長さ 100〜 200mm程度の短冊状の絶縁性
シート(もしくはフィルム)を基板5とし、外形加工部
を除いた一主面に複数の配線単位6群が分離可能に配置
されている。そして、前記複数の配線単位6群に、それ
ぞれ対応する外部接続端子(図示省略)群が、スルホー
ル接続(図示省略)して他主面の外形加工部を除いたに
領域に配設されている。なお、半導体チップ3の搭載・
配置は、通常、前記短冊状の半導体搭載用配線板5′の
各配線単位6に一括的に行った後、前記外形加工線(点
線で図示)に沿って切断・分離している。
Here, the wiring board for mounting a semiconductor is, as shown in an enlarged plan view in FIG.
A strip-shaped insulating sheet (or film) having a length of about 20 to 50 mm and a length of about 100 to 200 mm is used as a substrate 5, and a plurality of wiring units 6 groups are separably arranged on one main surface excluding an externally processed portion. I have. A group of external connection terminals (not shown) respectively corresponding to the six groups of the wiring units are arranged in the area except for the externally processed portion on the other main surface by through-hole connection (not shown). . The mounting of the semiconductor chip 3
The arrangement is usually performed collectively for each wiring unit 6 of the strip-shaped wiring board for semiconductor mounting 5 ′, and then cut and separated along the outline processing line (shown by a dotted line).

【0004】[0004]

【発明が解決しようとする課題】ところで、上記短冊状
の半導体搭載用配線板5′は、実用上、次のような不都
合をしばしば提起する。すなわち分離可能な配線単位6
群の羅列に伴う短冊状化は、絶縁性シート5の薄膜さと
配線単位6の形設と相俟って全体的に反りを発生し易
く、特に、長さ方向において僅かながらの捩れなどが認
められる。一方、半導体搭載用配線板5′に対する半導
体チップ3の搭載・配置は、一般的に、コンベア上を搬
送され、かつ位置決めされる半導体搭載用配線板5′面
に、半導体チップ3を順次移載・配置することによって
行われる。ここで、半導体搭載用配線板5′の所定位置
に、半導体チップ3を精度よく、また確実に搭載・配置
するためには、両者が精度よく位置決めされ、また、一
定の方向性などを採っていることが前提になる。
The strip-shaped wiring board 5 'for mounting a semiconductor often poses the following disadvantages in practical use. That is, the separable wiring unit 6
The strip formation accompanying the grouping of the groups tends to cause warpage as a whole, in combination with the thin film of the insulating sheet 5 and the formation of the wiring unit 6, and in particular, slight twisting in the length direction is recognized. Can be On the other hand, the mounting and disposition of the semiconductor chip 3 on the semiconductor mounting wiring board 5 'is generally performed by sequentially transferring the semiconductor chips 3 to the semiconductor mounting wiring board 5' which is conveyed and positioned on the conveyor.・ It is performed by arrangement. Here, in order to mount and arrange the semiconductor chip 3 at a predetermined position of the semiconductor mounting wiring board 5 'with high accuracy and certainty, both are positioned with high accuracy and a certain direction is adopted. Is assumed.

【0005】しかしながら、上記短冊状の半導体搭載用
配線板5′が、僅かでも反りを有する状態にあると位置
ズレを起こし易いので、上記半導体チップ3の搭載・配
置の精度が損なわれることなり、結果的に、信頼性の高
い半導体パッケージ(もしくは半導体モジュール)の構
成が難しくなる。つまり、信頼性の高い半導体パッケー
ジの量産性や歩留まりなどが損なわれる恐れがあり、有
効な改善策の提供が待たれている。
However, if the strip-shaped wiring board for semiconductor mounting 5 'is slightly warped, it is likely to be displaced, so that the accuracy of mounting and disposing the semiconductor chip 3 is impaired. As a result, it becomes difficult to configure a highly reliable semiconductor package (or semiconductor module). In other words, there is a possibility that the mass productivity and yield of highly reliable semiconductor packages may be impaired, and there is a need for providing effective improvement measures.

【0006】本発明は、上記事情に対処してなされたも
ので、微細な配線単位が配置された構成でも、精度よく
半導体チップを位置決め・搭載配置することが容易にで
きる半導体搭載用配線板の提供を目的とする。
SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and a semiconductor mounting wiring board capable of easily positioning, mounting, and arranging a semiconductor chip accurately even in a configuration in which fine wiring units are arranged. For the purpose of providing.

【0007】[0007]

【課題を解決するための手段】請求項1の発明は、外形
加工部を有し、かつ複数の配線単位群が分離可能に配置
された短冊状の半導体搭載用配線基板であって、前記外
形加工部の少なくとも長さ方向に反りを吸収する、断面
Ωもしくは断面Πの溝状の折り曲げ部を形成して成るこ
とを特徴とする半導体搭載用配線板である。
According to a first aspect of the present invention, there is provided a strip-shaped wiring board for mounting a semiconductor having an outer shape processing portion, wherein a plurality of wiring unit groups are arranged so as to be separable. Cross section that absorbs warpage at least in the length direction of the processed part
A wiring board for mounting a semiconductor, characterized in that a groove-shaped bent portion having a resistance of Ω or a cross section 形成 is formed.

【0008】請求項2の発明は、外形加工部を有し、か
つ一主面に複数の配線単位群が分離可能に配置された短
冊状の配線板本体と、前記複数の配線単位群に対応して
配線板本体の他主面に配設された外部接続端子群とを具
備する半導体搭載用配線基板であって、前記外形加工部
の少なくとも長さ方向に反りを吸収する、断面Ωもしく
は断面Πの溝状の折り曲げ部を形成して成ることを特徴
とする半導体搭載用配線板である。
According to a second aspect of the present invention, there is provided a strip-shaped wiring board main body having an externally processed portion and having a plurality of wiring unit groups separably disposed on one main surface, and corresponding to the plurality of wiring unit groups. And an external connection terminal group disposed on the other main surface of the wiring board main body, wherein the cross-section Ω or
Is a wiring board for mounting a semiconductor, which is formed by forming a groove-shaped bent portion having a cross section Π .

【0009】この短冊状の半導体搭載用配線板の発明に
おいて、配線板本体は、たとえば液晶ポリマー、ガラス
・エポキシ樹脂、ポリイミド樹脂などの,厚さ50〜 200
μmのシートもしくはフィルムを絶縁素材とし、また、
被接続端子を含む配線単位が、たとえば厚さ18〜35μm
程度の銅箔を素材として構成されたものである。そし
て、その形態は、両面配線型を始め、内層配線を有する
3層以上の多層配線型であってもよく、さらに、配線単
位などのピッチは、一般的に、60〜 300μm 程度であ
る。なお、ここで、半導体搭載用配線板は、半導体パッ
ケージ用やマルチチップモジュール用配線板を意味し、
外部接続端子をスルホール接続で他主面(裏面)に導出
した構成とることもできる。
In the invention of the strip-shaped wiring board for mounting a semiconductor, the wiring board body is made of, for example, a liquid crystal polymer, a glass epoxy resin, a polyimide resin or the like having a thickness of 50 to 200.
μm sheet or film as insulating material,
The wiring unit including the connected terminal has a thickness of 18 to 35 μm, for example.
It is composed of a copper foil of a degree. The form may be a double-sided wiring type or a multi-layered wiring type having three or more layers having inner layer wirings, and the pitch of the wiring unit or the like is generally about 60 to 300 μm. Here, the wiring board for mounting a semiconductor means a wiring board for a semiconductor package or a multi-chip module,
A configuration in which the external connection terminal is led to the other main surface (back surface) by through-hole connection may be employed.

【0010】上記構成の短冊状半導体搭載用配線板にお
いて、外形加工部の少なくとも長さ方向に反りを吸収す
るために設ける折り曲げ部は、たとえば深さ 0.1〜 1.5
mm程度断面Ωもしくは断面пの溝状折り曲げで、または
外形加工部の長さ方向端縁のL字折り曲げなどでそれぞ
れ形成できる。そして、この反り吸収用の折り曲げ部
は、外形加工部の長さ方向に設けることにより、薄型で
短冊状の配線板の反り発生を容易に吸収・低減できる
が、幅方向にも溝状折り曲げ部を併せて設けておいても
よい。
In the strip-shaped wiring board for mounting a semiconductor having the above structure, the bent portion provided for absorbing the warp at least in the longitudinal direction of the externally processed portion has a depth of, for example, 0.1 to 1.5.
It can be formed by groove-shaped bending with a cross section Ω or cross section of about mm, or L-shaped bending at the longitudinal edge of the externally processed portion. By providing the bent portion for absorbing the warp in the length direction of the externally processed portion, the occurrence of the warp of the thin and strip-shaped wiring board can be easily absorbed and reduced, but the groove-shaped bent portion is also provided in the width direction. May be additionally provided.

【0011】[0011]

【発明の実施の形態】以下、図1および図2 (a), (b)
を参照して実施例を説明する。
DESCRIPTION OF THE PREFERRED EMBODIMENTS FIGS. 1 and 2 (a) and (b)
An example will be described with reference to FIG.

【0012】図1,図2 (a), (b)は、半導体パッケー
ジ用配線板の要部構成例を示したもので、図1は平面
図、図2 (a), (b)はそれぞれ異なる半導体パッケージ
用配線の断面図である。
FIGS. 1 and 2 (a) and (b) show an example of a configuration of a main part of a wiring board for a semiconductor package. FIG. 1 is a plan view, and FIGS. It is sectional drawing of the wiring for different semiconductor packages.

【0013】上記各図において、7′は外形加工部8を
有し、かつ複数の配線単位9群が分離可能に配置された
短冊状の半導体搭載用配線板、10は前記外形加工部8の
少なくとも長さ方向に形設された反りを吸収する折り曲
げ部である。さらに、具体的に説明すると、外形加工部
8を有し、かつ一主面に複数の配線単位9群が分離可能
に配置された短冊状の配線板本体7と、前記複数の配線
単位9群にそれぞれ対応して配線板本体7の他主面に配
設された外部接続端子11群とを具備する半導体搭載用配
線板7′であって、前記外形加工部8の少なくとも長さ
方向に反りを吸収する折り曲10げが形設されていること
を特徴とする半導体搭載用配線板である。 ここで、短
冊状の配線板本体7は、たとえば厚さ 100μm ,長さ 1
50mm,幅が35mmのガラス・エポキシ樹脂シートであり、
また、被接続端子を含む配線単位9は、たとえば厚さ18
μm 銅箔のホォトエッチングで、 8× 8mm程度で、配線
ピッチ 170μm 程度に形成されている。つまり、短冊状
の配線板本体7の幅方向両端側、および配線単位9間に
は、それぞれ切断加工線(点線)で切断分離される外形
加工部8を有する構成と成っている。そして、前記各配
線単位9群に、それぞれ対応する外部接続端子11群が、
スルホール接続(図示省略)して外形加工領域外の他主
面に配設されている。
In each of the above drawings, reference numeral 7 'denotes a strip-shaped wiring board for mounting a semiconductor having an outer shape processing portion 8 and a plurality of wiring units 9 arranged so as to be separable. It is a bent portion formed at least in the length direction for absorbing a warp. More specifically, a strip-shaped wiring board main body 7 having an outer shape processing portion 8 and having a plurality of wiring units 9 groups separably arranged on one main surface, and the plurality of wiring units 9 groups A wiring board 7 ′ for mounting a semiconductor device, comprising a group of external connection terminals 11 disposed on the other main surface of the wiring board body 7, respectively, wherein the externally processed portion 8 is warped at least in the length direction. This is a wiring board for mounting a semiconductor, characterized in that it is provided with a bent portion 10 that absorbs the noise. Here, the strip-shaped wiring board body 7 has a thickness of, for example, 100 μm and a length of 1 μm.
50mm, 35mm width glass epoxy resin sheet,
The wiring unit 9 including the terminal to be connected has a thickness of, for example, 18 mm.
It is formed by photo-etching of μm copper foil with a size of about 8 × 8 mm and a wiring pitch of about 170 μm. In other words, the configuration is such that the outer shape processing portion 8 is cut and separated by a cutting line (dotted line) between both ends in the width direction of the strip-shaped wiring board main body 7 and between the wiring units 9. An external connection terminal 11 group corresponding to each of the wiring unit 9 groups is
The through-hole connection (not shown) is provided on the other main surface outside the contour processing area.

【0014】一方、図2 (a), (b)に示すごとく、前記
外形加工部8の端縁部に沿わせて(平行に)一部を、深
さ 1mm程度断面Ωもしくは断面пの溝状に折り曲げる
か、または端縁部を高さ 1mm程度の L字に折り曲げるこ
とにより、短冊状の配線板本体7もしくは短冊状の半導
体搭載用配線板7′に発生する反りが吸収される。
On the other hand, as shown in FIGS. 2 (a) and 2 (b), a part along (in parallel with) the edge of the externally processed portion 8 is formed with a groove having a cross section Ω or a cross section of about 1 mm in depth. By bending it into an L-shape or by bending the edge into an L-shape having a height of about 1 mm, the warpage generated in the strip-shaped wiring board body 7 or the strip-shaped wiring board 7 'for semiconductor mounting is absorbed.

【0015】なお、上記構成の短冊状の半導体搭載用配
線板7′に対する半導体チップの搭載・配置は、各配線
単位9に連続的に行った後、前記外形加工線(点線で図
示)に沿って切断・分離する形態で使用される。
The mounting and disposition of the semiconductor chip on the strip-shaped wiring board 7 'for semiconductor mounting having the above-described structure is performed continuously for each wiring unit 9 and then along the contour processing line (shown by a dotted line). It is used in the form of cutting and separating.

【0016】次に、上記半導体パッケージ用配線板の製
造方法例を説明する。
Next, an example of a method for manufacturing the wiring board for a semiconductor package will be described.

【0017】先ず、両面に厚さ18μm の銅箔張りで、か
つ全体の厚さが 100μm のガラス・エポキシ樹脂系の短
冊状積層板を用意し、所要の配線単位領域と外形加工領
域に分け、所要のスルホール接続部(図示省略)に相当
する位置に孔明けを行ってら、メッキ処理を施して明け
た孔内壁面に導電層化し、スルホール接続部をそれぞれ
形成する。次いで、前記両面銅箔をフォトエッチング処
理し、所要の配線単位9群、外部接続端子11群をそれぞ
れ形成することによって、所望の半導体パッケージ用配
線板を製造する。
First, a glass-epoxy resin strip-like laminate having a copper foil of 18 μm thickness on both sides and a total thickness of 100 μm was prepared, and divided into a required wiring unit area and an external processing area. Drilling is performed at a position corresponding to a required through-hole connection portion (not shown), and then a plating process is performed to form a conductive layer on the inner wall surface of the drilled hole, thereby forming a through-hole connection portion. Next, the desired double-sided copper foil is subjected to a photo-etching process to form 9 groups of required wiring units and 11 groups of external connection terminals, thereby manufacturing a desired wiring board for a semiconductor package.

【0018】その後、上記短冊状で、複数の配線単位9
群を有する半導体パッケージ用配線板の両幅側端縁に平
行する領域に、細い帯状の(選択的)加熱・加圧プレス
加工を施し、深さ 1mm,幅 1mmの断面п溝状に折り曲げ
ることによって、反りの発生が抑制ないし解消したて短
冊状の半導体パッケージ用配線板が得られる。なお、上
記折り曲げ位置は、両幅側端縁に平行する領域とともに
配線単位9同士の間隔部に併せて設けてもよいし、単純
に両幅側端縁をほぼ垂直方向折り曲げて・立たせてもよ
い。
Thereafter, a plurality of wiring units 9 are formed in the strip shape.
Apply a thin, band-shaped (selective) heat and pressure press process to the area parallel to the edges on both width sides of the wiring board for a semiconductor package with a group, and bend it into a cross-section groove with a depth of 1 mm and a width of 1 mm As a result, a strip-shaped wiring board for a semiconductor package is obtained in which the occurrence of warpage is suppressed or eliminated. The bending position may be provided along with the region parallel to both width side edges and also at the interval between the wiring units 9 or simply bending both width side edges substantially vertically and standing. Good.

【0019】なお、上記では、半導体パッケージ用配線
板に付いて例示したが、多チップ搭載のマルチチップモ
ジュール用配線板としても使用でき、本発明は、前記例
示に限定されるものでなく、発明の趣旨を逸脱しない範
囲で、いろいろの変形を採ることができる。たとえば配
線板本体の配線単位の構成は、多層であってもよいし、
絶縁性シートもガラス・エポキシ樹脂系以外の液晶ポリ
マーなどであってもよい。
In the above description, the wiring board for a semiconductor package has been described as an example. However, the present invention can also be used as a wiring board for a multi-chip module on which multiple chips are mounted, and the present invention is not limited to the above examples. Various modifications can be made without departing from the spirit of the present invention. For example, the configuration of the wiring unit of the wiring board body may be a multilayer,
The insulating sheet may also be a liquid crystal polymer other than the glass / epoxy resin type.

【0020】[0020]

【発明の効果】本発明に係る半導体搭載用配線板の場合
は、外形加工部11領域の一部を折り曲げ、配線板の伸縮
性に対して遊び部をおいた構成を採ったため、短冊状の
長さ方向に生じ易い反り発生性、反り発生現象が容易に
吸収されて、全体的に良好な平坦性を呈する。したがっ
て、半導体チップの搭載・実装に当たって、位置ズレな
ど起こす恐れも解消・低減されるので、量産での歩留ま
り向上を図りながら、信頼性の高い半導体パッケージの
提供に大きく寄与する。
In the case of the wiring board for mounting a semiconductor according to the present invention, since a part of the externally processed portion 11 is bent so that a play portion is provided for the elasticity of the wiring board, a strip shape is obtained. The warp generation property and the warp generation phenomenon that are likely to occur in the length direction are easily absorbed, so that good flatness is exhibited as a whole. Therefore, the risk of misalignment or the like during mounting and mounting of the semiconductor chip is eliminated and reduced, which greatly contributes to providing a highly reliable semiconductor package while improving the yield in mass production.

【図面の簡単な説明】[Brief description of the drawings]

【図1】一実施例の半導体パッケージ用配線板の要部構
成を示す平面図。
FIG. 1 is a plan view showing a configuration of a main part of a wiring board for a semiconductor package according to an embodiment.

【図2】(a), (b)は互いに異なる半導体パッケージ用
配線板の要部構成を示す断面図。
FIGS. 2 (a) and 2 (b) are cross-sectional views showing the main configuration of a wiring board for a semiconductor package different from each other.

【図3】従来の半導体パッケージの要部構造例を示す断
面図。
FIG. 3 is a cross-sectional view showing an example of a main part structure of a conventional semiconductor package.

【図4】従来の半導体パッケージ用配線板の要部構成を
示す平面図。
FIG. 4 is a plan view showing a configuration of a main part of a conventional wiring board for a semiconductor package.

【符号の説明】[Explanation of symbols]

1……配線板本体 2……マウント材 3……半導体チップ 4……ワイヤボンディング 5,7……短冊状配線板本体 5′、7′……短冊状の半導体搭載用配線板 6,9……配線単位 8……外形加工部 10……折り曲げ部 11……外部接続端子 DESCRIPTION OF SYMBOLS 1 ... Wiring board main body 2 ... Mounting material 3 ... Semiconductor chip 4 ... Wire bonding 5, 7 ... Strip shaped wiring board main body 5 ', 7' ... Strip shaped semiconductor mounting wiring board 6, 9 ... … Wiring unit 8… External processing part 10… Bending part 11 …… External connection terminal

Claims (2)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 外形加工部を有し、かつ複数の配線単位
群が分離可能に配置された短冊状の半導体搭載用配線基
板であって、 前記外形加工部の少なくとも長さ方向に反りを吸収す
、断面Ωもしくは断面Πの溝状の折り曲げ部を形成し
て成ることを特徴とする半導体搭載用配線板。
1. A strip-shaped wiring board for mounting a semiconductor having an externally processed portion and a plurality of wiring unit groups arranged so as to be separable, wherein the externally processed portion absorbs warpage at least in a length direction. A wiring board for mounting a semiconductor, characterized by forming a groove-shaped bent portion having a cross section Ω or a cross section す る .
【請求項2】 外形加工部を有し、かつ一主面に複数の
配線単位群が分離可能に配置された短冊状の配線板本体
と、 前記複数の配線単位群に対応して配線板本体の他主面に
配設された外部接続端子群とを具備する半導体搭載用配
線基板であって、 前記外形加工部の少なくとも長さ方向に反りを吸収す
、断面Ωもしくは断面Πの溝状の折り曲げ部を形成し
て成ることを特徴とする半導体搭載用配線板。
2. A strip-shaped wiring board body having an externally processed portion and having a plurality of wiring unit groups separably arranged on one main surface, and a wiring board body corresponding to the plurality of wiring unit groups. A semiconductor mounting wiring board comprising an external connection terminal group disposed on the other main surface of the semiconductor device, wherein the external shape processing portion absorbs warpage at least in a length direction, and has a groove-shaped cross section of Ω or Π. A wiring board for mounting a semiconductor, comprising a bent portion.
JP13515297A 1997-05-26 1997-05-26 Wiring board for semiconductor mounting Expired - Fee Related JP3355288B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13515297A JP3355288B2 (en) 1997-05-26 1997-05-26 Wiring board for semiconductor mounting

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13515297A JP3355288B2 (en) 1997-05-26 1997-05-26 Wiring board for semiconductor mounting

Publications (2)

Publication Number Publication Date
JPH10326848A JPH10326848A (en) 1998-12-08
JP3355288B2 true JP3355288B2 (en) 2002-12-09

Family

ID=15145040

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13515297A Expired - Fee Related JP3355288B2 (en) 1997-05-26 1997-05-26 Wiring board for semiconductor mounting

Country Status (1)

Country Link
JP (1) JP3355288B2 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4645261B2 (en) * 2005-03-28 2011-03-09 住友ベークライト株式会社 Flexible printed circuit board
JP5095140B2 (en) * 2006-07-03 2012-12-12 日本メクトロン株式会社 Component mounting method of flexible printed wiring board
JP6146732B2 (en) * 2013-01-18 2017-06-14 Shマテリアル株式会社 Semiconductor device mounting substrate and manufacturing method thereof

Also Published As

Publication number Publication date
JPH10326848A (en) 1998-12-08

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