JP3356258B2 - A / D conversion error correction circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an A / D conversion error correction circuit, and more particularly, to increasing the speed of A / D conversion using a plurality of A / D conversion circuits. The present invention relates to a device for correcting an error caused by the error.

[0002]

2. Description of the Related Art When the conversion speed of an A / D conversion circuit is insufficient, two A / D conversion circuits (ADCs) 1 as shown in FIG.
And 2, the same signal is sampled in parallel, the outputs of ADCs 1 and 2 are alternately switched by switch 6 and output in series, thereby increasing the speed of A / D conversion as a whole. However, the ADC is, for example, shown in FIG.
The reference voltages of the comparators 15 to 17 fluctuate due to fluctuations of the voltage dividing resistors 11 to 14, etc., and an offset difference occurs between ADC1 and ADC2. Nevertheless, there is a case where a difference occurs in the output signal of the binary conversion circuit 18. Due to this difference, for example, when a video signal is processed and displayed on a screen, vertical stripes of light and shade are generated at equal intervals on the screen as shown in FIG. The difference in shading increases with the difference in reference voltage between the ADCs. In addition, the offset difference changes due to a temperature change or the passage of time.

[0003]

In view of the foregoing, the present invention has been made in consideration of the above circumstances, and has been described in detail with respect to a period in which an input signal does not vary, for example, an ADC.
The difference between the output signals between the ADCs when sampling at
An object of the present invention is to correct an A / D conversion error by detecting a signal in a period of a flat synchronization signal and adding a difference to one of the signals .

[0004]

Means for Solving the Problems In order to solve the above-mentioned problems, the present invention converts the same video signal into a digital signal by a plurality of A / D conversion circuits and switches signals from the A / D conversion circuit. In the output, the difference between the output signal of the first A / D conversion circuit and the output signal of the other A / D conversion circuit when the same signal is input is applied during the period of the horizontal synchronization signal of the video signal
A difference detection unit that detects based on the sampling signal to be
A memory unit for storing the signal from the difference detection unit;
An adder for adding the read signal to the output signal of another A / D converter is provided, and the signal from the first A / D converter and the signal from the adder are sequentially switched and output. / D conversion error correction circuit is provided.

[0005]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In an A / D conversion error correction circuit according to the present invention, two ADCs are arranged in parallel, the same video signal is sampled in parallel by the two ADCs, and the period of the horizontal synchronization signal is adjusted.
The difference between the output signals of the two ADCs is detected by the difference detection unit based on the sampling signal applied between them, and is temporarily recorded in the memory unit. This signal is read out and added to the output signal of one ADC by the addition unit. The signal from the adder and the output signal of the ADC having no adder are switched by a switch and output. In addition, the memory unit holds until the period of the next horizontal synchronization signal,
Rewrite to the next signal from the difference detector .

[0006]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of an A / D conversion error correction circuit according to the present invention will be described below in detail with reference to the drawings. FIG. 1 is a block diagram of a main part of an embodiment of an A / D conversion error correction circuit according to the present invention, in which two A / D conversion circuits (ADCs) are used. In the figure, ADCs 1 and 2 sample an analog video signal at a required frequency, for example, a clock having a frequency four times the frequency of the color subcarrier signal of the video signal. Reference numeral 3 denotes a difference detection unit, which performs AD conversion on a sampling signal (a signal applied during a period of a horizontal synchronization signal of a video signal).
The difference between the output signals of C1 and ADC2 is detected. Reference numeral 4 denotes a memory unit that stores a signal from the difference detection unit 3. Reference numeral 5 denotes an adder for adding the signal read from the memory 4 to the output signal of the ADC 2. Reference numeral 6 denotes a switch that switches between the output signal of the ADC 1 and the signal from the adder 5 in synchronization with the sampling clocks of the ADCs 1 and 2.

Next, the operation of the A / D conversion error correction circuit according to the present invention will be described. 1 correspond to those in the signal waveform diagram shown in FIG. Analog video signals are simultaneously input to ADC1 and ADC2,
For example, four times the frequency (N) of the color subcarrier signal of the video signal
In the case of TSC, sampling is performed at a clock of about 3.58 MHz × 4 = about 14.32 MHz). As described above, there is an offset difference between the two ADCs due to a variation in the reference voltage of each comparator, and even if the same signal is sampled, a difference occurs between the output signals of the ADC1 and the ADC2. For example, A / D conversion is 8 bits and ADC
When the output signal of No. 1 is “00010000” and the output signal of ADC 2 is “000011111”, the difference between the two signals is “00000001”. In this example, a difference occurs in the least significant bit. However, depending on the magnitude of the offset difference, the signal difference is enlarged, and the above-described difference in shading of the screen in FIG. 5 becomes noticeable.

For this reason, a signal (sampling signal) having the same width as the horizontal synchronizing signal synchronized with the horizontal synchronizing signal, for example, is applied to the difference detecting section 3 during a period in which the video signal has no variable element. Is subtracted from the output signal of ADC2 to detect the difference. This operation is
An average of a signal and a sampling value of the signal is obtained, and a difference between the average values of the two signals is calculated. In the above example, the signal of this difference is “00000001”. The signal from the difference detection unit 3 is once written into the memory unit 4, and the signal from the memory unit 4 is read out during the scanning period of the video signal, input to the addition unit 5, and added to the signal from the ADC 2 to obtain a signal. The memory unit 4 holds this signal until the next horizontal synchronizing signal, and rewrites it when a new signal is input.

As a result, the signal switched by the switch 6 is a signal in which the offset difference between the two ADCs is corrected. For example, the video signals at the time of sampling of the ADC1 and the ADC2 are at the same level, and the signal is "100,000".
00 "and the signal" 01111111 ", the signal is the signal" 10000000 "obtained by adding the signal to the signal.
And the error due to the A / D conversion is corrected.
The vertical stripes shown in FIG. The sampling signal is, for example, a signal generated by separating only the horizontal synchronizing signal from the video signal, or a signal generated with substantially the same width as the horizontal synchronizing signal synchronized with the horizontal synchronizing signal.

In the above description, an example in which two ADCs are arranged in parallel has been described. However, the required A / D conversion speed or the AD used
Depending on the capability of C, three or more ADCs are arranged in parallel, any one of the ADCs is used as a reference, the offset difference between the reference ADC and another ADC is detected, and each difference is used as the other ADC.
The voltage may be applied to an adder provided at a stage subsequent to the DC and added to the output signal.

[0011]

As described above, according to the present invention, A
According to the / D conversion error correction circuit, in order to increase the A / D conversion speed, a plurality of ADCs simultaneously sample one video signal or the like, sequentially switch the output, and output the offset in a serial manner. Since the error of the output signal caused by the above is corrected, the vertical stripes generated on the screen are removed, and it is useful that this can be realized with a simple circuit configuration.

[Brief description of the drawings]

FIG. 1 is a main block diagram of an embodiment of an A / D conversion error correction circuit according to the present invention.

FIG. 2 is an example of a waveform diagram of and in the block diagram shown in FIG. 1;

FIG. 3 is a main part block diagram of an example of a conventional A / D conversion circuit.

FIG. 4 is an example of a circuit configuration of an A / D conversion circuit for explaining an offset difference.

FIG. 5 is a diagram illustrating vertical stripes on a screen due to an offset difference.

[Explanation of symbols]

 1, 2 A / D conversion circuit (ADC) 3 Difference detection unit 4 Memory unit 5 Addition unit 6 Switch 11-14 Resistor 15-17 Comparator 18 Binary conversion circuit

Claims (5)

(57) [Claims] A plurality of A / D conversion circuits for converting the same video signal into a digital signal and switching and outputting a signal from the A / D conversion circuit; The difference between the output signal of the D conversion circuit and the output signal of another A / D conversion circuit is applied to the period of the horizontal synchronization signal of the video signal
A difference detection unit that detects based on the sampling signal to be
A memory unit for storing the signal from the difference detection unit;
An adder for adding the read signal to the output signal of another A / D converter is provided, and the signal from the first A / D converter and the signal from the adder are sequentially switched and output. / D conversion error correction circuit. 2. The method according to claim 1, wherein the difference detection section detects a difference between output signals of the A / D conversion circuits each time sampling is performed.
A / D conversion error correction circuit according to any one of the preceding claims. 3. The A / D conversion error correction circuit according to claim 1, wherein said difference detection section outputs an average value obtained by sampling a difference between output signals of said A / D conversion circuits a required number of times. 4. The A according to claim 2, wherein an output signal of each of the A / D conversion circuits is an output when sampling is performed at a frequency four times as high as a color subcarrier signal of a video signal.
/ D conversion error correction circuit. Wherein said memory unit, an output of from the difference detection unit written, and held until the period of the next horizontal synchronizing signal,
2. The A / D conversion error correction circuit according to claim 1, wherein the A / D conversion error correction circuit rewrites a new signal.