JP3360038B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a circuit block on a substrate which is a source of noise and crosstalk, and other circuits which are not subject to noise and crosstalk from the circuit block. The present invention relates to a semiconductor device provided with a block.

[0002]

2. Description of the Related Art FIG. 5 shows a conventional semiconductor device. In the vicinity of the surface of the P-type semiconductor substrate 201, the circuit block (CB1) 202 and the circuit block (CB) are set at a predetermined distance.
2) 203 is provided. Here, the circuit block 2
02 generates noise and crosstalk, and the circuit block 203 does not want to be affected by the noise and crosstalk from the circuit block 202. Circuit block 2
02 in the P-type semiconductor substrate 201 immediately below the P-well 20.
4 are formed, and similarly, a P well 205 is formed immediately below the circuit block 203. P-type diffusion regions 206 and 207 are provided around the P-wells 204 and 205, and N-wells 208 and 209 are provided in the vicinity thereof. P between N wells 208 and 209
A type semiconductor substrate region 210 is formed, and a wiring layer 211 is provided near the surface of the P-type semiconductor substrate 201 above the P-type semiconductor substrate region 210. The P-type semiconductor substrate region 210 provided between the circuit block 202 and the circuit block 203 is provided for measures against noise and crosstalk.
In 10, neither the N well nor the P well is formed.

In the configuration shown in FIG. 5, if the P-type diffusion regions 206 and 207 are set to the GND potential,
09, the power supply voltage VDD is applied, and the circuit block 202,
When measures against noise and crosstalk are taken by electrically surrounding the circuit block 203, the substrate resistance (R) generated between the circuit blocks 202 and 203 is about 1 KΩ. But,
With such a resistance value, it is difficult to attenuate noise and crosstalk leaking from the circuit block 202 to the circuit block 203. However, as shown in FIG. 5, the P-type semiconductor substrate region 210 where the N well and the P well are not provided is provided.
Is provided, the substrate resistance (R) 212 can be increased to several tens of times. As a result, the circuit block 2
It is possible to sufficiently attenuate noise and crosstalk leaking from the circuit block 02 to the circuit block 203.

[0004]

However, according to the conventional semiconductor device, since the impurity concentration of the P-type semiconductor base region 210 is as low as about 1 × 10 ¹⁵ / cm ³ , the wiring layer between the circuit blocks 202 and 203 is not provided. When the N-type inversion layer 21 is provided, the N-type inversion layer 21 is provided above the P-type semiconductor substrate region 210.
3 is formed. This N-type inversion layer 213 allows VD
N-wells 208 and 209 biased to D are short-circuited. For this reason, if the VDDs biasing the N-wells 208 and 209 of the circuit blocks 202 and 203 are separated so that they do not have a common impedance to prevent crosstalk, noise and crosstalk deteriorate. . Also, when VDD biasing the N wells 208 and 209 is supplied from another pin, a leak may occur between the pins.

Therefore, an object of the present invention is to provide a wiring layer between circuit blocks without forming an N-type inversion layer, thereby reducing noise and noise.
An object of the present invention is to provide a semiconductor device capable of reducing leakage, crosstalk, and the like.

[0006]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention provides a semiconductor device having a first distance from a semiconductor substrate at a predetermined distance.
And a second circuit block, wherein the first and second circuit blocks are provided.
A P-well is formed near the surface in the semiconductor substrate corresponding to each of the circuit blocks of FIG.
N-wells functioning as guard rings are provided
A wiring layer is provided between the first and second circuit blocks.
In the semiconductor device that is a P-type semiconductor substrate region portion provided in the semiconductor substrate opposite to the wiring layer without N-well and P-well is formed, the wiring layer and the P-type semiconductor substrate region portion Between the ground
Noise or noise within the first and second circuit blocks.
On the circuit block that is the source of crosstalk
Is biased by a reverse phase signal having a potential opposite to that of the
A semiconductor device including a conductive layer for preventing an N-type inversion layer from being formed in a semiconductor substrate region .

According to this structure, the conductive layer provided between the P-type semiconductor substrate region where the N well and the P well are not formed and the wiring layer is biased to the ground potential, or
Noise or noise within the first or second circuit block
On the circuit block that is the source of the stoke
Biased by the opposite phase signal of the opposite potential to the signal
Therefore, an N-type inversion layer is not formed on the P-type semiconductor substrate region.
No. Therefore, the layer resistance in the P-type semiconductor substrate region is sufficiently increased, and noise from one circuit block to the other circuit block is reduced. Also, crosstalk is reduced.

[0008]

Embodiments of the present invention will be described below with reference to the drawings. [First Embodiment] FIG. 1 shows a first embodiment of a semiconductor device according to the present invention. FIG. 2 shows an AA cross section of FIG.

In the vicinity of the surface of the P-type semiconductor substrate 101, a circuit block (CB1) 102 and a circuit block (CB2) 103 are arranged at a predetermined distance. Here, it is assumed that the circuit block 102 generates noise and crosstalk, and the circuit block 103 does not want to be affected by the noise and crosstalk from the circuit block 102. P-type semiconductor substrate 101 immediately below circuit block 102
Inside, a P well 104 is formed, and similarly, a P well 105 is formed immediately below the circuit block 103.
P-type diffusion region 1 is provided around P wells 104 and 105.
06 and 107 are provided, and N wells 108 and 109 are provided in the vicinity thereof. A P-type semiconductor substrate region 110 is formed between the N wells 108 and 109. Polysilicon (polycrys- talline) is formed near the surface of the P-type semiconductor substrate 101 above the P-type semiconductor substrate region 110.
A layer 111 is provided, and a wiring layer 112 is provided near the surface of the polysilicon layer 111. Note that the polysilicon layer 111 may be a conductive layer such as a metal wiring instead of the polysilicon.

The circuit blocks 102 and 103 include P-type diffusion regions 106 and 107 biased to GND potential, and
The guard ring is formed by N wells 108 and 109 biased by the VDD potential. In the P-type semiconductor substrate region 110, neither the N well nor the P well 109 is formed. The polysilicon layer 111 provided so as to cover the P-type semiconductor substrate region 110 is bypassed to the GND potential.
Be assassinated. Since the P-type semiconductor substrate region 110 has a low impurity concentration of about 1 × 10 15 / cm 3, as described with reference to FIG.
An N-type inversion layer 213 is formed, which causes a short circuit between the N wells 108 and 109 of the guard ring and causes a leak.

However, as shown in FIG. 2, a polysilicon layer 111 is formed so as to cover the P-type semiconductor substrate region 110,
By biasing the polysilicon layer 111 to the GND potential, the polysilicon layer 111 functions as a field plate, the N-type inversion layer 213 does not occur due to the wiring layer 112, short-circuit and leakage are prevented, and noise is reduced. be able to.

[Second Embodiment] FIG. 3 shows a second embodiment of the semiconductor device according to the present invention. In the present embodiment, noise (power supply ripple) from VDD can be reduced. In FIG. 3, the same reference numerals are used for the same components as those shown in FIG. 2, and thus redundant description will be omitted below.

As shown in FIG. 3, the polysilicon layer 111 is
It has a width that covers the N wells 108 and 109. Then, it is biased to the GND potential together with the P-type diffusion regions 106 and 107.

As described above, by floating the N wells 108 and 109, the ripple of VDD is reduced to P
Without penetrating into the semiconductor substrate 101, and
Since the polysilicon layer 111 is provided so as to cover the type semiconductor substrate region 110 and the N wells 108 and 109, the N type inversion layer 213 described with reference to FIG. 5 does not occur.
Therefore, the N wells 108 and 109 do not cause a short circuit caused by the inversion layer 213. Also in the present embodiment, the polysilicon layer 111 may be a metal wiring instead of the polysilicon.

[Third Embodiment] FIG. 4 shows a third embodiment of the semiconductor device according to the present invention. In FIG. 4, the same reference numerals are used for the same components as those shown in FIGS. 2 and 3, and therefore, the duplicate description will be omitted below. In the present embodiment, the polysilicon layer 111
Are biased at a potential other than GND. In particular,
The bias potential of the polysilicon region 111 is biased by a reverse-phase signal 114 having a potential opposite to that of the signal of the circuit block 2. When the negative-phase signal 114 is applied to the polysilicon layer 111, for example, when a signal leaks from the circuit block 102 to the circuit block 103 and crosstalk deteriorates, the circuit block 1
In response to a signal leaking from 02 through the P-type semiconductor substrate region 110 to the circuit block 103, a negative-phase signal 114 is transmitted from the polysilicon layer 111 to the P-type semiconductor substrate region 110 through the circuit block 102 to cancel each other, thereby reducing crosstalk. .

[0016]

As described above, according to the semiconductor device of the present invention, in a semiconductor device having a circuit block for generating noise and the like and a circuit block for preventing noise and the like, the N-well and the P-well have the same structure. Since the conductive layer is provided between the unformed P-type semiconductor substrate region and the wiring layer, no N-type inversion layer is formed above the P-type semiconductor substrate region, and the layer resistance in the P-type semiconductor substrate region is sufficiently increased. Thus, leakage of signals and noise from one circuit block to the other circuit block can be reduced, and crosstalk can be reduced.

[Brief description of the drawings]

FIG. 1 is a plan view showing a first embodiment of a semiconductor device according to the present invention.

FIG. 2 is a sectional view showing an AA section in FIG. 1;

FIG. 3 is a sectional view showing a second embodiment of the semiconductor device according to the present invention.

FIG. 4 is a sectional view showing a third embodiment of the semiconductor device according to the present invention.

FIG. 5 is a sectional view showing a conventional semiconductor device.

[Explanation of symbols]

 Reference Signs List 101 P-type semiconductor substrate 102 Circuit block (CB1) 103 Circuit block (CB2) 104, 105 P-well 106, 107 P-type diffusion region 108, 109 N-well 110 P-type semiconductor substrate region 111 Polysilicon layer (polysilicon layer) 112 Wiring layer

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ identification code FI H01L 27/04 27/088 (58) Investigated field (Int.Cl. ⁷ , DB name) H01L 21/3205-21/3213 H01L 21/761 H01L 21/768

Claims (5)

(57) [Claims] 1. A first device having a predetermined distance on a semiconductor substrate.
And a second circuit block, wherein the first and second circuit blocks are provided.
A P-well is formed near the surface in the semiconductor substrate corresponding to each of the circuit blocks of FIG.
N-wells functioning as guard rings are provided
A wiring layer is provided between the first and second circuit blocks.
In the semiconductor device that is a P-type semiconductor substrate region portion provided in the semiconductor substrate opposite to the wiring layer without N-well and P-well is formed, the wiring layer and the P-type semiconductor substrate region portion Between the ground potential and the first and second circuit blocks
Of the side that is the source of noise and crosstalk
Bias with the opposite phase signal of the potential opposite to the signal on the circuit block
As a result, an N-type inversion layer is formed in the P-type semiconductor substrate region.
A semiconductor device, comprising: a conductive layer for preventing the occurrence of an electric field. 2. The semiconductor device according to claim 1, wherein said conductive layer is a polysilicon layer or a metal layer. 3. The semiconductor device according to claim 1, wherein said P well is biased to a ground potential. 4. The semiconductor device according to claim 1, wherein said conductive layer has a size that overlaps with each of said N wells of said first and second circuit blocks. 5. The semiconductor device according to claim 4, wherein said N-well is floating.