JP3360057B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is formed on an insulating material such as glass or a material obtained by forming an insulating film such as silicon oxide on a silicon wafer, and is used at a relatively high voltage. Insulated gate transistor (TFT)
And a method for manufacturing the same. The present invention particularly relates to an N-channel TFT. Further, the present invention is particularly effective for TFTs formed on a glass substrate having a glass transition point (also referred to as strain temperature or strain point) of 750 ° C. or less. The semiconductor device according to the present invention is used for a driving circuit such as an active matrix such as a liquid crystal display, an image sensor, or a three-dimensional integrated circuit.

[0002]

2. Description of the Related Art Conventionally, TFs have been used for driving active matrix type liquid crystal display devices and image sensors.
T (thin film transistor) is widely used. In particular,
Recently, crystalline silicon TFTs having higher electric field mobility have been developed in place of amorphous silicon TFTs using amorphous silicon for the active layer due to the need for high-speed operation. However, when more advanced characteristics and durability against driving at a high voltage were required, it was necessary to have a high resistance region. Hereinafter, in the present invention, a high resistance region is referred to as a high resistance impurity region (high resistance drain (HR)
D) or a low-concentration drain (LDD)) as well as a portion where the gate electrode and the impurity region do not overlap (that is, an offset region).

[0003]

However, in such a structure, particularly in an N-channel type TFT, a negative charge generated by hot carriers is trapped in the gate insulating film on the drain side. Has a weak P-type conductivity in the high-resistance region, and current between the source and the drain is hindered.

In the process of forming such a high-resistance region, it is necessary to rely on photolithography, and it is difficult to form a high-resistance region at the end of the gate electrode in a self-aligned manner. In addition, the yield and uniformity of characteristics of the obtained TFT were not good. The present invention has been made in view of such a problem, and prevents deterioration due to hot carriers, and allows a high-resistance region to be self-aligned (self-aligned).
In other words, the yield and the uniformity of the characteristics of the TFT are improved by forming the region in an appropriate manner, that is, by forming the region without using a photolithography process.

[0005]

According to the present invention, a positive charge such as silicon nitride having a thickness of 20 to 200 nm is formed on a high resistance region or on a gate insulating film (silicon oxide) formed on the high resistance region. Is provided with a film capable of trapping (trapping). Since positive charges are trapped in the film, the high-resistance region thereunder becomes weak N-type or cancels the negative charges, and as a result, deterioration due to hot carriers can be suppressed. That is, a high voltage is applied between the drain and the gate, for example, +15 V is applied to the drain, and -2 is applied to the gate.
Even when 0 V is applied, of the charges generated by the impact ionization, if the silicon oxide film does not exist on the high resistance region, the negative charge is not trapped, and the silicon oxide film does not exist. Even if negative charges are trapped there, if there is a coating that traps positive charges, the effect of negative charges will be canceled out,
The high resistance region does not become P-type. Therefore, high reliability can be obtained.

FIG. 4 shows the positional relationship between such a film for trapping (trapping) positive charges and the gate insulating film. In the figure, 1, 11, 21, 31 are sources, and 5, 1,
5, 25 and 35 are drains. Also, 2, 4, 1
2, 14, 22, 24, 32 and 34 are high resistance regions, and 3, 13, 23 and 33 are channel formation regions.
These semiconductor active layers are formed on the gate insulating films 6, 16, 2 and
There are 6, 36. Gate electrodes 7, 17, 27, and 37 are provided so as to cover the gate insulating film. The top and side surfaces of the gate electrode are covered by the anodic oxide layers 7 ', 17', 27 ', 37'. Then, interlayer insulators 8, 18, 28, and 38 are formed to cover them, and source electrodes 9, 19, 29, and 39, drain electrodes 10, 2, and
0, 30, and 40 are formed. Coatings 8 ', 18', 28 ', 38' for trapping positive charges are provided between the interlayer insulator and the gate electrode. The following four patterns can be considered from the relationship with the gate insulating film.

First, as shown in FIG. 4A, a gate insulating film 6 covers a source region 1 and a drain region 5, and a film 8 'is formed thereon. Second, FIG.
As shown in FIG. 2B, the gate insulating film 16 substantially covers the high resistance regions 12 and 14 and the channel formation region 13. Third, as shown in FIG. 4C, the gate insulating film 26 substantially covers only the channel formation region 23. Fourth is an improvement of FIGS. 4 (A) and (B).
As shown in FIG. 4D, the gate insulating film 36 is formed thinner except for a portion below the gate electrode (that is, a portion above the channel formation region 33).

In the present invention, when the high-resistance region is formed in a self-aligned manner as described above, an oxide layer formed by means such as anodic oxidation of a gate electrode is used positively, It is characterized in that a high resistance region is formed. The anodic oxide has a feature that its thickness can be precisely controlled, and its thickness can be wide and uniform from a thin one of 100 nm or less to a thick one of 500 nm or more (for example, 1 μm). Therefore, from the viewpoint of increasing the degree of freedom of the width of the high resistance region and adopting the self-alignment process, it is preferable to reduce the variation in the width.

In particular, the so-called barrier type anodic oxide is not etched unless it is a hydrofluoric acid-based etchant, whereas the porous type anodic oxide is selectively etched by an etchant such as phosphoric acid. For this reason, TFT
Is characterized in that it can be treated without damaging other materials (for example, silicon and silicon oxide). Further, in both the barrier type and the porous type, the anodic oxide is extremely difficult to be etched by dry etching. In particular, the feature is that the selectivity is sufficiently large in etching with silicon oxide. Therefore, after a porous anodic oxide is formed on at least a side surface of the gate electrode by a specific width, for example, 1 μm, the gate insulating film is etched using the porous anodic oxide as a mask, and then the porous anodic oxide is formed. When the object is etched, a region having no gate electrode and having only the gate insulating film can be formed about 1 μm beside the gate electrode. Through such steps, the structure in FIG. 4B can be obtained.

In the case of FIG. 4B, the high resistance region 12,
14 can be doped with an N-type impurity at a lower concentration than the source region 11 and the drain region 15 in one doping step. That is, in the case of impurity ions of specific energy, for example, phosphorus ions of 30 keV, the impurity concentration is highest at a depth of several tens nm from the surface, and generally has a Gaussian distribution. Therefore, while sufficient impurities are implanted into the source and drain regions not covered by the gate insulating film, in the high resistance region covered by the gate insulating film 16, most of the impurities are implanted by the gate insulating film. Stopping, the impurities implanted into the high resistance regions 12 and 14 are lower by about one or two digits than those implanted into the source and drain regions. When the energy of ions is lowered, the amount of impurities implanted into the high-resistance region is further reduced as compared with the amount of impurities implanted into the source region and the drain region, and remains the same conductivity type as that of the channel formation region. Become. As described above, the high-resistance region can be formed in a self-aligned manner by using the gate insulating film formed in a self-aligned manner.

In any case, the effect of the negative charges generated by the hot carriers can be offset by providing the coating for trapping the positive charges such as silicon nitride on the high resistance region. First, the case of FIG. 4A will be described. In this case, of the gate insulating film, the negative charge is trapped by the hot carrier injection into the gate insulating film (of the silicon oxide) on the drain-side high-resistance region 4 (of the silicon oxide). Since the positive charges are trapped in the film 8 'thereon, the negative charges are canceled. However, in order for the effect of the positive charge to reach the high resistance region, it is not desirable that the gate insulating film is too thick, and the thickness of the gate insulating film is preferably 50 nm or less. However, a disadvantage is that a thin film of 50 nm or less has a large leak current in a gate insulating film of poor quality.

Also in the case of FIG. 4B, the effect of the negative charges trapped in the gate insulating film on the high resistance region 14 on the drain side is affected by the positive charges trapped in the film 18 'thereon. Counteract. As in the case of FIG. 4A, it is not desirable that the gate insulating film is too thick.
The thickness of the gate insulating film is preferably 50 nm or less.

In the case of FIG. 4C, there is no gate insulating film on the high-resistance region 24 on the drain side, and positive charges are trapped in 28 ', so that the conductivity type of the high-resistance region is always constant. Weak N-type. However, in this case coating 2
When the film 8 ′ is formed, the high resistance region 2
2, 24 may be damaged. Generally light CV
The D method and the low-pressure CVD method have little damage, but the former has a disadvantage that the film formation rate is slow, and the latter has a high film formation temperature. However, plasma damage is unavoidable in the plasma CVD method having good mass productivity and low film formation temperature. Therefore, it must be taken into account that this structure can degrade the characteristics of the device somewhat.

In the case of FIG. 4D, the gate insulating film on the channel forming region 33 can be made sufficiently thick, so that the leakage current is small and the high resistance regions 32 and 34 are formed.
Is not damaged when forming the coating 37 '. The thickness of the gate insulating film 36 is preferably 50 nm or less on the high resistance region. The problem with this structure is that it is difficult to perform a technique for etching the gate insulating film only to an appropriate thickness, and there is a slight difficulty in mass productivity. FIG.
In (D), the gate insulating film 36 has the high resistance regions 32 and 34.
Although an example in which only the channel formation region 33 is covered is shown, the source region 31 and the drain region 35 may be covered. Hereinafter, examples of the present invention will be shown and described in further detail.

[0015]

[Embodiment 1] FIGS. 1 and 2 show this embodiment. FIG. 1 shows the basic steps of the present invention. First, a base insulating film 102 is formed over a substrate 101. As a substrate, a non-alkali glass, for example, Corning 705
9 (300mm × 400mm or 100mm × 10
0 mm). Thickness of 100 as the base insulating film 102
A silicon oxide film having a thickness of about 300 nm was formed. As a method for forming this oxide film, a sputtering method in an oxygen atmosphere was used. However, in order to further improve mass productivity, a film in which TEOS is decomposed and deposited by a plasma CVD method may be used. As a base film, a single layer film of aluminum nitride or a multilayer film of silicon oxide and aluminum nitride may be used other than silicon oxide. For forming the aluminum nitride film, a reactive sputtering method in a nitrogen atmosphere may be used.

Further, the active layer 103 is formed of a crystalline semiconductor (in the present invention, a semiconductor containing a small amount of crystals, such as a single crystal, polycrystal, or semi-amorphous, is called a crystalline semiconductor). Here, plasma CVD or LPCVD
An amorphous silicon film is deposited by a method at 30 to 500 nm, preferably 50 to 100 nm, and deposited at 550 to 600 ° C.
For 24 hours in a reducing atmosphere to allow crystallization. This step may be performed by laser irradiation. Then, the silicon film crystallized in this manner was patterned to form the island-like region 103. Then, the insulating film 104 is formed of a material such as silicon oxide so as to cover this.
The thickness of the insulating film 104 is 30 to 15 by a sputtering method.
Silicon oxide film 1 having a thickness of 0 nm, preferably 50 nm or less
04 was used.

Further, a film is formed of an anodizable material. Aluminum, tantalum, titanium, silicon, and the like, which can be anodized, are preferable as the material of the coating.
In the present invention, a gate electrode having a single layer structure using these materials alone may be used, or a gate electrode having a multilayer structure in which two or more layers are stacked. For example, it has a two-layer structure in which titanium silicide is stacked on aluminum or a two-layer structure in which aluminum is stacked on titanium nitride. The thickness of each layer may be determined by a practitioner according to the required device characteristics.

Further, a film serving as a mask in anodic oxidation is formed to cover the film, and both are simultaneously patterned and etched to form a gate electrode 105 and a mask film 106 thereon. As a material of the mask film, a photoresist used in a normal photolithography process, a photosensitive polyimide, or a material which can be etched with a normal polyimide may be used.

Here, as a film that can be anodized, aluminum (1 wt% S) having a thickness of 100 nm to 3 μm is used.
i or a film containing 0.1 to 0.3 wt% of Sc (scandium)) was formed by an electron beam evaporation method or a sputtering method. Then, a photoresist (for example, OFPR800 / manufactured by Tokyo Ohka) is used as a mask for anodic oxidation.
30 cp) by spin coating. Prior to the formation of the photoresist, a highly insulating, preferably barrier-type anodic oxide film, for example, having a thickness of 1
When an aluminum oxide film having a thickness of 0 to 100 nm is formed on the surface, adhesion to the photoresist is good, and current leakage from the photoresist is suppressed.
In the subsequent anodic oxidation step, it was effective in forming the porous anodic oxide only on the side surfaces. Thereafter, the photoresist and the aluminum film were patterned and etched together with the aluminum film to form a gate electrode 105 mask film 106. (Fig. 1 (A))

Next, by applying a current to the gate electrode 105 in an electrolytic solution, a porous anodic oxide 107 is formed on the side surface of the gate electrode. This anodizing step is performed in three steps.
The reaction is performed using an acidic aqueous solution of citric acid or oxalic acid, phosphoric acid, chromic acid, sulfuric acid, or the like of about 20%. In this case, at a low voltage of about 10 to 30 V, 0.3 to 25 μm,
For example, a thick anodic oxide of 1.0 μm can be formed. After the anodizing step, the mask film 106 is removed by etching.

In this embodiment, the thickness is 300 nm to 2 μm,
For example, a porous anodic oxide 107 having a thickness of 500 nm was formed. The anodic oxidation may be performed using a 3 to 20% aqueous solution of citric acid or oxalic acid, phosphoric acid, chromic acid, sulfuric acid, or the like, and applying a constant current of 10 to 30 V to the gate electrode. In this example, the voltage was set to 10 V in an oxalic acid solution (30 ° C.), and anodization was performed for 20 to 40 minutes. The thickness of the anodic oxide was controlled by the anodic oxidation time. (Figure 1
(B))

In the present invention, before proceeding to the next step,
By applying a current to the gate electrode in an ethylene glycol solution containing 3 to 10% tartaric acid, boric acid, and nitric acid, a barrier type anode having high insulating properties is further formed on the side and top surfaces of the gate electrode. The oxide 108 is preferably provided. In this anodic oxidation step, the thickness of the obtained anodic oxide is determined by the magnitude of the voltage applied between the gate electrode 105 and the opposing electrode.

That is, the mask was removed, and a current was applied to the gate electrode again in the electrolytic solution. In this anodization, an ethylene glycol solution containing 3 to 10% tartaric acid, boric acid, and nitric acid was used. A better oxide film was obtained when the temperature of the solution was lower than room temperature around 10 ° C. As a result, a barrier-type anodic oxide 108 was formed on the upper and side surfaces of the gate electrode. The thickness of the anodic oxide 108 is proportional to the applied voltage.
nm of anodic oxide was formed. Although the thickness of the anodic oxide 108 was determined by the required offset and the size of the overlap, a high voltage of 250 V or more was required to obtain an anodic oxide having a thickness of 300 nm or more.
It is preferable to set the thickness to 300 nm or less, since it adversely affects the characteristics of T. In this embodiment, the voltage was increased to 80 to 150 V, and the voltage was selected according to the required thickness of the anodic oxide film 108. (Fig. 1 (C))

It should be noted that although barrier-type anodic oxidation is a later step, barrier-type anodic oxide is not formed outside porous anodic oxide, but barrier-type anodic oxidation is performed. The object 108 is to be formed between the porous anodic oxide 107 and the gate electrode 105. In the above phosphoric acid-based etchant, the etching rate of the porous anodic oxide is 10 times or more the etching rate of the barrier anodic oxide. Therefore, the porous anodic oxide 10
7, the barrier type anodic oxide 108
Is not substantially etched by a phosphoric acid-based etchant, so that the inner aluminum gate electrode can be protected.

Then, the insulating film 104 is etched by a dry etching method, a wet etching method or the like.
This etching depth is arbitrary, and etching may be performed until the underlying active layer is exposed, or may be stopped during the etching. However, from the viewpoint of mass productivity, yield, and uniformity, it is desirable to perform etching up to the active layer. In this case, the anodic oxide 107 and the gate electrode 10
The insulating film having the original thickness is left in the insulating film (gate insulating film) below the region covered with 5. The gate electrode is mainly composed of aluminum, tantalum, and titanium.
When the insulating film 104 contains silicon oxide as a main component,
In the case of using a dry etching method, if dry etching is performed using a fluorine-based (eg, NF ₃ , SF ₆ ) etching gas, the insulating film 104 made of silicon oxide is used.
Is quickly etched, but the etching rate of aluminum oxide, tantalum oxide, and titanium oxide is sufficiently small, so that the insulating film 104 can be selectively etched.

In the wet etching, 1
A hydrofluoric acid-based etchant such as / 100 hydrofluoric acid may be used. In this case as well, the insulating film 104 made of silicon oxide is quickly etched, but the etching rate of aluminum oxide, tantalum oxide, and titanium oxide is sufficiently small, so that the insulating film 104 can be selectively etched.

In this embodiment, the silicon oxide film 104 is etched by a dry etching method. In this etching, even in the plasma mode of isotropic etching,
Alternatively, a reactive ion etching mode of anisotropic etching may be used. However, it is important to prevent the active layer from being etched deeply by sufficiently increasing the selectivity between silicon and silicon oxide. CF ₄ was used as an etching gas. As a matter of course, the silicon oxide film 104 ′ (hereinafter, referred to as a gate insulating film) under the porous anodic oxide 107 remains without being etched. (Figure 1
(D)) Thereafter, the porous anodic oxide 107 is removed. As the etchant, a phosphoric acid-based solution, for example, a mixed acid of phosphoric acid, acetic acid, and nitric acid is preferable. Etching rate is about 60nm
/ Min. The gate insulating film 104 'thereunder remained as it was. (FIG. 1 (E))

Through the above steps, a structure in which the gate insulating film 104 'was selectively left below the gate electrode was obtained. Since the gate insulating film 104 ′ originally existed under the porous anodic oxide 107, not only under the gate electrode 105 and under the barrier anodic oxide 108 but also at the barrier anodic oxide 108. , And a width y is almost constant, that is, determined in a self-aligned manner with respect to the gate electrode. In other words, a region where the gate insulating film 104 'exists and a region where the gate insulating film 104' does not exist are formed in a self-alignment manner outside the channel formation region below the gate electrode in the active layer 103.

Thereafter, the process is shifted to the step shown in FIG. First, the active layer 10 of the TFT is formed by ion doping.
3, N-type impurity ions, for example, phosphorus ions were implanted in a self-aligned manner using the gate electrode portion (that is, the gate electrode and the surrounding anodic oxide film) and the gate insulating film as masks. The dose amount is 1 × 10 ^{14 to} 5 × 10 ¹⁵ atom cm ⁻² , for example, 2 × 10 ¹⁵ atom cm ⁻² , and the acceleration energy is 10 to 10.
60 keV, for example, 40 kV. At this time, since the acceleration voltage was low, a sufficient amount of N-type impurity was implanted into regions 110 and 113, but a small amount of N-type impurity was implanted into regions 111 and 112 because the gate insulating film became an obstacle. Did not. As described above, the difference in the N-type impurity concentration and the nitrogen ion concentration causes the low-resistance region (source /
Drain regions) 110, 113, high-resistance regions 111, 1
No. 12 was formed. Phosphine (PH ₃ ) was used as a doping gas. (Fig. 2 (A))

Results of SIMS (Secondary Ion Mass Spectrometry)
According to this, the impurity concentration of the regions 110 and 113 is 1 × 10
²⁰~ 2 × 10^{twenty one}cm^-3, 1 × 1 in the regions 111 and 112
0¹⁷~ 2 × 10¹⁸cm^-3Met. In dose conversion,
The former is 5 × 10¹⁴~ 5 × 10 ^Fifteencm^-2The latter is 2 × 10
¹³~ 5 × 10¹⁴cm^-2Met. This difference is gate insulation
This is caused by the presence or absence of the film 104 '.
Generally, the impurity concentration of the low-resistance impurity region is
0.5 to 3 orders of magnitude larger than those in the range.

Subsequently, the entire surface is formed by a plasma CVD method.
A silicon nitride film 114 having a thickness of 20 to 200 nm
Was. This silicon nitride film is made of silane (SiH_Four) And ammonia
(NH _Three) At a substrate temperature of 250 to 40
It was formed at 0 ° C., typically 350 ° C. Silane and Ann
If the amount of silane is higher than that of Monia, silicon
Is excessive, that is, a trap cell that can capture a positive charge.
This results in a silicon nitride film having many intercepts. However, insulating
Is worse than a silicon nitride film having a small amount of silane. Sand
That is, the insulating properties are sufficient and some excess silicon is
A silicon nitride film that exists as a raster can be obtained
Thus, it is necessary to determine the ratio of silane to ammonia.
You. Specifically, considering the atomic ratio, Si / N = 10 /
It is desirable to set the ratio to be 1 to 2/1.

In addition, instead of this silicon nitride film, a three-layer structure having a structure in which a silicon film containing excess silicon is sandwiched by a general silicon nitride film (indicated by a composition ratio of Si ₃ N ₄ or similar) is used. It is also effective to employ a layer (film). Specifically, 1 to 10 nm, for example, 5 nm from the side contacting the active layer.
nm of a general silicon nitride film and 2 to 20 nm, for example, 10 nm.
It is also possible to adopt a structure in which an excess silicon film of silicon of 3 nm and a general silicon film of 10 to 100 nm, for example, 50 nm are laminated in three layers.

This is a configuration for achieving both the ability to capture positive charges and the insulating property. In this case, the insulating property is maintained by a general silicon nitride film (indicated by a composition ratio of Si ₃ N ₄ or a similar value), and the ability of silicon to capture a positive charge can be obtained by an excessive silicon film. it can.

The silicon nitride film 114 may be formed by a low pressure CVD method, or may be formed by implanting nitrogen ions into the silicon film. After the silicon nitride film 114 was formed in this manner, XeF excimer laser (wavelength: 355 nm, pulse width: 40 nsec) was irradiated to activate the impurity ions introduced into the active layer. Since a laser beam needs to pass through the silicon nitride film 114, a longer wavelength is preferable when an ultraviolet laser such as an excimer laser is used.

In this embodiment, an excimer laser is used as described above, but it goes without saying that another laser may be used. However, when using a laser, a pulsed laser is preferred. In the case of a continuous wave laser, the irradiation time is long, and there is a risk that an object to be irradiated is separated by expansion due to heat.

As for the pulse laser, Nd: YAG
Infrared laser such as laser (preferably Q-switched pulse oscillation) and its visible light such as its second harmonic, Kr
Various ultraviolet lasers using excimers such as F, XeCl, and ArF can be used. However, when laser irradiation is performed from the upper surface of the metal film, it is necessary to select a laser having a wavelength that is not reflected by the metal film. However, there is almost no problem when the metal film is extremely thin. Further, the laser light may be applied from the substrate side. In this case, it is necessary to select a laser beam that passes through the underlying silicon semiconductor film.

The laser annealing described above
Lamp annealing by irradiation of visible light or near-infrared light may be used. When performing lamp annealing,
So that the surface to be irradiated is about 600 to 1000 ° C.
Lamp irradiation is performed for several minutes at 600 ° C. and for several tens seconds at 1000 ° C. Near infrared (for example, 1.
Annealing with infrared light (2 μm) absorbs near-infrared rays selectively into the silicon semiconductor, does not heat the glass substrate so much, and shortens the time of one irradiation, thereby suppressing heating of the glass substrate. Very useful.

Thereafter, hydrogen is ion-doped.
Doped with ions. Acceleration energy is 10-50
kV, for example, 20 kV, and the dose amount is 1 × 10¹⁴~ 5x
10 ^FifteenAtom cm^-2, For example, 1 × 10^Fifteencm^-2And
This is because the silicon nitride film 114 contains hydrogen during normal thermal annealing.
This was done to keep out. At least source / dray
0.01 to 10 atoms in the area between the
% Of hydrogen is desirably opped. Also,
This hydrogen ion doping process was introduced earlier
Laser annealing (or lamp annealing) of impurities
It is desirable to carry out after the step.

Finally, as an interlayer insulator 115 on the entire surface,
The silicon oxide film is formed to a thickness of 200 nm to 1 μm by the CVD method.
m, for example, 300 nm. Further, contact holes were formed in the source / drain of the TFT, and aluminum wiring / electrodes 116 and 117 were formed. And 20
Annealing was performed at 0 to 400 ° C. in a nitrogen atmosphere.
In this step, the hydrogen atoms previously introduced by the ion doping method were activated. Thus, the TFT was completed. (Fig. 2 (C))

Embodiment 2 FIGS. 1 and 3 show this embodiment. A base film 102, an active layer 103, a gate insulating film 104 ', a gate electrode 105, and an anodic oxide 108 were formed on a glass substrate 101 by a process similar to that of the first embodiment. However, in this embodiment, the thickness of the gate insulating film (silicon oxide) is set to 100 to 150 nm, for example, 120 nm. As a result, the gate leak current is small, and it can withstand a high anodic oxidation voltage in a later process. (FIG. 1 (E))

Then, by ion doping, T
Nitrogen ions were implanted into the FT active layer 103 in a self-aligned manner using the gate electrode portion (that is, the gate electrode and the surrounding anodic oxide film) and the gate insulating film as masks. The dose amount is 1 × 10 ^{14 to} 3 × 10 ¹⁶ atoms cm ⁻² , for example, 2 × 1
And 0 ¹⁵ atoms cm ^-2, an acceleration voltage is 50～100KV, for example, was 80 kV. In this case, since the accelerating voltage is high, the active layer region 13 without the gate insulating film 104 'thereon is formed.
At 0 and 133, nitrogen ions are transmitted, and almost no nitrogen is doped into the active layer regions 130 and 133 (according to SIMS (secondary ion mass spectrometry) method, 1 × 1
0 ¹⁹ cm ^-3 or less. On the other hand, in the active layer regions 131 and 132 on which the gate insulating film is present, the concentration of nitrogen becomes maximum in this region, so that 5 × 10 ¹⁹ to 2 × 10 ^21.
Nitrogen at a concentration of atoms cm ^-3 (depending on depth) was introduced. (FIG. 3 (A))

Subsequently, using the anodic oxide 108 as a mask, the gate insulating film 104 ′ is etched to form a new gate insulating film 104 ″.
A silicon nitride film 124 having a thickness of 20 to 200 nm, for example, 100 nm was deposited on the entire surface by a plasma CVD method.
Further, N-type impurities were implanted into the active layer of the TFT by an ion doping method. The dose is 5 × 10 ^{14 to} 5
× 10 ¹⁵ cm ^-2 , and the acceleration voltage was 50 to 100 kV, for example, 80 kV. Phosphine (PH ₃ ) was used as a doping gas. As a result, regions 120 and 12
N-type impurities of the same amount were implanted into 1, 122, and 123 to form impurity regions. However, depending on the amount of the previously implanted nitrogen ions, the regions 120, 123
Is a low resistance region, whereas the regions 121 and 122 are high resistance regions. In the present embodiment, unlike the first embodiment, since the silicon nitride film is formed on the surface of the active silicon layer at the time of doping with phosphorus ions, the surface can be prevented from being roughened. (FIG. 3 (B))

Thereafter, irradiation with a XeF excimer laser (wavelength: 355 nm, pulse width: 40 nsec) was performed to activate impurity ions and nitrogen ions introduced into the active layer. According to the result of SIMS (secondary ion mass spectrometry), the concentration of phosphorus in the regions 120, 121, 122, and 123 was 1 × 10 ²⁰ to 2 × 10 ²¹ cm ⁻³ . In terms of dose amount, it was 5 × 10 ^{14 to} 5 × 10 ¹⁵ cm ⁻² .

Thereafter, hydrogen ions were doped by an ion doping method in the same manner as in Example 1. Finally,
A 300-nm-thick silicon oxide film was formed as an interlayer insulator 125 over the entire surface by a CVD method. Further, contact holes were formed in the source / drain of the TFT, and aluminum wiring / electrodes 139 and 140 were formed. And 2
Annealing was performed in a nitrogen atmosphere at 00 to 400 ° C.
Thus, the TFT was completed. This embodiment is different from the first embodiment in that a high-resistance region is formed by the concentration of the added resistance material (in this case, nitrogen). (FIG. 3 (C))

Using the method shown in FIGS. 1 and 3, 1
As an example in which a plurality of TFTs are formed on a single substrate, an active matrix type electro-optical device (for example, a liquid crystal display) is used to monolithically form a matrix region and a peripheral drive circuit for driving the matrix region on the same substrate. An example is shown in FIG. In this example, three TFTs 1 to 3 were formed. TFT1 and TFT2 are driver TFT
The thickness of the oxide corresponding to the anodic oxide 108 in FIG.
nm, and due to diffraction of impurity ions during ion doping, the gate electrode and the high resistance region (HRD)
Was made to overlap. In the figure, the drain of an N-channel type TFT 1 and the drain of a P-channel type TFT 2 are connected to each other by a wiring 503.
An example is shown in which a source of the TFT 1 is grounded and a source of the TFT 2 is connected to a power supply to form a CMOS inverter. There are various other peripheral circuits as well.
An S-type circuit may be used.

On the other hand, the TFT 3 is used as a pixel TFT, and one of the source / drain electrodes of the TFT 3 is connected to the pixel electrode 502 of ITO. The anodic oxide was 100 nm similarly to the TFTs 1 and 2, but the width y ′ of the high resistance region between the drain region and the gate electrode was 0.4 to 2 μm, for example, 0.5 μm.
The leakage current was suppressed. Conversely, in TFTs 1 and 2,
The width y of the high resistance region is smaller than that of the TFT 3, for example, 0.2 μm. Thus, the width of the high resistance region is set to T
To change the thickness by the FT, the thickness of the porous anodic oxide 107 may be changed by the TFT.
The gate wiring at the time of anodic oxidation may be separately controlled between T1 and T2 and the TFT3 so that they can be controlled independently. In addition, in the TFT 3 for the pixel as described above, since the width of the high-resistance region is large, the parasitic capacitance between the gate and the drain due to the application of the voltage can be reduced. This is preferable for use as a pixel TFT.

Since the TFTs 1 and 3 are of the N-channel type, the manufacturing method of this embodiment may be used.
Since T2 is a P-channel type, it is not preferable in terms of characteristics to employ the process of this embodiment as it is. That is, in the case of the N-channel type TFT, the gate insulating film 104 'is etched along the gate electrode portion at the stage of transition from FIG. Such a process is not performed in the type TFT because the silicon nitride film 501 (corresponding to the silicon nitride film 124 in FIG. 3 ) may be in contact with the high-resistance region. , Silicon nitride film 5
01 traps positive charges, so that the P-channel type TF
In the case of T by the presence of the silicon nitride film 124, since the high resistance region is inverted into N-type, it prevents the current between the source over scan / drain. Therefore, the P-channel type has a shape as shown in the figure.

Embodiment 3 FIG. 5 shows an N-channel type TFT.
An example in which is formed will be described. First, a base oxide film 202 is formed on a substrate (for example, Corning 7059) 201 having an insulating surface by using the steps of FIGS.
Island-shaped silicon semiconductor region (for example, a crystalline silicon semiconductor having a thickness of 80 nm) 203, and a silicon oxide film 20 having a thickness of 120 nm
4. a gate electrode 205 made of an aluminum film (thickness: 200 nm to 1 μm) and a porous anodic oxide (thickness: 300 nm to 1 μm, for example, 500 nm) on the side surface of the gate electrode;
06 was formed. (FIG. 5 (A)) Then, similarly to the first embodiment, the thickness of the barrier mold is 100 to 25.
A 0 nm anodic oxide 207 was formed. (FIG. 5 (B))

Further, using the porous anodic oxide 206 as a mask, the silicon oxide film 204 was etched to form a gate insulating film 204 '. After that, the barrier type anodic oxide film 2
07, the porous anodic oxide film 206 was removed by etching. Thereafter, the gate electrode portions (205, 20)
7) and impurity implantation is performed by ion doping using the gate insulating film 204 ′ as a mask to form low-resistance impurity regions 208 and 211, high-resistance impurity regions 209 and
10 was formed. Dose amount is 1-5 × 10 ¹⁴ atoms c
m ^-2 and the acceleration voltage were 30 to 90 kV. Phosphorus was used as an impurity. (FIG. 5 (C))

Further, a coating of a suitable metal, for example, titanium, nickel, molybdenum, tungsten, platinum, palladium, etc., for example, a titanium film 212 having a thickness of 5 to 50 nm was formed on the entire surface by sputtering. As a result, the metal film (here, titanium film) 212 was formed in close contact with the low-resistance impurity regions 208 and 211. (FIG. 5
(D))

Then, a KrF excimer laser (wavelength: 248 nm, pulse width: 20 nsec) is irradiated to activate the doped impurities and to react the metal film (here, titanium) with the silicon of the active layer to form a metal silicide ( Here, regions 213 and 214 of (titanium silicide) were formed.
Laser energy density is 200-400mJ / cm
² , preferably 250 to 300 mJ / cm ² . When the laser is irradiated, the substrate is 200 to 500
By heating to ℃, the peeling of the titanium film could be suppressed.

Thereafter, the titanium film was etched with an etching solution in which hydrogen peroxide, ammonia and water were mixed at a ratio of 5: 2: 2. Titanium films other than those in contact with the exposed active layer (for example, the gate insulating film 204 'and the anodic oxide film 207)
Since the titanium film existing on the upper surface remains in a metal state as it is, it can be removed by this etching. On the other hand, titanium silicides 213 and 214, which are metal silicides, are not etched and can be left.

Thereafter, the gate insulating film 204 'is etched by dry etching using the gate electrode portion as a mask to form a new gate insulating film 204 "having a shape leaving 20 to 50 nm. Then, the plasma CV is formed.
By the method D, a silicon nitride film 217 having a thickness of 200 to 200 nm was formed on the entire surface. In this embodiment, the second embodiment
Unlike silicon nitride film formation, the high-resistance regions 209, 2
Since a thin silicon oxide film remains on the substrate 10, damage at the time of film formation can be reduced. (FIG. 5E)

Thereafter, hydrogen ions were doped into the active layer by an ion doping method. Finally, FIG.
As shown in (F), an interlayer insulator 218 is formed on the entire surface.
The silicon oxide film is formed to a thickness of 200 nm to 1 μm by the CVD method.
m, for example, 300 nm, a contact hole is formed in the source / drain of the TFT, and an aluminum wiring
The electrodes 219 and 220 are set to 200 nm to 1 μm, for example, 50
It was formed to a thickness of 0 nm.

In this embodiment, the portion where the aluminum wiring contacts is made of titanium silicide, and the stability of the interface with aluminum is better than that of silicon, so that a highly reliable contact was obtained. Further, when titanium nitride is formed as a barrier metal between the aluminum electrodes 219 and 220 and the silicide regions 213 and 214, the reliability can be further improved. In this example, the sheet resistance in the silicide region was 10 to 50 Ω / □. On the other hand, in the high-resistance impurity regions 209 and 210 having the same conductivity type as the source / drain, the resistance was 10 to 500 kΩ / □.

Further, the high-resistance region is formed via a silicon oxide film.
Since it is covered with the silicon nitride film 217, entry of mobile ions such as sodium from the outside is prevented. Further, as described above, the silicon nitride film 217 traps the positive charges, thereby canceling the effect of the negative charges trapped in the silicon oxide film thereunder.

In this embodiment, the low-resistance impurity region 211 and the metal silicide region 214 can be substantially matched.
In particular, the end 215 of the gate insulating film 204 ′ and the boundary 216 between the high-resistance impurity region 210 and the low-resistance impurity region 211 substantially coincide with each other, and at the same time, the end 215 and the end of the metal silicide region 214 substantially coincide with each other. Was completed.

As an example in which a plurality of TFTs are formed on one substrate using the method shown in FIG. 5, an active matrix type electro-optical device (for example, a liquid crystal display)
FIG. 8B shows an example in which a matrix region and a peripheral drive circuit for driving the matrix region are monolithically formed on the same substrate.
Shown in In this example, three TFTs 1 to 3 were formed. TFT1 and TFT2 are CM as driver TFT
The thickness of the oxide corresponding to the anodic oxide 207 in FIG. 2 was set to 20 to 200 nm, for example, 100 nm, which was used as an OS configuration, here, an inverter configuration. On the other hand, the TFT 3 is used as a pixel TFT, and the thickness of the anodic oxide is set to 100 nm. TF
One of the source / drain electrodes of T3 is connected to the pixel electrode 505 of ITO. Reference numeral 506 denotes an output terminal of the inverter, and 504 denotes a silicon nitride film (corresponding to 217 in FIG. 5).

With respect to the anodic oxide, the thickness of the anodic oxide was selected so that the end of the gate electrode and the end of the source / drain region coincided with each other in consideration of the wraparound during ion implantation. One of the source / drain electrodes of TFT3 is ITO
Are connected to the pixel electrode 502. In the TFT 3, the width y ′ of the high resistance region is set to 0.4 to 5 μm, for example, 0.5 μm.
On the other hand, in TFTs 1 and 2, the width y was shorter than that, for example, 0.2 μm. In order to change the width of the high resistance region by the TFT as described above, the porous anodic oxide 2
The thickness of 06 may be changed depending on the TFT, and for this purpose, the TFTs 1 and 2 and the TFT 3 may be controlled independently of each other by using a separate wiring for anodic oxidation. Note that TFT1 and TFT3 are N-channel TFTs.
FT and TFT2 are P-channel TFTs. As described above, in the pixel TFT 3, since the width of the high-resistance region is large, the parasitic capacitance between the gate and the drain due to the application of the voltage can be reduced. This is preferable for use as a pixel TFT.

The TFTs 1 and 3 which are N-channel TFTs were manufactured by the process shown in this embodiment.
The difference from T1 and T3 is due to the same reason as described in the second embodiment. In this embodiment, the step of forming a titanium film is provided after the step of ion doping, but the order may be reversed. In this case, since the titanium film covers the entire surface at the time of ion irradiation, the effect is large in preventing abnormal charging (charge-up) which has become a problem in the insulating substrate. After the ion doping, annealing may be performed by a laser or the like, and then a titanium film may be formed. Then, titanium silicide may be formed by irradiation with a laser or the like or thermal annealing.

Embodiment 4 FIG. 6 shows this embodiment. First, on the substrate (Corning 7059) 301, the base oxide film 302, the island-shaped crystalline semiconductor region, for example, the silicon semiconductor region 303 is formed on the substrate (Corning 7059) 301 by using the steps of FIGS. Silicon oxide film 304, aluminum film (thickness 2
00 nm to 1 μm) and a porous anodic oxide (600 nm thick) 30 on the side surface of the gate electrode 305.
6. Further, a barrier type anodic oxide 307 was formed between the gate electrode 305 and the porous anodic oxide 306.
(FIG. 6 (A))

Further, using the porous anodic oxide 306 as a mask, the silicon oxide film 304 was etched to form a gate insulating film 304 '. Then, the porous anodic oxide 30
6 was etched to expose a part of the gate insulating film 304 '. Then, an appropriate metal, for example, a titanium film 308 having a thickness of 5 to 50 nm was formed on the entire surface by sputtering. (FIG. 6 (B))

Then, by ion doping, T
N-type impurities were implanted into the FT active layer. The dose is 5
× 10 ¹⁴ -5 × 10 ¹⁵ cm ^-2 , acceleration energy is 10
30 keV. At this time, since the accelerating voltage was low, a sufficient amount of N-type impurity was implanted into the regions 309 and 312, but the gate insulating film hindered the region 31 and 312.
Only a small amount of N-type impurities were implanted into 0 and 311. As described above, depending on the difference between the N-type impurity concentration and the carbon ion concentration, the low-resistance region (source / drain region)
309, 312 and high resistance regions 310, 311 were formed. Phosphine (PH ₃ ) was used as a doping gas. (FIG. 6 (D))

Then, a KrF excimer laser (wavelength: 248 nm, pulse width: 20 nsec) is irradiated to cause a reaction between titanium and silicon in the active layer.
314 was formed, and the impurities doped in the regions 310 and 311 were activated. The energy density of the laser was 200 to 400 mJ / cm ² , and preferably 250 to 300 mJ / cm ² . In addition, when the substrate was heated to 200 to 500 ° C. during laser irradiation, peeling of the titanium film could be suppressed.
This step may be performed by lamp annealing by irradiation with visible light or near infrared light.

Thereafter, the titanium film was etched with an etching solution in which hydrogen peroxide, ammonia and water were mixed at a ratio of 5: 2: 2. A titanium film (for example, a gate insulating film 304 ′) other than a portion which is in contact with the exposed active layer and becomes titanium silicide.
And the titanium film present on the anodic oxide film 307 remain in a metal state as it is, and can be removed by this etching. On the other hand, the titanium silicides 317 and 318 are not etched and can be left. Thereafter, the gate insulating film 304 'is etched by dry etching using the gate electrode portion as a mask to form a new gate insulating film 304 ". Then, a 20 to 200 nm thick film is formed by plasma CVD. Silicon nitride film 315
Was formed on the entire surface. (FIG. 6E)

Thereafter, the active layer was doped with hydrogen ions by an ion doping method, and annealed in a nitrogen atmosphere. Then, CV is applied as an interlayer insulator 316 on the entire surface.
A silicon oxide film is formed to a thickness of 600 nm by the D method,
Contact holes were formed in the source / drain of T, and aluminum wiring and electrodes 317 and 318 were formed. Through the above steps, a TFT having a high resistance region was completed. (FIG. 6 (F))

FIG. 8C shows an example (cross-sectional view) in which a TFT is used for a pixel of an active matrix liquid crystal display device by the manufacturing process shown in FIG. In the figure, area 50
Reference numeral 7 denotes a TFT region, a region 508 denotes a storage region for supplementing the capacitance of the pixel electrode, and a region 509 denotes a contact region of the first and second wiring layers. As is clear from the figure, T
A silicon nitride film 512 is provided so as to cover the active silicon layer and the gate electrode of the FT and the wirings 510 and 511 (both of which have an anodic oxide film formed on the surface) in the same plane as the gate electrode. ing. Then, an interlayer insulator 513 is formed on the silicon nitride film.

The source electrode 516 and the drain electrode 517 of the TFT are connected to the pixel electrode 514 of ITO, 517. The interlayer insulator 513 covering the wiring 510 is in the region 5
In FIG. 15, the pixel electrode 514 and the wiring 510 are removed.
Are opposed to each other with the anodic oxide film and the silicon nitride film 512 interposed therebetween to form a capacitor. In this case, a large capacitance can be obtained in a small area because the distance between the electrodes is narrow and the dielectric constant of both silicon nitride and the anodic oxide film (aluminum oxide) is large. Interlayer insulator 51 on wiring 511
3, the silicon nitride film 512, and the anodic oxide film are removed by etching to form contact holes, which are in contact with the second-layer wiring 518 that is the same as the source / drain electrodes.

Embodiment 5 FIG. 7 shows this embodiment. First, on a substrate (Corning 7059) 401, a base oxide film 402, an island-shaped crystalline semiconductor region such as a silicon semiconductor region 403, a silicon oxide film 404, and an aluminum film (thickness 20)
(0 nm to 1 μm) to form a gate electrode 405.
(FIG. 7A) Then, a porous anodic oxide (thickness: 600 nm) 406 was formed on the top and side surfaces of the gate electrode. The conditions of the anodic oxidation were the same as the conditions for forming the anodic oxide 107 of Example 1. (FIG. 7B) Further, the gate electrode 405 and the porous anodic oxide 40
6, a barrier-type anodic oxide 407 was formed. (FIG. 7 (C))

Thereafter, using the porous anodic oxide 406 as a mask, an N-type impurity was implanted into the active layer of the TFT by ion doping. The dose is 5 × 10 ^{14 to} 5
× 10 ¹⁵ cm ^-2 , acceleration energy is 40-100 keV
And Phosphine (P
H ₃₎ was used. Through the above-described steps, low-resistance regions (source / drain regions) 408 and 409 and a high-resistance region (offset region, not shown) having substantially the same conductivity type as the channel formation region and less affected by the gate electrode were formed. . The width z of the offset region is anodic oxides 406 and 4
07. (FIG. 7 (D))

Further, the porous anodic oxide 406 was removed by etching to expose the surface of the barrier anodic oxide 407. Then, a KrF excimer laser (wavelength 35
Irradiation of 5 nm and a pulse width of 40 nsec) was performed to activate the doped impurities. The energy density of the laser was 200 to 400 mJ / cm ² , and preferably 250 to 300 mJ / cm ² . Further, the substrate may be heated to 200 to 500 ° C. during laser irradiation. This step may be performed by lamp annealing by irradiation with visible light or near infrared light. And
A silicon nitride film 410 is formed on the entire surface by a plasma CVD method.
The thickness was 20 to 200 nm, for example, 100 nm. Further, hydrogen ions were implanted by an ion doping method, and activated by annealing in a nitrogen atmosphere. (FIG. 7E)

Finally, as shown in FIG. 7F, a silicon oxide film having a thickness of 600 nm is formed on the entire surface as an interlayer insulator 411 by a CVD method, contact holes are formed in the source / drain of the TFT, and nitrided. The multilayer wiring / electrodes 412 and 413 of titanium and aluminum were formed. Through the above steps, a TFT was completed.

[0073]

According to the present invention, in an N-channel TFT, a high-resistance region (HRD), that is, a weak N-type region or an offset region is formed in a self-aligning manner and is formed on or in the region. By forming a film (for example, a silicon nitride film) capable of trapping positive charges on the silicon oxide film over the region, it was possible to prevent generation of a parasitic channel generated in the high resistance region. The present invention was particularly effective in preventing a decrease in mobility at a drain voltage of several volts. For this reason, when such an N-channel TFT is used as a pixel transistor of a liquid crystal display device, a delicate voltage can be controlled, and it is preferable to reproduce a delicate halftone image. .

It can be said that the TFT of the present invention is formed in the same manner when a three-dimensional integrated circuit is formed on a substrate on which a semiconductor integrated circuit is formed, or when formed on glass or an organic resin. In any case, it is characterized in that it is formed on an insulating surface. In particular, the effect of the present invention is remarkable for an electro-optical device such as a monolithic active matrix circuit having peripheral circuits on the same substrate. That is, the TFT according to the present invention has the characteristics of low reverse leakage current, high withstand voltage, and high reliability (the degree of deterioration is small). It is effective when used.

[Brief description of the drawings]

FIG. 1 illustrates a general process of the present invention.

FIG. 2 shows a method for manufacturing a TFT according to Example 1.

FIG. 3 shows a method for manufacturing a TFT according to Example 2.

FIG. 4 illustrates a structure of a TFT of the present invention.

FIG. 5 shows a method for manufacturing a TFT according to a third embodiment.

FIG. 6 shows a method for manufacturing a TFT according to Example 4.

FIG. 7 shows a method for manufacturing a TFT according to a fifth embodiment.

FIG. 8 shows an example of an integrated circuit of a TFT obtained according to Examples 1 and 3.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 101 Insulating substrate 102 Base oxide film (silicon oxide) 103 Active layer (crystalline silicon) 104 Insulating film (silicon oxide) 104 'Gate insulating film 105 Gate electrode (aluminum) 106 Mask film (photoresist) 107 Anodic oxide (porous) Aluminum oxide) 108 Anodic oxide (barrier type aluminum oxide) 109 Edge of gate insulating film

Claims (7)

(57) [Claims] 1. A semiconductor device having an N channel type thin film transistor and a P-channel thin film transistor on an insulating surface, the N-channel type thin film transistor and the P
Each of the channel type thin film transistors includes a gate electrode, an oxide layer provided on the side and top surfaces of the gate electrode, a gate insulating film existing under the gate electrode, and a channel formed under the gate insulating film. A region, a pair of high-resistance regions adjacent to the channel forming region, and a pair of low-resistance regions provided outside the high-resistance region; A silicon nitride film in which silicon is present , wherein the p-channel thin film transistor
A semiconductor device, wherein a silicon film is provided so as not to contact the high-resistance region . 2. A semiconductor device having an N-channel thin film transistor and a P-channel thin film transistor on an insulating surface, wherein the N-channel thin film transistor and a P-channel thin film transistor
Each of the channel type thin film transistors includes a gate electrode, an oxide layer provided on side surfaces and an upper surface of the gate electrode, and a gate made of silicon oxide present under the gate electrode.
An insulating film, a channel formation region existing below the gate insulating film , a pair of high resistance regions adjacent to the channel formation region, and a pair of low resistance regions provided outside the high resistance region. It has, and, on the high resistance region, and a silicon nitride film excess silicon is present is provided in the P-channel type thin film transistor, the high resistance
The gate insulating film exists on the anti-region, and the silicon nitride film
Is a semiconductor device provided on the gate insulating film . 3. The semiconductor device according to claim 1, wherein the width of the high resistance region is 0.4 to 5 μm. 4. The method according to claim 1, wherein
A semiconductor device comprising a CMOS inverter in which a channel type thin film transistor and the P channel type thin film transistor are connected. 5. The method according to claim 1, wherein:
The semiconductor device, wherein the excess silicon exists as a cluster. 6. The method according to claim 1, wherein
The composition ratio of the silicon nitride film is Si / N = 10/1 to 2 /
1. A semiconductor device, which is 1. 7. The method according to claim 1, wherein
Active Ma <br/> preparative Riku scan type electro-optical device characterized by using the semiconductor device.