JP3361165B2 - Information recording / reproducing device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a zone CAV system in which a recording area of a recording medium is divided into a plurality of zones, and recording / reproduction is performed by changing a recording frequency for each zone. The present invention relates to an information recording / reproducing apparatus for reading / writing from / to a disc. 2. Description of the Related Art In recent years, optical information recording / reproducing apparatuses capable of recording or reproducing information at a high density by optically recording or reproducing information using a light beam have become widespread.
FIG. 5 shows a first conventional example of an information recording / reproducing apparatus disclosed in JP-A-3-232163. FIG. 5 is a block diagram showing an information recording / reproducing apparatus of the zone CAV system. As the zone CAV type disk, for example, a magneto-optical disk is used, and its track is divided into a plurality of zones in order to take a large recording capacity. That is, by increasing the recording frequency (read / write clock) in the zone on the outer peripheral side,
The recording density on the outer peripheral side is increased, and the recording capacity is increased. Here, the address detection circuit 81 detects the last sector by reading the ID section address of each sector existing in the zone, and outputs this detection signal to the frequency switching control circuit 82. The frequency switching control circuit 82 receives the detection signal of the last sector of each zone of the address detection circuit 81,
A control signal for switching to a frequency for each zone is output. The frequency switching control circuit 82 outputs a frequency switching signal and frequency-divided data for setting the clock frequency of the next zone to the synthesizer 83. When receiving the frequency switching signal, the synthesizer 83 divides the frequency of the system clock, which is the reference clock for the operation of the device, by the value specified by the frequency-divided data, and generates the frequency clock for the next zone. This synthesizer 83 also generates a recording / erasing reference clock. The gate circuit 86 includes a frequency switching control circuit 8
2 and a circuit which is connected between the synthesizer 83 and inhibits input of a frequency switching signal to the synthesizer 83 during recording by the apparatus. The W-GATE signal is supplied to the gate circuit 8
6, a frequency switching signal is output to the synthesizer 83 at the timing of the W-GATE signal, and a clock frequency corresponding to each zone is set. In the drawings, reference numerals 84 and 85 denote a PLL circuit and a demodulation circuit. FIG. 6 shows a second conventional example disclosed in JP-A-3-237664. FIG. 6 is a block diagram of the information recording / reproducing apparatus, and FIG. 7 shows a time chart thereof. In the block diagram of FIG. 6, reference numeral 91 denotes an SM for detecting a sector mark recorded at the head of each sector.
It is a detection circuit. Reference numeral 92 denotes an address detection circuit for detecting address information recorded in the header section of each sector, an AM detection circuit 93 similarly an address mark detection circuit for detecting address marks recorded in the header section of the sector, and 94 a reproduction signal of the sector. A PLL circuit 95 for synchronization is a MODEM for demodulating the address information of the reproduction signal. Next, the operation of the configuration shown in FIG. 6 will be described with reference to FIG. FIG. 7A shows a reproduction signal pattern. Here, when the apparatus is started, first, a recording medium such as an optical disk is rotationally driven by a spindle motor (not shown), and when a predetermined number of rotations is reached, a semiconductor laser (not shown) is turned on. When the focus and tracking servo systems are driven, the reproduction of the reproduction pattern of the recording medium becomes possible. In this state, first, S
The M detection circuit 91 sets a detection section for detecting the sector mark pattern shown in FIG. In this example, as shown in FIG. 7C, the SM window signal for setting the detection section is set to a high level so as to be valid. When the SM detection circuit 91 detects the sector mark pattern, it sets the SM window signal to a low level as shown in FIG. 7C, and inhibits the detection of the sector mark pattern. At the same time, the SM detection circuit 91 outputs an SM signal, which is a detection signal of the sector mark pattern, to the AD detection circuit 92 as an address detection command. Upon receiving the SM signal, the AD detection circuit 92 obtains address data by
The RG signal as shown in FIG.
The signals are output to the PLL circuit 94 and the MODEM 95, respectively. When the PLL circuit 94 receives the RG signal,
The signal is output to the AM detection circuit 93 and the MODEM 95. The AM detection circuit 93 includes an RG signal and a PLL circuit 94.
, And outputs an AM signal as a detection signal to the MODEM 95 as shown in FIG. [0013] MODEM95 is an RG signal, an AM signal,
The address data A is output by a signal from the PLL circuit 94.
The DR is demodulated, and the demodulated data of the address data shown in FIG. AD detection circuit 2
Detects the address data from the demodulated data, and if the address data is detected correctly, ADR-RD as shown in FIG.
The Y signal is output to the SM detection circuit 91. At the same time, this signal is sent to a CPU (not shown) which manages the entire apparatus.
The SM detection circuit 91 executes the above-described series of operations after detecting the SM, and finally receives the ADR-RDY signal indicating that the detection of the address data is completed, and then detects the SM detected earlier.
Is determined to be true. After determining that SM is true, the SM detection circuit 91 intermittently counts the reference clock to generate the next SM window signal. Then, by counting a predetermined number of reference clocks, the SM of the next sector is counted.
At the timing of the detection, the operation of validating the SM window signal is performed again. However, in the method of the first conventional example, when reading and writing near the boundary area of a zone and switching to an adjacent zone, the frequency of the read / write clock is changed to the previous frequency. When a window used for detecting a preformat signal is opened to perform switching in the middle of a zone, the following problem occurs. That is, a window used for detecting a preformat signal in a head sector of a zone, such as a sector mark or an address mark, at a fixed clock count number such as CAV opens a window too early. Therefore, the signal recorded in the preformat part of the disc while the window is open cannot be detected,
Problems such as failure to detect preformat data may occur. Further, since the synthesizer 83 also generates a recording / erasing reference clock, there is a problem that the recording / erasing reference clock is changed along with changing the frequency of the read / write clock in the middle of the previous zone. In this case, it is possible to configure so that the recording / erasing reference clock is not changed, but it is necessary to construct an extra circuit configuration, which leads to an increase in cost. In the case of the second conventional example, when the read / write frequency is different for each zone such as the zone CAV, the timing for opening the window for detecting the ID portion is shifted. However, while the window is open, the signal of the preformat section and the data section cannot be detected. The present invention has been made in order to solve such a problem. In a zone CAV disk, an information recording system capable of reliably detecting a signal preformatted in the first sector of the next adjacent zone. It is an object to provide a playback device. In order to achieve the above object, in a zone CAV disk, an address detecting means for detecting the last sector of the zone and a window for detecting a preformat signal are provided. Control means for controlling the timing of opening the memory, and counting means for counting the read / write clock in each zone. When performing continuous read / write of an adjacent zone,
By switching to the frequency of the read / write clock between the last sector of the zone and the beginning of the next zone, and taking into account this switching, the timing is controlled so that the window is opened at the next ID section, thereby achieving the zone CAV method. In such a disc, a preformat signal such as a sector mark and an address mark existing at the head of the next zone can be reliably read. Embodiments of the present invention will be described below with reference to the drawings. FIGS. 1 to 3 relate to a first embodiment of the present invention. FIG. 1 is a block diagram showing a configuration of a signal processing system in an optical disk recording / reproducing apparatus according to the first embodiment. FIG. 3 shows a part of the standard of the 130 mm zone CAV. In the information recording / reproducing apparatus according to the present invention, the recording / reproducing apparatus refers to an apparatus having at least one function of reproducing, recording, and erasing processes. An optical head is arranged to face an optical disk such as a magneto-optical disk which is rotated by a spindle motor (not shown). The optical head is movable in the radial direction of the optical disk by a head moving mechanism. This optical disk is divided into a plurality of zones, and a zone C in which recording is performed by changing the recording frequency for each zone.
This is an AV optical disk (hereinafter, referred to as a zone CAV disk). FIG. 3 shows the relationship between each zone Band in the 130 mm zone CAV disc and the (first) track radius in the zone Band. In this 130 mm zone CAV disk,
The zone Band used for recording information is the innermost Bn.
16 zones B from ad0 to the outermost Band15
For example, the innermost zone Band0 starts with a normal radius of 30.000 mm, and has a normal radius of 30.000 mm.
It ends at 1.877 mm, and moves from this 31.877 mm to the next zone Band1. By performing recording at a recording frequency proportional to the track radius of each zone Band, the recording density on the outer peripheral side is increased and the recording capacity is increased. Also,
For example, from the innermost zone Band0 to the next zone Ban
When shifting to d1, the recording frequency is switched to a higher frequency by about 6%. The reproduced signal from the zone CAV disk is read by the PLL circuit 1 shown in FIG.
A clock synchronized with the clock in the FO area is generated, and a signal recorded in synchronization with the clock is extracted from the reproduced signal input to the demodulation circuit 2. The output signal output from the demodulation circuit 2 is input to an address detection circuit 3, which detects a sector mark signal recorded at the head of a sector ID portion in each zone (FIG. Further, the address information recorded after the VFO and the address mark (FIG. 7A)
ADR) of the zone is detected to detect that it is the last sector of the zone.
The last sector detection signal is output to the write clock counter. An address signal is also input to the frequency switching control circuit 4. When the last sector detection signal and the address signal are input from the address detection circuit 3, the frequency switching control circuit 4 outputs frequency-divided data for setting the clock frequency switching to the synthesizer 6 and follows the ID section. At the end position of the data section, the read / write clock output from the synthesizer 6 is switched to the read / write clock corresponding to the next zone. The synthesizer 6 has a circuit function of generating a read / write clock having a frequency corresponding to each zone from the frequency-divided data and a clock generation circuit for generating a recording / erasing reference clock. The read / write clock counter 5
Immediately after the last sector detection signal is input from the address detection circuit 3,
It starts counting the write clock and outputs the count value to the window control circuit 7. The window control circuit 7 is set so that the count value of the read / write clock counter 5 is turned on / off (open / closed) at a predetermined value. An ID section read permission signal (window) for permitting detection is output. When it is turned off (closed), a signal (reset signal) for resetting the counter value is sent to the read / write clock counter 5. The window control circuit 7 sets the timing of the count value at which the window opens at the head of the next ID section in consideration of the read / write clock switching timing. In this embodiment, the clock frequency is switched to the clock frequency of the next (N + 1) zone at the timing of passing through the data section of the last sector of the N zone, and the clock frequency is set to a higher clock frequency by this switching. Therefore, if the window is set to be opened when the count value of the read / write clock reaches a certain set value without considering the switching, the window is opened before the next ID section is reached. If the window is closed for a certain period, the window will be closed before reading the ID section. The opening and closing of the window in this case is shown by a window at the conventional timing in FIG. As described above, in this embodiment, at the timing of passing through the data section of the last sector of the N zone, the next N + 1
In consideration of switching to set a higher clock frequency of the zone, the window is set to be opened when a predetermined number of clocks are counted extra than the conventional timing. Fig. 2
(E) shows a window delayed by n clocks. The read / write clock counter 5 is set so as to be reset at the fall of the window for permitting the detection of the ID portion. Next, the operation of this embodiment will be described with reference to the time chart of FIG. FIG. 2A shows a disk format. Here, the vicinity of the boundary between the N and N + 1 zones is enlarged. A buffer serving as a buffer area is provided between the last sector of the N zone and the first sector of the N + 1 zone. First, when the reproduction signal has read the ID portion of FIG. 2A, a final sector detection signal for recognizing the last sector of the zone is output from the address detection circuit 3 (FIG. 2B). ). After counting the number of pulses of the data portion (the number of pulses of the data portion is stored in the ROM or the like) from the pulse of the last sector detection signal, at the timing when the pulse reaches the buffer unit in FIG. The frequency switching control circuit 4 outputs the frequency-divided data of the (N + 1) th zone to the synthesizer 6. The divided data may be output before the above timing, and an instruction signal for instructing the switching of the read / write clock (using the divided data) may be output at the timing approaching the buffer unit. . The counting of the number of pulses in the data portion may be performed by a counter in the frequency switching control circuit 4 or the timing of switching from the output of the read / write clock counter 5 may be determined. Based on the frequency-divided data, the synthesizer 6 switches the read / write clock to the frequency of the next N + 1 zone (clock switching point (c) in the figure). Therefore, data is read from the buffer after the last sector of the N zone.
Since the write clock frequency is switched to the clock frequency of the (N + 1) th zone, the window control circuit 7 delays the window opening timing by n clocks from the conventional timing of FIG. The window is prevented from closing ((e) in the figure). Instead of FIG. 2 (e), the timing of opening the window is the same as the conventional timing of FIG. 2 (d),
Conversely, the timing of closing the window may be delayed (counting is performed for m clocks) ((f) in the figure). FIG. 2D shows a conventional timing window to clarify the features of this embodiment. This is to detect the preformat information of the ID part,
This corresponds to a window opening / closing operation in a case where a window is opened at a timing at which the occurrence of the next ID portion is expected from the detection signal of the ID portion without considering that the zone CAV. As described above, since the zone CAV is not taken into consideration, and the clock frequency increases during the counting, the window is opened earlier than appropriate timing. It will be before you finish reading the section. On the other hand, the number of clocks to be delayed from the conventional timing, n or open at the same timing as the conventional timing,
The number m of clocks for changing the period during which the window opens so as to lengthen the closing timing will be described using a specific example. For example, in the case of 2-7 modulation, assuming continuous reading / writing from the innermost circumference (Band0) of the zone to Band1, if the read / write clock is not changed in the last sector buffer section of Band0, the buffer section is used. Is 192 clocks (12Byte * 8 * 2)
It becomes. However, as in this embodiment, the clock frequency is changed by the last sector buffer of Band 0 to Band
Switching to a clock frequency of 1 increases the clock by approximately 6% (12 clocks). As a result, if the window is opened and closed at the conventional timing, the timing of the increase (12 clocks) is deviated, and the I
The window closes while the D section is being detected, and the information of the ID section cannot be read. Therefore, the window opening timing is delayed by 12 clocks or is counted extra, and the window is opened longer to correct the window opening period (the window opening period during the ID portion reading period). State.) As described above, n is a variable for delaying the opening of the window for 12 clocks, and m is for opening the window long for 12 clocks (counts extra).
Is a variable. According to the first embodiment, when performing continuous read / write of an adjacent zone in a zone CAV disk, the final position of the data portion of the last sector of the previous zone (in other words, the final position At the beginning of the buffer section adjacent to the zone), the read / write clock is switched to the frequency of the next zone, and the window opening timing is changed to read the information of the preformat section existing in the first sector of the zone. This prevents the window from closing in the middle and making address marks and sector marks unreadable. FIG. 4 shows a second embodiment of the present invention. In this embodiment, the read / write clock counter 5 is not provided and the last sector detection signal from the address detection circuit 3 is input to the window control circuit 7 'in FIG. The read / write clock from the synthesizer 6 is input to the window control circuit 7 '. The window control circuit 7 'includes the read / write clock counter 5 and the window control circuit 7 shown in FIG.
It has the function of The operation and effect of this embodiment are almost the same as those of the first embodiment. In the above-described embodiment, the clock switching point at which the clock is switched is described as the timing after the last position of the data section of the last sector or the timing when the head reaches the next buffer section. If there is unevenness or the like, the clock switching point may actually deviate slightly from the above timing, and this deviation will slightly deviate the window opening / closing timing. For example, as shown in FIG.
If it is set correctly to open at the end of the part, if the start of the next zone is rotated quickly from the last sector part due to uneven rotation of the disk, the window will open after hitting the next ID part It is also expected. Therefore, considering the influence of the uneven rotation of the disk, even if the maximum allowable uneven rotation occurs, the window should be located forward of the end of the buffer so that the above-mentioned inconvenience does not occur. The window may be set to be opened at the timing so that the next ID section is reached after the window is opened even if there is uneven rotation. The timing for closing the window is also I
It may be shifted to the rear side from the part D. The timing of closing the window may be determined based on a detection signal of a sector mark detected while the window is open. Since the synthesizer 6 is also used to generate a recording / erasing reference clock, it is not desirable to switch the clock in the middle of the data section.
In this case as well, considering the effect of uneven rotation of the disk,
Instead of performing the switching accurately at the final position of the data section, the clock switching may be performed at a timing slightly after the beginning of the buffer section or at the center position of the buffer section, for example. This makes it possible to prevent the recording / erasing reference clock from being changed during data recording or the like in the data section even if rotational unevenness exists. That is, clock switching is performed in the buffer area between the last sector of the zone and the head of the sector in the next zone, and the timing of opening the window and the opening / closing period of the window are set in consideration of the switching. As a result, it is possible to set the window to be opened in the next ID section even if there is uneven rotation or the like, and it is possible to perform recording on the data section of the last sector without any trouble. As described above, according to the present invention,
When performing continuous read / write of an adjacent zone in a zone CAV type disk, the read / write clock frequency of the next zone is switched in the buffer section after the data section of the last track, and the clock is used. It controls the timing of the window for detecting the preformat signal in the first sector of the next zone. This makes it possible to reliably detect information preformatted on the disk, such as a sector mark and an address mark existing in the first sector of the next zone.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a configuration of a signal processing system in an optical disc recording / reproducing apparatus according to a first embodiment of the present invention. FIG. 2 is a timing chart for explaining the operation of FIG. 1; FIG. 3 is an explanatory view showing a part of the standard of a 130 mm zone CAV. FIG. 4 is a block diagram showing a configuration of a signal processing system in an optical disc recording / reproducing apparatus according to a second embodiment of the present invention. FIG. 5 is a block diagram of a first conventional optical disc recording / reproducing apparatus. FIG. 6 is a block diagram of a second conventional optical disk recording / reproducing apparatus. FIG. 7 is a timing chart for explaining the operation of FIG. 6; [Description of Signs] 1 PLL circuit 2 Demodulation circuit 3 Address detection circuit 4 Frequency switching control circuit 5 Read / write clock counter 6 Synthesizer 7 Window control circuit

Claims (1)

(57) [Claim 1] A recording area of a disk-shaped recording medium is divided into a plurality of zones, and a continuous read / write operation of an adjacent zone is performed using a different read / write clock for each zone. In an information recording / reproducing apparatus for writing, a switching means for switching the frequency of a read / write clock signal between a last sector of a zone and a first sector of the next zone, and detection for detecting a reference mark of the last sector Means, a clock counter for counting the number of read / write clocks, and a timing or period length for opening / closing a window for permitting reading of a signal of a preformat unit of a recording medium by a count output of the clock counter. A window control circuit that changes according to frequency switching of the write clock signal. The information recording and reproducing apparatus.