JP3361911B2 - VTR device and mute circuit used therefor - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a mute circuit and a VTR for eliminating the influence of noise mixed in a reproduction input circuit in a VTR (video tape recorder).

[0002]

2. Description of the Related Art Generally, in a VTR, a magnetic head is used for both recording and reproduction. Therefore, the reproduction input circuit is deactivated during recording, and the recording circuit is deactivated during reproduction. Then, particularly when recording, if the reproduction input circuit is not sufficiently muted, noise or the like is generated. The muting of the conventional reproduction input circuit is designed to drop the bias of the reproduction input amplifier (reproduction input amplifier).

On the other hand, a digital VT that has recently received attention
In R, each recording track is subdivided into a plurality of blocks, and a signalless portion exists between the blocks. Even with this format VTR, a normal V
As in the case of TR, it is usual to mute the reproduction input circuit during recording.

Further, in this digital VTR, there is a space between tracks, and the heads are switched during that period, so that noise periodically enters the reproduction input circuit even during reproduction. become. If this is left as it is, noise appears on the reproduction screen and noise is generated in the reproduced sound. Therefore, muting for removing head switching noise is performed during the reproducing operation.

A conventional example thereof is shown in FIGS. 6 and 7. In the conventional example of FIG. 6, in the reproduction input amplifier configured as a differential amplifier, the base is connected to the magnetic head and the emitter of the second transistor Q92 whose base is connected to the constant bias E ₁₀ is connected. Muting is performed by turning off the switches 102 and 103 connected in series to the constant current sources 100 and 101, respectively, which are turned off, thereby substantially deactivating the first and second transistors Q91 and Q92. To do. 10
4 is a DC power supply voltage line, and 105 is an output line.

On the other hand, in the conventional example of FIG. 7, in the reproduction input amplifier having the same structure as that of FIG. 6, a switch 110 is connected to the base of the first transistor Q91, and the input line 111 and the bias voltage E ₂₀ are selectively selected by this switch. You can choose to. Then, when the bias voltage E ₂₀ side is selected, mute is applied.

[0007]

However, each of these conventional examples has the following drawbacks. First, in the conventional example of FIG. 6, the potential of the output point K changes between the steady operation and the mute. That is, in the steady operation, the output point K is a potential determined by the voltage drop based on the current flowing through the resistor R10.
Become _CC . Therefore, the switching pulse is generated as noise when the steady operation is changed to the mute operation and when the mute operation is changed to the normal operation.

Further, in the conventional example of FIG. 7, the bias voltage E
_{If 10} and E ₂₀ are not the same, transistors Q91 and Q92
A difference occurs in the base potential of the DC output, and the DC output potential changes between the steady operation and the mute. In particular, since a semiconductor switch is used as the switch 110, an offset occurs due to the switch itself, and it is difficult to make the base potentials of the transistors Q91 and Q92 the same.

An object of the present invention is to provide a VTR mute circuit in which a difference in DC output voltage does not occur between normal reproduction and mute.

Another object of the present invention is to provide a VTR mute circuit and a VTR in which noise is not mixed into a reproduction input circuit during post-recording in a digital VTR.

[0011]

In order to achieve the above object, according to the present invention, in a mute circuit for muting a reproduction input circuit connected to a recording / reproducing magnetic head device in a VTR at the time of recording, The collector of the amplification transistor is connected to the DC power supply voltage line through a resistor, the emitter is connected to a constant current source, the reproduction signal is input to the base, and the output is taken out from the collector. Furthermore, the collector and the emitter are bypassed. The collector and emitter of the transistor are connected to each other, and the base bias of the bypass transistor is switched between during recording and during reproduction so that the bypass transistor is turned on and the amplification transistor is turned off during recording.

Further, according to the present invention, in the mute circuit for performing the reproduction mute in the no-signal period in the digital VTR in which the recording track is subdivided into a plurality of blocks and the no-signal period exists between the tracks,
The collector of the amplification transistor of the reproduction input circuit is connected to the DC power supply voltage line via a resistor, the emitter is connected to a constant current source, the reproduction signal is input to the base, and the output is taken out from the collector. By connecting the collector and the emitter of the bypass transistor to the emitter, and switching the base bias of the bypass transistor between the track period and the period between tracks during reproduction, the bypass transistor is switched in the period between the tracks. The transistor is turned on and the amplification transistor is turned off.

Further, according to the present invention, in a digital VTR of a format in which a recording track is subdivided into a plurality of blocks and there is a non-signal portion between the blocks, a direct current power source is provided to the collector of an amplification transistor of a reproduction input circuit through a resistor. The collector is connected to the voltage line and the emitter is connected to a constant current source, the reproduction signal is input to the base, and the output is extracted from the collector. Further, the collector and the emitter of the bypass transistor are connected to the collector and the emitter, respectively. A base bias is applied to the bypass transistor so that the bypass transistor is turned on and the amplifier is turned off during the period of the block for recording and the no-signal portion before and after the recording at the time of after-recording for reproducing and recording in the unit of block. Means are provided.

[0014]

According to the structure of claim 1, the current of the constant current source flows through the amplifying transistor to the resistor on the collector side during reproduction, and flows through the resistor through the bypass transistor during mute. Therefore, the current flowing through the resistor is the same during reproduction and mute, the DC voltage drop due to the resistance is the same, and the DC output potential does not fluctuate at all when changing from reproduction to mute and from mute state to reproduction.

According to the second aspect of the invention, in the digital VTR in which there is no signal period between tracks (channel switching period), the reproduction input circuit is muted during that period. Moreover, as in the case of claim 1, the fluctuation of the DC output potential does not occur.

According to the structure of claim 3, in a digital VTR of a format in which a recording track is subdivided into a plurality of blocks and there is a signalless portion between the blocks, when post-recording is performed in block units, reproduction input is performed during a recording period. The circuit is muted. In this case, the period for muting and releasing is shorter than that in the first aspect, but there is no fluctuation in the output potential as in the first aspect.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In FIG. 1, reference numeral 1a is a magnetic head for both recording and reproduction, and its output is given to the base of a transistor Q1 of a reproduction input amplifier. The output of the transistor Q1 is given to the emitter of the transistor Q2 connected as shown in the figure, is amplified, and then enters the mute circuit 2 from the collector of the transistor Q2.

The mute circuit 2 is a differential amplifier 5 comprising amplification transistors Q3 and Q4, a resistor R2, and constant current sources 3 and 4, and a bypass for connecting collectors and emitters to the collectors and emitters of the transistors Q3 and Q4, respectively. Applying a bias voltage E ₃ to the transistors Q5 and Q6 and these bypass transistors Q5 and Q6,
It has a switch 6 for shutting off.

The output of the mute circuit 2 is taken out from the collector connection point (a) of the transistors Q3 and Q5.
Reference numeral 7 is a feedback path including a buffer 8 and a resistor R5, which is a negative feedback type feedback path for applying a base bias of the transistor Q1. 9a is an amplifier.

Reference numeral 1b is a magnetic head having a different azimuth from the magnetic head 1a, and its output is guided to a changeover switch (channel changeover switch) 11 through a circuit 10 similar to the above-mentioned circuit and an amplifier 9b. The changeover switch 11 alternately switches the output of the amplifier 9a and the output of the amplifier 9b for each field and guides it to a subsequent circuit (not shown).

Now, at the time of recording, the mute circuit 2 operates to remove the noise flowing into the reproduction input circuit. The mute operation will be described. VTR by operating member 13
When the recording mode is set, the control unit 12 controls the switch 6
Turn on. Since the bias voltage E ₃ is set sufficiently higher than E ₁ and E ₂ , the transistors Q5 and Q6 are turned on, and the transistors Q3 and Q4 forming a differential pair with these transistors are turned off.

Therefore, the input signal applied from the magnetic head 1a to the base of the transistor Q3 through the transistors Q1 and Q2 is cut off because the transistor Q3 is OFF and is not output to the point (a). In addition, the constant current source 3,
The voltage of 4 does not flow to the resistors R3 and R4 through the transistors Q3 and Q4 during the reproducing operation. Instead, the currents of these constant current sources 3 and 4 are bypass transistors Q5 and Q5.
6 through resistors R3 and R4. Therefore, (a)
The DC voltage at the point is the same as when the transistors Q3 and Q4 are ON and the transistors Q5 and Q6 are OFF (in the reproduction mode), and is constant.

Next, when the operation member 13 is switched to the reproduction mode, the control unit 12 turns off the switch 6. Therefore, the bypass transistors Q5 and Q6 are turned off, and the transistors Q3 and Q4 are turned on.
In this case, the reproduction signal reproduced by the magnetic head 1a appears at point (a) from the transistors Q1 and Q2 through the transistor Q3, and the current of the constant current sources 3 and 4 appears at the resistors R3 and R4 through the transistors Q3 and Q4. .

According to the mute circuit of this embodiment, the DC potential at the output point (a) does not change at all during reproduction and during mute, and remains constant, so that mute is turned on and off. Switching noise does not occur. Further, since the base bias of the transistor Q1 given through the feedback path 7 does not change, there is no problem that the rise of the transistor Q1 is delayed when the mute is released and the reproducing operation is started.

In FIG. 1, reference numerals 13a and 13b denote recording circuits for supplying a recording current to the magnetic heads 1a and 1b. The recording circuits 13a and 13b are set to the operating state by the control unit 12 when the recording mode is selected by the operation unit 13, and are set to the inoperative state when the reproduction mode is selected.

Next, as shown in FIG. 2, each recording track 9
A format in which blocks A, B and C subdivided on 0 and 91 are provided with blank spaces (non-signal portions) G1 and G2 between them (the blank space is on the order of about 10 μsec or so. In a digital VTR according to (a), when recording is performed, reproduction and recording are performed in block units.

Therefore, for example, after reproducing the block A,
Recording is performed in block B, and then block C is reproduced. In such a case, in the reproduction input circuit, noise associated with recording will be reproduced during the block B period.

Therefore, in the second embodiment, as shown in FIG. 3, the mute circuit 2 having the same structure as the mute circuit 2 of FIG. 1 is provided in the second amplifier 22. Note that, unlike FIG. 1, the mute circuit 2 is not provided on the first amplifiers 21a and 21b side but is provided on the second amplifier 22 side. Therefore, the first amplifier 21
a, 21b, the third amplifier 23, and the AGC circuit 24 are in the operating state. By doing so, high speed reproduction can be supported.

If the first amplifiers 21a and 21b, the third amplifier 23, and the AGC circuit 24 are turned off at the time of recording, the rise of the entire reproduction input circuit will be delayed when the reproduction operation is started. Therefore, in the present embodiment, the second
Only amplifier 22 is substantially disabled. The first amplifiers 21a and 21b may be turned off during reproduction, but in that case as well, noise may fly from the magnetic heads 1a and 1b to the second and subsequent amplifiers 22, so Is provided with a mute circuit 2. As described with reference to FIG. 1, since the bias of the mute circuit 2 does not change between the mute state and the mute release state, the rise of the second amplifier itself is not delayed.

In FIG. 3, the control signal from the control unit 12 (FIG. 1) to turn ON / OFF the switch 6 (FIG. 1) covers at least the recording period (block B) as shown in FIG. 4B. A pulse with a width of Then, mute is applied during this pulse period. The pulse in FIG. 4B covers the block B and the blank spaces G1 and G2. Thus, in the embodiment of FIG. 3, the digital V
In the TR, when post-recording is performed on a block-by-block basis, the reproduction input circuit is muted for at least the recording period, so that noise is not output from the reproduction input circuit.

Incidentally, in the digital VTR, it may be desirable to mute the reproduction input circuit not only during dubbing and recording but also in the normal reproduction mode. That is, in a general VTR, a signal also exists between tracks on which head switching (channel switching) is performed, so even if there is channel switching noise during that time, it is not so noticeable, but in a digital VTR, tracks and tracks are not noticeable. Since there is no signal between them, if head switching noise occurs during that time, the noise will be noticeable.

Moreover, the noise N generated when the channel is switched is generated in the AGC circuit 24 (see FIG. 3) as shown in FIG. 5A.
Is input, the detection circuit 25 of the AGC circuit 24 detects the noise and lowers the gain of the variable amplifier 26. As a result, the output has a shape as shown in FIG.

However, in this embodiment, the switch 6 (FIG. 1) of the mute circuit 2 of the second amplifier 22 shown in FIG.
2 (FIG. 1) to FIG. 5 (c), noise N is eliminated by applying a pulse that covers the channel switching period during reproduction. Therefore, since the AGC circuit 24 does not receive a malfunction due to the noise N and operates normally, the output of the reproduction input circuit becomes a normal form as shown in FIG. 5D.

[0034]

According to the first aspect of the present invention, the DC output potential of the reproduction input circuit does not fluctuate at the time of changing from the reproduction state to the mute state or from the mute state to the reproduction state, so that noise is newly added to the reproduction input circuit. It is possible to avoid problems that occur.

According to the second aspect of the invention, in the digital VTR in which there is no signal period between tracks (channel switching period), the reproduction input circuit is muted during that period, so that channel switching noise is eliminated. To be done. Moreover, since the DC output potential does not fluctuate as in the case of claim 1, noise is not generated.
Therefore, when the AGC circuit is provided in the subsequent stage of the reproduction input circuit, the AGC circuit does not malfunction due to the noise.

According to the third aspect of the invention, in the digital VTR of the format in which the recording track is subdivided into a plurality of blocks and the non-signal portion exists between the blocks, when the post-recording is performed in the unit of the block, the reproduction input is performed during the recording period. Although the circuit is muted, the output potential of the reproduction input circuit does not fluctuate as in the case of the first aspect. Therefore, when the AGC circuit is provided in the subsequent stage of the reproduction input circuit, the AGC circuit does not malfunction.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a part of a reproduction input circuit of a VTR using a mute circuit of the present invention.

FIG. 2 is a diagram showing recording tracks for explaining the format of a digital VTR.

FIG. 3 is a digital VT using the mute circuit of the present invention.
The block circuit diagram which shows the reproduction | regeneration input circuit of R.

FIG. 4 is a diagram showing a mute period when performing post-recording with the circuit of FIG.

FIG. 5 is a diagram for explaining an effect when muting is performed at the time of channel switching in the circuit of FIG.

FIG. 6 is a circuit diagram showing a conventional mute circuit.

FIG. 7 is a circuit diagram showing another conventional mute circuit.

[Explanation of symbols]

1a, 1b magnetic head 2 muting circuit Q3 amplifying transistor Q5 bypass transistor E ₃ bias voltage 6 switch 12 control unit 90 and 91 track A, B, C block G1, G2 blank (no signal) space

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Claims (4)

(57) [Claims] 1. A mute circuit for muting a reproduction input circuit connected to a recording / reproducing magnetic head device in a VTR at the time of recording, wherein a collector of an amplification transistor of the reproduction input circuit is connected through a resistor to a DC power supply voltage line. And the emitter is connected to a constant current source, the reproduction signal is input to the base, and the output is taken out from the collector. Furthermore, the collector and the emitter of the bypass transistor are connected to the collector and the emitter, respectively. A mute circuit in a VTR, wherein the base bias of the bypass transistor is switched during reproduction so that the bypass transistor is turned on and the amplification transistor is turned off during recording. 2. A mute circuit for performing reproduction mute in a non-signal portion of a digital VTR having a format in which a recording track is subdivided into a plurality of blocks and a non-signal portion exists between the blocks. The collector of the amplification transistor is connected to the DC power supply voltage line through a resistor, the emitter is connected to a constant current source, the reproduction signal is input to the base, and the output is taken out from the collector. Furthermore, the collector and the emitter are bypassed. The collector and emitter of the transistor are connected to each other, and during reproduction, the base bias of the bypass transistor is switched between the track period and the period between tracks to turn on the bypass transistor during the period between tracks. And the amplification transistor A mute circuit in a VTR characterized by being turned off. 3. In a digital VTR having a format in which a recording track is subdivided into a plurality of blocks and a non-signal portion exists between the blocks, the collector of an amplification transistor of a reproduction input circuit is connected to a DC power supply voltage line via a resistor. In addition, the emitter is connected to a constant current source, the reproduction signal is input to the base, the output is taken out from the collector, and the collector and the emitter of the bypass transistor are connected to the collector and the emitter, respectively. Mute having means for applying a base bias to the bypass transistor so that the bypass transistor is turned on and the amplifier is turned off during the period of the recording block and the no-signal portion before and after the post-recording block. Characterized by using a circuit VTR device. 4. The VTR device according to claim 3, wherein the non-signal portion corresponds to a time of the order of 10 μsec.