JP3363109B2 - How to create a mask pattern - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a mask pattern forming method.

[0002]

2. Description of the Related Art With the recent trend toward higher density and finer semiconductor devices, in order to separate a plurality of elements provided on a semiconductor substrate, a groove (trench groove) is provided between the elements to electrically connect the elements. A trench isolation technique for isolation has been introduced.

Generally, an insulating film is deposited along the surface of a substrate on which irregularities are formed by separating elements by trench grooves, and then the surface is flattened. One of the surface flattening treatments is a chemical polishing agent. And a polishing pad are used to chemically and mechanically polish the substrate surface.
MP method).

The CMP method is a method for polishing the surface of a substrate with a polishing pad while adding a chemical polishing agent to chemically and mechanically polish the surface of the substrate for planarization. This method has the characteristics that a high degree of mirror surface can be obtained because the processing unit is small, the specularity is high because a viscoelastic polisher is not used, and the deterioration of processing is extremely small because a chemical reaction is used. There is.

However, in the CMP method, the polishing pad polishes along the surface of the insulating film formed on the surface of the substrate, so that, for example, the insulating film portion formed so as to fill the stepped portion such as a large trench groove. When polishing a region where the surface is slightly concave, the surface is polished along the concave of the insulating film surface.

Therefore, the surface of the finally obtained substrate is partially concave, the corners forming the step of the pattern are shaved, and the fine pattern surrounded by the large trench groove is polished. In some cases, the insulating film in the central portion of the trench groove is partially polished to be dug down.

In order to prevent the disappearance of the fine pattern and the partial digging of the insulating film due to such polishing, Japanese Unexamined Patent Publication No. 9-181159 discloses regular dummy protrusions in the trench groove. It has been proposed that a plurality of grooves be provided to substantially reduce the size of the groove and make the surface of the upper insulating film structurally uniform.

In Japanese Unexamined Patent Publication No. 9-181159, first, a dummy pattern non-forming region on a substrate is formed by ORing regions including an active region, a gate electrode region, a wiring region and the vicinity of each region. Form a pattern to represent. Next, the tenth intermediate mask region is formed by taking the logical sum of the formed pattern and the lattice-shaped dummy pattern that represents the non-formed region of the dummy pattern when a plurality of dummies are arranged regularly. An eleventh intermediate mask region representing the dummy pattern non-forming region on the substrate is formed by taking the logical product of the ten intermediate mask regions and the formation pattern of the inactive region obtained by inverting the pattern representing the active region forming the semiconductor. Then, the pattern obtained by reversing the dummy pattern formation region and the dummy pattern non-formation region in the eleventh intermediate mask region becomes a trench pattern, and a mask is formed based on the obtained trench pattern to pattern the semiconductor device. I do.

[0009]

[Problems to be Solved by the Invention]
If the size is not more than (for example, vertical × horizontal is about 0.5 μm × 0.5 μm), the resist pattern formed on the substrate surface during dummy formation may collapse, the resist pattern may peel off, or the resist pattern peeled off. Is likely to fly over other patterns and adhere to other patterns such as patterns that represent active areas or patterns that represent dummy patterns.If the resist pattern falls or peels off, the pattern after etching may The shape will be different from the desired pattern.

Further, if the size of the dummy pattern is too small, the light-shielding area to be left as a dummy pattern formed on the exposure mask also becomes small, and the desired pattern cannot be patterned due to the wraparound of light during exposure. .

In the method of forming a mask disclosed in Japanese Patent Laid-Open No. 9-181159 described above, a plurality of patterns are simply overlapped to determine a final pattern, and therefore the mask is closest to the active region, the gate electrode and the wiring. It is inevitable that the dummy pattern provided as a part of the dummy pattern is partially cut.

Therefore, a minute dummy pattern that cannot be exposed is actually formed on the mask due to light wraparound, or the resist formed on the substrate is collapsed even if it is exposed, or it is formed on the substrate. The resist formed may peel off and adhere to other resists. By etching while the resist is tilted or attached to another resist, for example, the active region formed by etching is deformed, or the active region patterns are connected to each other and short-circuited, so that a desired pattern is formed. Causes a problem that patterns of different shapes are formed.

In view of the above, the present invention has an object to provide a method of forming a mask pattern in which the resist does not fall or peel off.

[0014]

In order to achieve the above object, a mask pattern forming method according to a first aspect of the present invention is a first pattern in which a dummy pattern forming region in a patterning region is represented by a first logical variable. And a second pattern in which a predetermined number of dummy patterns represented by the first logical variable are arranged over the entire patterning region to obtain an intermediate pattern representing the dummy pattern formed in the patterning region. A process of forming a dummy pattern having a predetermined threshold size or less from the intermediate pattern is performed.

That is, according to the first aspect of the invention, first, an intermediate pattern representing a dummy pattern formed in the patterning region is formed. That is, the first pattern, which is the pattern of the dummy pattern formation region represented by the first logical variable, and the second pattern, in which the predetermined number of dummy patterns represented by the first logical variable are arranged on the entire patterning region, By taking the logical product, an intermediate pattern representing the dummy pattern formed in the dummy pattern formation region is obtained.

Since this intermediate pattern is a pattern obtained by simply superposing the patterns on each other, a dummy pattern having a size smaller than a predetermined threshold size is also included. Therefore, in claim 1, next, the intermediate pattern is
Each dummy pattern of the pattern is reduced and each remaining dummy pattern is reduced.
Turn in a predetermined width in the opposite direction to the contracted direction
By performing the enlarging process, a process of erasing the dummy pattern having a predetermined threshold size or less from the intermediate pattern is performed. In this way, remove the dummy pattern of a certain size that the resist may fall over or peel off,
Obtain a mask pattern that prevents the resist from falling or peeling.

The process of erasing a dummy pattern having a size equal to or smaller than a predetermined threshold size from the intermediate pattern is performed by, for example, setting the threshold size of the dummy pattern toward the center from the outer edge of each dummy pattern of the intermediate pattern. 1/2
It is preferable to perform a process of reducing the width of the dummy pattern and expanding the remaining dummy pattern in a direction opposite to the reduction direction by a predetermined width.

That is, by processing so as to reduce the area having a width of 1/2 of the threshold size from the outer edge of each dummy pattern toward the center, each dummy pattern is changed without changing the center position. The pattern can be reduced.

At this time, the dummy pattern having a size larger than the predetermined threshold size is a pattern reduced to the size of the width of the difference from the predetermined threshold size, and has a size smaller than the predetermined threshold size. Since the dummy pattern cannot be reduced, it will be erased at that point.

Since there is no data representing the pattern at the position where the dummy pattern is erased, thereafter, each of the obtained reduced patterns is expanded by a predetermined width in the direction opposite to the contracted direction, so that it is predetermined. A pattern in which only dummy patterns having a size larger than the threshold size remain is obtained.

By setting the expansion width at this time to a width of 1/2 of the threshold size as described in claim 3, only the dummy pattern having a size larger than the predetermined threshold size is the original. The pattern returned to size is obtained.

The predetermined threshold size is determined by various factors such as the type of resist and the size of the pattern, but at least when the resist is formed, the resist does not fall or peel off. For example,
It is preferable that the dimension is 0.5 μm or more and the flatness due to CMP polishing is not impaired, for example, 10 μm or less.

Further, the method of reducing and enlarging each dummy pattern in the intermediate pattern is not limited to the method described in claim 2, and, for example, a threshold value is set from the end of two sides forming one corner of each dummy pattern. After the process of reducing the size width is performed, the process of enlarging only the remaining pattern in the opposite direction to the reduction may be performed.

The invention described in claim 4 is the same as claim 1
4. The method for producing a mask pattern according to claim 3, wherein a pattern of a sum of the intermediate pattern and a pattern representing an active region forming a semiconductor element is formed to form an active region forming a semiconductor element. This is a method of creating a dummy pattern including a pattern.

That is, according to the invention of claim 4, the mask pattern to be formed includes the mask pattern of the active region constituting the semiconductor element, and the mask and the semiconductor device formed based on the obtained mask pattern. The patterning of the active region can be performed simultaneously with the patterning of the dummy pattern to improve the patterning work efficiency.

[0026]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, an example of an embodiment of the present invention will be described in detail with reference to the drawings. In this embodiment,
This is an example of a case where an exposure mask is created by using the mask pattern creation method of the present invention and a semiconductor device is manufactured using the obtained exposure mask.

First, as shown in FIG. 1 (A), the pattern of the pattern 20 representing the active region indicated by the broken line is enlarged from each outer edge in the direction away from the center of the pattern 20 by a region having a width of 5 μm, for example. The area including the active area and its surroundings is represented by a logical variable “1”, the other areas are represented by a logical variable “0”, and the first pattern 30 (diagonal line) composed of the area represented as “1” is shown. Part) is formed.

Here, the pattern 20 representing the active region is enlarged by a region having a width of 5 μm, but the range of the pattern enlargement is preferably 0.5 μm or more and 10 μm or less, although it varies depending on the type of resist. .

If it is smaller than 0.5 μm, the dummy is more likely to be formed in a position closer to the active region than 0.5 μm, and if the dummy is formed in a position closer than 0.5 μm to the active region. It is not preferable because the dummy and the active region are electrically connected to each other due to defective patterning or dust, which may cause a short circuit.

On the other hand, if it is larger than 10 μm, the dummy and the active region are too far apart from each other, so that the function as the dummy cannot be achieved and the insulating film formed in the upper layer may sag, which is not preferable. . The width of the enlarging process below is 0.5 μm or more for the same reason.
μm or less.

Further, as shown in FIG. 1B, the center of the pattern 20 is a region having a width of 5 μm from the outer edge of each pattern 20 of the pattern 22 representing the gate electrode and the pattern 24 representing the wiring, which are indicated by broken lines. The region including the gate electrode and its surroundings is expanded by a logical variable "1", and the other regions are expanded by a logical variable "0",
The second pattern 32 (hatched portion) that is formed by the area
, The area including the wiring and its surroundings is represented by the logical variable “1”, and the other area is represented by the logical variable “0”,
And a third pattern 34 (hatched portion) formed of the area shown as.

Further, as shown in FIG. 1C, a rectangle 26a enlarged by a region having a width of 0.25 μm or more and 5 μm or less from the well boundary 26 shown by a broken line and the well boundary 26 of 0.25 μm or more and 5 μm or less. The area sandwiched between the rectangle 26b reduced by the area having the width of 1 is represented by the logical variable "1", and the other area is represented by the logical variable "0". 4 patterns 36 (hatched portions) are formed. The range of expansion and contraction of the well boundary 26 is set so that the dummy pattern formed in the vicinity of the well boundary 26 does not come too close to the well boundary 26 and is not too far away.

1st to 4th patterns 3 consisting of areas represented as "1" of the logical variables in FIGS. 1A to 1C.
Reference numerals 0, 32, 34, and 36 are areas in which the dummy patterns are not formed in the area 10 corresponding to the substrate, respectively, and are shown as the shaded area in FIG. 2 by taking the logical sum of the patterns represented by "1". The area where the dummy pattern is not formed on the substrate, such as
The fifth pattern 12 expressed as is obtained.

After that, the fifth pattern 12, which is shown as "1" in FIG. 2 and representing the region on the substrate where the dummy pattern is not formed, is inverted to form the dummy pattern on the substrate as shown by the hatched portion in FIG. The sixth pattern 13 composed of the regions represented by "1" is obtained by defining the region to be formed as "1" and the region in which the dummy pattern is not formed as "0".

Thereafter, as shown in FIG. 4, a pattern area 14 in which rectangular dummy patterns are represented as logical variables "1" is regularly arranged on the entire surface of the area 10 corresponding to the substrate, and areas other than the dummy pattern are arranged. 5 is obtained by taking a logical product of the seventh pattern 15 in which is expressed as a logical variable “0” and the sixth pattern 13 in which the obtained area on the substrate forming the dummy is expressed as a logical variable “1”. An eighth pattern 16 is obtained in which the dummy pattern formed on the substrate as shown in (1) is represented as a logical variable "1".

Next, the obtained eighth pattern 16 includes dummy patterns 14a, 14b and 14c which are reduced in size by cutting a part of the rectangular dummy pattern 14, and such dummy pattern 14 is formed. 14a, 14b, 14c
The following processing is performed to erase the.

First, the minimum size (that is, the threshold size) of the dummy pattern formed on the substrate is determined. The dimension that can be formed as the dummy pattern is at least that the resist does not collapse and the rectangular pattern formed on the mask can be used as the mask. In the present embodiment, the dimension of the dummy pattern 14 is defined as vertical × The width is 7 μm × 7 μm, and the pattern size representing the threshold is 6 μm × 6 μm in the length × width.

Next, with respect to the individual dummy patterns 14 in the eighth pattern 16 representing the dummy pattern formed on the substrate as shown in FIG. 5, 1 / th of the threshold size is applied in the direction from each side toward the center of the dummy pattern. The pattern is reduced by performing a process of subtracting a region having a width of 3 μm, which is 2.
Dummy pattern 14 that has not been cut during pattern formation
As shown in FIG. 6A, since all four sides are 7 μm, when the pattern is reduced by performing a process of subtracting a region having a width of 3 μm from each side toward the center of the pattern,
It remains as a rectangle with one side of 1 μm. Similarly, as shown in FIG. 6B, the dummy pattern 1 in which the lengths of all four sides are equal to or larger than the threshold size even if they are partially cut during pattern formation
Even if the pattern 4b is reduced by performing a process of subtracting a region having a width of 3 μm in the direction from each side toward the center of the dummy pattern, it remains as a rectangle having one side of 1 μm.

Further, as shown in FIGS. 6C and 6D, among the patterns to be reduced, the dummy patterns 14c and 14d having a size smaller than the threshold size are located at the center of the dummy pattern from each side. When the area having a width of 3 μm is subtracted in the direction toward, it becomes negative and cannot be represented as a figure. Therefore, at that time, a process of erasing the data representing the dummy pattern is performed. As a result, the threshold size of vertical ×
All dummy patterns having a size smaller than 6 μm × 6 μm in width will be erased.

That is, in the case of FIG. 6, the dummy patterns left by the reduction processing are dummy patterns 14 and 14 having a size equal to or larger than the threshold size as shown in FIGS. 6 (A) and 6 (B).
Only a pattern in which a is reduced, and a pattern in which only the dummy pattern 14 having a size equal to or larger than the threshold size is selectively reduced can be obtained.

After that, the obtained pattern is subjected to 3
By performing a process of enlarging by adding an area having a width of μm, a ninth pattern 18 including only dummy patterns having a size equal to or larger than a threshold size is obtained, as shown in FIG.

Thereafter, the obtained ninth pattern 18 and the pattern representing the active region pattern 20 of FIG. 1A are enlarged from each side by a width of 0.5 μm or more and 10 μm or less, and the active region and its periphery are enlarged. An exposure mask is created based on the pattern obtained by taking the logical sum of the included region and the first pattern 30 in which the logical variable is represented by "1".

This exposure mask is 7 .mu.m.times.7 .mu.m in the present embodiment considering that it is reduced by projection exposure.
28 μm × 28 μm for the rectangular light-shielding part corresponding to the dummy
Or a Cr film having a size of about 35 μm × 35 μm. By setting the size of the rectangular light-shielding portion to be 2 μm or more, patterning cannot be prevented due to light sneak and 0.5 μm on the substrate.
This is preferable because a dummy pattern having the above dimensions can be formed. Also, by setting the thickness to 50 μm or less, 1
This is preferable because a dummy of 0 μm or less can be formed.

The dummy pattern obtained by performing exposure based on the mask thus formed is formed by exposing a resist smaller than a predetermined threshold size dimension as shown in FIG. Therefore, it is possible to prevent various problems from occurring due to a small resist falling down, flying from the substrate surface and adhering to another resist.

Therefore, in the obtained semiconductor device, the surface is partially concave, the corners forming the step of the pattern are shaved, and, for example, the fine pattern surrounded by the large trench groove is polished and disappears. In addition, the insulating film in the central portion of the trench groove is not polished and is not dug down.

[0046]

As described above, according to the first aspect of the present invention, since the dummy pattern having a size smaller than the predetermined threshold size is erased, the dummy pattern which does not fall or peel off the resist is formed. It has the effect that it can be created.

According to the second and third aspects of the present invention, the position of the dummy pattern does not deviate from the initial position by the process of erasing the dummy pattern having a size smaller than the predetermined threshold size, and it is simple. Further, there is an effect that a pattern having a size smaller than a predetermined threshold size can be selectively erased.

Further, in the invention of claim 4, since the convex dummy pattern and the active region can be formed at the same time, there is an effect that it is not necessary to newly provide an exposure step for forming the dummy pattern.

[Brief description of drawings]

1A is a diagram showing a first pattern showing a region including an active region and its periphery in a region corresponding to a substrate in a region corresponding to a substrate; FIG. 1B is a gate; FIG. 1C is a diagram showing a second pattern representing a region including an electrode and its periphery, and FIG. 1C is a diagram showing a pattern representing a region including the periphery of a well boundary.

FIG. 2 is a diagram showing a pattern representing a region in a patterning region where a dummy pattern is not formed.

FIG. 3 is a diagram showing a pattern representing a region for forming a dummy pattern in a patterning region.

FIG. 4 is a diagram showing a pattern in which rectangular dummy patterns are regularly arranged on the entire patterning region.

FIG. 5 is a diagram showing a dummy pattern in a dummy pattern formation region.

FIG. 6 is an explanatory diagram showing an example of reduction processing according to the present embodiment.

FIG. 7 is a diagram showing a dummy pattern in a dummy pattern formation region after reduction processing and enlargement processing.

FIG. 8 is a diagram showing a dummy pattern and an active region pattern in the present embodiment.

[Explanation of symbols]

10 Area corresponding to the substrate (patterning area) 12 Fifth pattern 13 6th pattern (1st pattern) 14, 14a to 14c Dummy pattern 15 7th pattern (2nd pattern) 16 8th pattern (intermediate pattern) 18th pattern 20 Patterns that represent active areas 22 Patterns representing gate electrodes 24 wiring patterns 26 well boundary 26a Rectangular shape with enlarged well boundary 26b Rectangle with reduced well boundary 30 First pattern 32 Second pattern 34 Third pattern 36 4th pattern

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Claims (4)

(57) [Claims] 1. A first pattern in which a dummy pattern formation region in a patterning region is represented by a first logic variable, and a predetermined number of dummy patterns represented by a first logic variable is arranged over the entire patterning region. The intermediate pattern representing the dummy pattern formed in the patterning region is formed by taking the logical product of the two patterns, and each dummy pattern of the intermediate pattern is reduced and left.
The direction in which each dummy pattern is reduced by a predetermined width
A mask pattern creating method for performing a process of erasing a dummy pattern having a predetermined threshold size or less from the intermediate pattern by performing a process of enlarging in the opposite direction . 2. The dummy pattern of the intermediate pattern is reduced from the outer edge of the dummy pattern toward the center by a width of ½ of the threshold size, and the remaining dummy patterns are reversed by a predetermined width in the opposite direction. The method for creating a mask pattern according to claim 1, wherein the dummy pattern having a size equal to or smaller than the predetermined threshold size is erased by performing a process of enlarging in the direction of. 3. The method of creating a mask pattern according to claim 2, wherein the predetermined width is a half of the threshold size. 4. The method for producing a mask pattern according to claim 1, wherein a pattern of a sum of the intermediate pattern and a pattern representing an active region forming a semiconductor element is formed. A method of forming a mask pattern for forming a dummy pattern including a pattern of an active region constituting a semiconductor element.