JP3364573B2 - Electronic tone generator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [0001] BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic musical instrument,
Device and desktop music (DTM: De
CMOS (Complementary Metal Ox) such as sk Top Music
ide Semiconductor) sound source LSI (Large
Scale Integrated Circuit) electronically generates musical sounds
Related to electronic musical sound generators applied to
is there. [0002] 2. Description of the Related Art Conventionally, a plurality of sounds are generated simultaneously by time division.
Possible electronic musical instruments are known. Such an electronic musical instrument
Is to store the waveform data of the musical tone corresponding to the keyboard operation
(Read Only Memory) in time division
Allocating sound to channels (musical sound generation channels)
The number of channels prepared for generating musical tones
It is made to be able to pronounce sometimes. [0003] By the way, as described above,
Power consumption is the largest among conventional electronic musical instruments
Is a speaker drive circuit, which is used to obtain a general volume.
The driver circuit of the loudspeaker has a tone generator circuit (tone generator).
Nere) requires about one order of magnitude more power. Therefore, by eliminating the speaker, the mainstream
From 5V power supply to 3V power supply
Digital electronic musical instruments. However, this
Electronic musical instruments save more power than the power required for speakers
It is not intended. That is, a conventional electronic musical instrument is
Power saving is being promoted, but with the tone generator circuit itself
Because there was no one aiming at power saving, total
Power saving could not be achieved. In particular, in the sound source circuit of a conventional electronic musical instrument,
Prepared for both sounding and non-sounding channels
For all channels that have been
The power required to calculate the channels that do not sound
It was always useless. For this reason, battery-powered electronic musical instruments
Are products that can only be used for a few days due to battery life.
there were. Accordingly, the present invention eliminates the above disadvantages.
For electronically generating musical tones.
Power saving of sound source LSI and its peripheral logic (waveform ROM, etc.)
Power savings to achieve total power savings
To provide an electronic musical sound generator capable of
I do. [0008] SUMMARY OF THE INVENTION An electronic musical tone generator according to the present invention.
Generates multiple tone data in a time-division
Electronic tone generator that outputs tone data for sound channels
A plurality of pieces of music data for generating the plurality of pieces of tone data.
Control data and a sound channel
Memory device in which channel information is stored externally for each sound channel
Above and synchronized with the time slot of each sounding channel
From the storage means, a plurality of control data and
Reading the storage means so that the channel information is read out.
Control means for controlling the operation, and
Latches multiple control data for each sound channel.
Switch means and the latch means for each sound channel.
Latch signal supply means for selectively supplying a latch signal.
The latch signal supply means reads from the storage means.
Based on the output channel information, unused pronunciation channels
In the time slot ofFor the above latch means
Not to supply the latch signal
The latch means includes a plurality of control data for unused sound channels.
Data is not latchedIt is characterized by doing
You. [0009] BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described.
This will be described with reference to the drawings. [0010] An electronic musical tone generator according to the present invention, for example,
It is applied to an electronic musical instrument 1 as shown in FIG. The electronic musical instrument 1 has a structure as shown in FIG.
The keyboard 10, the operation panel 20, and the sequencer
Below, it is referred to as SEQ) 40 and a tone generator (hereinafter, referred to as SEQ).
Below, also called a wave generator) 50, operation panel
20 and SEQ40 and wave generator 50
Connected to the host CPU (Cent
ralProcessing Unit) 30 and wave generator 5
0 and a wave table 60 connected to the
Digital / analog to which the output of the neerator 50 is supplied
A converter (hereinafter, referred to as DAC) 70 and a DAC 70
And a speaker 80 to which the output is supplied. Ma
The host CPU 30 includes other electronic musical instruments and the like.
No external sound source device can be connected and this external sound source
MIDI (Musical Instrument Digital Int)
erface) signal to provide external control information
It has been done. The wave generator 50 is connected to the host CP
The output of U30 is supplied via input terminal I51.
Output of the assignment memory 100 and the assignment memory 100
Wavetable address generator to which each power is supplied
Data 200 and the envelope generator 300,
Envelope connected to envelope generator 300
Memory 400 and the output of assignment memory 100
Each provided accumulator 500 and system clock generator
Of the generator 600 and the envelope generator 300
Output and output of wavetable 60 from input terminal I54
And a multiplier 700 to which a force is supplied. Also,
The addressing circuit 10
1 is also supplied and the wavetable address generator
The output of the oscillator 200 is output via the output terminal I53.
The table 60 is supplied. Further
In addition, the envelope memory 400 stores the addressing times.
The output of the path 401 is supplied and the envelope memory 400
Is supplied to the host CPU 30 via the output terminal I52.
It is made to be paid. Furthermore, the accumulator 50
0 is supplied with the output of multiplier 700 and accumulator 500
Is supplied to the DAC 70 via the output terminal I55.
It has been made. The electronic musical instrument 1 as described above has a sounding channel
For example, 16 channels are used as (music generation channels)
It is easy to use 16 channels (16 sounds)
It is designed to be able to generate sounds and generate simultaneous sounds. Therefore, first, a series of operations of the electronic musical instrument 1 will be described.
explain about. The host CPU 30 is, for example, a microcomputer.
Key operation information of the keyboard 10
Operation information of the channel 20, output information of the SEQ 40, and the above
MIDI information of the external sound source device
A sounding instruction or a mute instruction based on each information is input to the input terminal I.
The signal is supplied to the wave generator 50 via 51. In the wave generator 50, the input
The command from the host CPU 30 supplied via the terminal I51
The command information is stored in the assignment memory 100. So
Then, the information stored in the assignment memory 100 is
The information is read out in a time-sharing manner, and
Wave for generating read address of wave table 60
Table address generator 200 and envelope
The envelope generator 300 that generates the
Work. Wave table address generator 2
The read address generated at 00 is output via the output terminal I53.
And supplied to the wavetable 60. Wave tape
The module 60 is composed of a ROM, and is configured to read data from the output terminal I53.
Outputs waveform data to input terminal I54 according to address
I do. Therefore, from the input terminal I54 to the multiplier 700
Is supplied with the waveform data output from the wavetable 60.
Be paid. Incidentally, the wave table 60 may be a RAM or
Wave generator 50 composed of flash RAM
Is not operating, the host CPU 30
(R / W). Also, the envelope generator 300
The envelope value obtained by the calculation is also supplied to the multiplier 700.
Be paid. Therefore, the multiplier 700
Read address of the table address generator 200
Waveform data read from the wavetable 60 in accordance with
Data obtained by the envelope generator 300.
It is multiplied by the envelope value. The accumulator 500 calculates the multiplication result of the multiplier 700
Is accumulated, and accumulated for 16 channels in one sample period.
Outputs the calculation result. The accumulation result of this accumulator 500 is
It becomes the output of the generator 50, and D is output through the output terminal I55.
Supplied to AC70 and converted to analog by DAC70
Thereafter, sound is emitted from the speaker 80. Next, inside the wave generator 50,
This will be specifically described. Here, FIG.
Timing chart showing timing clock at 0
USE signal and timing signals t0 to t in the figure.
7, ts0 to ts15 are system clock generators.
Data 600. First, the USE signal is a time-division signal.
Here, ch. 0 to ch. Time for 15 16 channels
Percent), the channel of the provided time slot is used
"1" when it is used, when it is not used
It becomes "0". Therefore, in this figure, the used channel
Is ch. 0 and ch. 2 channels. The timing signal t0 is a USE signal.
Is always output, regardless of the value of
The USE signal of each time division channel is generated by the
It is made to be latched. On the other hand, the other timing signals t1 to t7 are
If the USE signal is "0", it will not be output.
Has been made. That is, the wave generator 50
Then, when the USE signal is “1”,
Therefore, a pipe described later with the timing signals t1 to t7 is used.
Line latch clock is generated and USE signal is "0"
In the case of, because it is an unused channel, the point in FIG.
As shown by the line, make sure that the latch clock does not occur.
Has been made. Therefore, the unused channel
Channel ch. 1 and ch. 3 to ch. 15 timeslots
In the reset, the latch signals of the timing signals t1 to t7 are
The lock is omitted. The timing signals ts0 to ts15 are
Nell ch. 0 to ch. 15 respectively.
This signal is “1” at the time of the corresponding channel. here
Is the timing signal ts1 in the accumulator 500 described later.
Only use. The USE signal and the timing described above
System for generating signals t0 to t7 and ts0 to ts15
The details of the clock generator 600 will be described later.
You. Therefore, first, the assignment memory 100
Will be specifically described. The assignment memory 100 is, for example,
As shown in FIG. 0 to ch. Every 15
8A corresponding to the timing signals t0 to t7 described above.
A dress is provided for each. At the address corresponding to the timing signal t0,
Indicates whether the channel is used or unused.
USE information is stored and corresponds to the timing signal t1.
Address is used to store enable information.
It has been done. An address corresponding to the timing signal t2
The loop top information is stored in the
The address corresponding to the signal t3 contains the loop end information.
At the address corresponding to the timing signal t4,
Frequency number (hereinafter referred to as F number) information is stored
The address corresponding to the timing signal t5 is
As address information is stored, and the
The corresponding address has an envelope target value (hereinafter referred to as E
Envelope speed (hereinafter referred to as E speed)
Information is stored and corresponds to the timing signal t7.
The loudness information is stored at the address
It has been done. The various information for each channel as described above is
Various information stored and stored by the host CPU 30
Information is read out by the addressing circuit 101.
Has been made. In particular, an address corresponding to the timing signal t0
The USE information stored in the address
This is information to be generated, and is generated by the host CPU 30.
USE information of the channel assigned when the key is pressed
Set to “1” and envelope release ends after key release
The completed channel is confirmed in the envelope memory 400.
When reset, it is reset to "0". The data stored in the assignment memory 100 is
Details of various types of information will be described later. Also here
Are assigned to addresses corresponding to the timing signals t0 to t7, respectively.
Species information is arranged, but it is limited to this arrangement.
Not something. Next, the assignment memo described above is used.
Read and operate various information stored in the memory 100
About Wavetable Address Generator 200
This will be specifically described. Wave table address generator 2
00 is, for example, as shown in FIG.
Latches to which the information read from the memory 100 is respectively supplied.
Paths 201 to 206 and each of latch circuits 203 and 206
An adder 210 to which an output is supplied, a latch circuit 202 and
And a comparator 211 to which each output of the adder 210 is supplied;
Each of the latch circuit 204, the adder 210, and the comparator 211
A selector 212 to which an output is supplied, a latch circuit 201 and
An adder 213 to which each output of the selector 212 is supplied;
A latch circuit 207 to which the output of the adder 213 is supplied;
FACC memory 214 to which the output of selector 212 is supplied
And the gate 2 to which the output of the FACC memory 214 is supplied
16 and the output of the latch circuit 207 is
Output of the bootable address generator 200
Supplied to the wavetable 60.
You. The gate 216 is connected to the output of the latch circuit 205.
The output of the gate 216 is
6 is provided. In addition, FACC
The memory 214 stores the output of the addressing circuit 215
Is read out. The latch circuits 201 to 207 have:
Timing signals t1 to t7 as shown in FIG.
These latch circuits 201 to 207
Constitutes a pipeline. Therefore, for example, the wavetable address
Ch. To 0
When an operation is performed on the latch, the latch circuit 201
At the timing of the falling edge of the
Bias address information read from the
The information is obtained and supplied to the adder 213. This bias add
Address information indicates that the waveform being calculated is
The value indicating whether the address is written from the address,
This is information indicating a start address. The latch circuit 203 is provided with a timing signal.
Read from the assignment memory 100 by the number t4
The obtained F number information is obtained and supplied to the adder 210. This
Is the value for generating the frequency,
It is accumulated by the adder 210. Further, the latch circuit 202 outputs a timing signal.
Read from the assignment memory 100 by the number t3
The loop end information is obtained and connected to the A terminal of the comparator 211.
Supplied to the latch circuit 204 according to the timing signal t2.
The loop read from the assignment memory 100
The top information is obtained and supplied to the B terminal of the selector 212.
These loop end information and loop top information are
For changing the shape reading method to the Head + Loop method
For example, an address as shown in FIG. 5 is generated.
This is the information to make it work. In addition, wavetable address
The generator 200 performs calculations for 16 channels.
Therefore, the address read by the Head + Loop method
Less than 16 types are generated simultaneously in one sampling period
It is, of course, possible. The latch circuit 205 is provided with a timing signal.
Read from the assignment memory 100 by the number t1
Obtained enable information is supplied to the gate 216.
This enable information is keyed by the host CPU 30.
Is temporarily turned off at the time of the
FACC stored in the FACC memory 214
Is cleared. Further, the latch circuit 206 receives the timing signal.
By the signal t4, the FACC from the gate 216 is obtained and added.
It is supplied to the arithmetic unit 210. The adder 210 is connected to the latch circuit 20
3 and the F number from the latch circuit 205.
Add CC and compare the result as FACC
To terminal B of selector 211 and terminal A of selector 212.
You. The comparator 211 is supplied to its A terminal.
Loop end information from the latch circuit 202 and its B end
Compare with FACC from adder 210 supplied to the child
And the loop end information is equal to or greater than the above addition result
(A ≦ B), that is, FACC which is the accumulated value of the F number
Reaches the end of the loop, the result is
To supply. The selector 212 receives the comparison from the comparator 211
As a result, the accumulated value of F number reaches the loop end
The loop top information from the latch circuit 204,
And the accumulated value of F number reaches the loop end
If not, the FACC from the adder 210 is selected.
Then, the selector 212 selects the selected loop top information or
Stores the FACC in the FACC memory 214.
To the upper bit information (b16 to b31) of the information.
It is supplied to the arithmetic unit 213. The adder 213 outputs the signal from the latch circuit 201.
Bias address information and the upper bits from selector 212
(B16 to b31) and add the result
It is supplied to the latch circuit 207. The latch circuit 207 has a timing signal t4
Obtains the addition result from the adder 213, and
Not through the output buffer,
Output as read address. The data stored in the FACC memory 214
Information is read as FACC by gate 216
And output to the latch circuit 206. At this time,
The gate 216 has enable information from the latch circuit 205.
Information is provided. This enable information is provided by host C
PU30 temporarily turns off at key-on event
FACC is cleared at this time
It is. The channel to be used ch. 2 o'clock is also up
The used channel ch. Because it is the same as midnight,
Detailed description is omitted. On the other hand, the wave table address generator
Channel 200, which is an unused channel. Performance for 1
When the calculation is performed, as shown by the dotted line in FIG.
No latch clock of the timing signals t1 to t7 is generated.
No. Therefore, the latch circuits 201 to 207 have
Latch signals of the switching signals t1 to t7 are not supplied.
Therefore, the latch circuits 201 to 207 do not operate, that is,
The contents of the pipeline processing latch are not updated.
Calculation processing of the used channel, for example,
Channel ch. The value latched by the 0 processing remains.
Becomes The unused channel ch. 3 to ch. Fifteen
The operation at the time of the use channel ch. Same as 1:00
Therefore, the detailed description is omitted. Therefore, the unused channel ch. 1 and
ch. 3 to ch. In 15 time slots,
Not only the latches of the latch circuits 201 to 207 but also
Circuits (adder 210, comparator 211,
The selector 212 and the adder 213) do not operate.
And the CMOS elements constituting the circuit are switches
Will be in a state where it does not run. This allows the wavetable
Since the read address of 60 does not change,
There is no need to switch the output of the console 60. The assignment memory 100 and the FACC
The memory 214 is used regardless of whether the channel is used or not.
Addressing circuit 101 and addressing circuit 2 respectively
15 accessed. Next, the envelope generator 300
Will be specifically described. For example, the envelope generator 300
For example, as shown in FIG.
Latch circuits 301 to 301 to which read information is respectively supplied
302 and a multiplier to which the output of the latch circuit 301 is supplied
309 and the output of the latch circuit 302 are supplied.
An arithmetic unit 306 and a multiplier 307; a latch circuit 303;
Gate to which each output of the envelope memory 400 is supplied
310 and a latch circuit to which the output of the gate 310 is supplied
304, outputs of the latch circuit 304 and the multiplier 307
Is supplied from the adder 308 to which the
And a latch circuit 305 supplied thereto.
The output of 305 is the output of the envelope generator 300
Is supplied to the multiplier 700.
The output of the latch circuit 304 is also supplied to the subtractor 306.
The output of the subtractor 306 is also supplied to a multiplier 307.
It has been made. Further, the output of the adder 308
Are stored in the multiplier 309 and the envelope memory 400, respectively.
It is made to be supplied. And the latch circuit 3
01, 302, 303, 304 and 305
The timing signals t7, t6, t1, t as shown in FIG.
7 and t7 are provided, respectively. The envelope generator 3 as described above
00 means that the accumulated value of the envelope is EACC
hand, EACC = (E target value−EACC) × E speed + EA
CC The envelope is gradually increased to the E target value by the following arithmetic expression.
To bring them closer. That is, this envelope generator
300, the channel to be used, ch. Against 0
When the operation is performed, the latch circuit 301
At the falling timing of the signal t7, the assignment
The loudness information read from the memory 100 is obtained,
It is supplied to the arithmetic unit 309. This loudness information is
It is a parameter for controlling the rope value as a whole,
Multiplied by EACC in multiplier 309 and output
is there. Further, the latch circuit 302
Read from the assignment memory 100 by the number t6
E target value / E speed information
The signal is supplied to the A terminal of the subtractor 306,
The information is supplied to the multiplier 307. The latch circuit 303 outputs a timing signal.
Read from the assignment memory 100 by the number t1
Obtained enable information is supplied to the gate 310.
This enable information is keyed by the host CPU 30.
Is temporarily turned off at the time of the
EACC (envelope of the envelope) supplied to the gate 310
(Accumulated value) is cleared. Also, the latch circuit 304
With the signal t7, the EACC from the gate 310 is obtained and reduced.
It is supplied to the B terminal of the arithmetic unit 306 and the adder 308. The subtractor 306 is connected to its A terminal.
From the supplied E target value information from the latch circuit 302,
EACC from the latch circuit 304 supplied to the B terminal of
Is subtracted (E target value−EACC). So this
By subtracter 306, how much EACC is not equal to E target value
Is required. The multiplier 307 calculates the subtraction result of the subtractor 306.
And E speed information from the latch circuit 302, that is,
Multiply by the rate at which the EACC reaches the E target
((E target value−EACC) × E speed) and its multiplication result
The result is supplied to the adder 308. The adder 308 calculates the multiplication result of the multiplier 307.
And EACC from the latch circuit 304, that is,
EACC and ((E target value−EACC) × E speed)
+ EACC), and the addition result is used as the current EACC.
Supplied to the multiplier 309 and the envelope memory 400
I do. The multiplier 309 outputs the EA from the adder 308
CC and the loudness information from the latch circuit 301 are multiplied.
The result is supplied to the latch circuit 305. The latch circuit 305 has a timing signal t7
, The multiplication result from the multiplier 309 is obtained. This
The multiplication result latched by the switch circuit 305
Envelope value which is the output of the loop generator 300 and
Then, it is supplied to the multiplier 200. The channel to be used ch. 2 o'clock is also up
The used channel ch. Because it is the same as midnight,
Detailed description is omitted. On the other hand, the envelope generator 300
An unused channel ch. An operation is performed on 1
If the above mentioned wavetable address generator
As in the case of 200, as shown by the dotted line in FIG.
No latch clock of the imaging signals t1 to t7 is generated.
No. Therefore, the latch circuits 301 to 305
Latch signals of the switching signals t7, t6 and t1 are supplied.
Therefore, the latch circuits 301 to 305 do not operate.
The operation processing of the used channel performed in the
Channel ch. The value latched by the processing of 0 remains
It will be. The unused channel ch. 3 to ch. Fifteen
The operation at the time of the use channel ch. Same as 1:00
Therefore, the detailed description is omitted. Therefore, the unused channel ch. 1 and
ch. 3 to ch. In 15 time slots,
Latch circuits 301 to 305, as well as a subtractor 3
06, multiplier 307, adder 308 and multiplier 309
Does not work, keeps the same value during this time, configures the circuit
The CMOS element does not switch. Next, the accumulator 500 will be specifically described.
I will tell. The accumulator 500 is, for example, as shown in FIG.
Circuit 5 to which the multiplication result of the multiplier 700 is supplied
01 and information read from the assignment memory 100.
And a latch circuit 502 to which information is supplied.
Circuit 503 to which the output of
01 and a gate to which each output of the latch circuit 503 is supplied.
510 and an adder 51 to which the output of the gate 510 is supplied
1 and the latch circuit 50 to which the output of the adder 511 is supplied.
4 and a latch to which the output of the latch circuit 504 is supplied, respectively.
Circuit 513 and a gate 512,
The output of the path 513 is the output of the accumulator 500, that is, the way.
Is supplied to the DAC 70 as the output of the
It has been made. The output of the gate 512 is
The data is supplied to an adder 511. Soshi
The latch circuits 501 to 504 have the configuration shown in FIG.
Such a timing signal t0 is provided, and a latch circuit
The channel ch. 513 as shown in FIG. 1
Is given. Also the gate
512, the timing signal ts1 is output from the inverter 5
12a. Incidentally, the timing signal t0 is, as described above,
Is always output regardless of whether the channel is used or not.
Therefore, the latch circuits 501 to 504 use channels,
The timing signal t0 is always supplied regardless of whether it is unused.
You. Further, the timing signal ts1 also uses the channel,
Since it is always output irrespective of unused state, the latch circuit 51
3 and the gate 512 indicate whether the channel is used or not.
Instead, the timing signal ts1 is always supplied. The accumulator 500 as described above is time-divisionally
Generated 16-channel tone data (sample points
Value). Here, as described above, the USE signal is
In the case of “1”, that is, in the case of the used channel,
Address by the address table 200
While the waveform data is read out from the
The envelope is generated by the envelope generator 300.
Generated and read waveform data and generated envelope
The rope is multiplied by multiplier 700. On the other hand, the USE signal
Is “0”, that is, in the case of an unused channel,
Wavetable address generator 200 and end
The envelope generator 300 retains the previous data
Therefore, the multiplier 700 outputs the previous power
The calculation result is output. Therefore, in this case
Need to clear (gate) the result of the multiplication. Therefore, in this accumulator 500, unused channels
Data from the multiplier 700 input at the timing of the channel
Data gates. That is, first, as described above, the envelope
Timing generator from rope generator 300 to multiplier 700
That the envelope is supplied at the timing of the
Thus, the multiplier 700 also supplies the latch circuit 501 with
The multiplication result is supplied at the timing of the imaging signal t7.
You. The latch circuit 501 controls the timing and
Considering the timing, the next timing of the timing signal t7
Provided for re-latching at the signal t0,
By the timing signal t0, the power from the multiplier 700
The calculation result is obtained and supplied to the gate 510. On the other hand, the latch circuits 502 and 503
Wave table address generator 200 and envelope
Delay caused by the arithmetic processing of the rope generator 300
This is provided to make this one channel.
Therefore, the latch circuit 502 outputs the timing signal t0
As a result, the output of the assignment memory 100 is obtained.
The latch circuit 503 supplies the
The output of the latch circuit 502 is obtained by the imaging signal t0.
The control signal is supplied to the gate 510 as a control signal. Gate 510 receives the signal from latch circuit 503
The control signal causes the
Data from the latch circuit 501 to the adder 511 as it is.
Supply, and in the case of an unused channel, a latch circuit 501
Is cleared and supplied to the adder 511. The adder 511 outputs the output of the gate 510 and the gate.
Add the output of port 512 and supply it to latch circuit 504
Then, the latch circuit 504 operates in response to the timing signal t0.
The addition result from the arithmetic unit 511 is obtained and the result is obtained through the gate 512.
It is supplied to the adder 511. Such accumulation processing is
Nell ch. 0 to ch. 15 hours. At this time, the gate 512 is connected to the inverter 5
12a via the timing signal ts1
When the accumulation process for 16 channels is started,
The data (accumulated result) from the switch circuit 504 is cleared.
Here, as described above, the latch circuits 501 to 503
Therefore, the data supplied to the adder 511 is one channel
Channel ch. At 1
Adder 511 has channel ch. 0 data is input
You. Therefore, the contents (accumulated result) of the latch circuit 504 are cleared.
Is determined by the timing of the timing signal ts1.
I'm trying. The 16 channels obtained as described above
The accumulation result is supplied to the latch circuit 513,
Reference numeral 513 denotes 16 channels based on the timing signal ts1.
Is obtained, and the accumulation result is output from the accumulator 500.
To the DAC 70. Next, the system clock generator 6
00 will be specifically described. The system clock generator 600 includes:
For example, as shown in FIG.
Circuit 601 to which the information read from is supplied
, The counter 602, and the output of the counter 602, respectively.
The supplied AND circuit 603 and counter 610,
An AND circuit 611 to which an output of the counter 610 is supplied;
Latch circuit 604t0 to which the output of ND circuit 603 is supplied
To 604t7, latch circuits 601 and 604t0 to 604
a gate 608 to which each output of t7 is supplied, and an AND circuit 6
Latch circuits 612ts0 to 612 to which 11 outputs are supplied
ts15, and the output of the latch circuit 604t0 is
The output of the gate 608 is output as the
Output as timing signals t1 to t7,
The output of each of the switch circuits 612ts0 to 612ts15 is a timing signal.
No. ts0 to ts15 are output.
You. Then, the latch circuit 601 and the latch circuit 612ts
The timing signal t0 is given to 0 to 612ts15,
For the counter 602 and the latch circuits 604t0 to 604t7
Is supplied with a clock signal ck. The system clock generator as described above
The timing signal t as shown in FIG.
0 to t7 and timing signals ts0 to ts15
Generates the latch clock of each latch circuit that constitutes the pipeline.
Is what it does. That is, the system clock generator
At 600, first, the latch circuit 601
The assignment memory 100 at the timing of the
The USE information is obtained and supplied to the gate 608. Generated by the synchronous type counter 602
The counted value is input to an AND circuit 603,
The output when all become “1” in the circuit 603 is
It is obtained by the clock signal ck in the switching circuit 604t0. This
The output of the latch circuit 604t0 at the time of
Output as 0. The latch circuit 604t1 receives the clock signal.
With the signal ck, the output of the latch circuit 604t0 is obtained.
The signal is supplied to the gate 608 as the mining signal t1. Also,
The latch circuit 604t2 latches the clock signal ck.
The output of the switch circuit 604t1 is obtained and used as a timing signal t2.
To the gate 608. Further, the latch circuit 604
t3 is the time required for the latch circuit 604t2 by the clock signal ck.
The output is obtained and the timing signal t3 is supplied to the gate 608.
Supply. The same applies to the subsequent latch circuits 604t3 to 604t7.
Then, the clock signal ck causes the latch circuit of the preceding stage to
An output is obtained, and the timing signal t3 to t7 is output to the gate 6
08. The gate 608 receives the signal from the latch circuit 601.
If the USE information is “1”, that is,
If the latch circuit 604t1 to 604t7
The timing signals t1 to t7 are output and the latch circuit 601 is output.
If the USE information from is “0”, that is,
604t1 to 604
The timing signals t1 to t7 from t7 are not output. Therefore, this gate 608 makes use of
For each channel only,
The latch clock of the switch circuit is output. On the other hand, the synchronous type counter 610
AND the count value according to the count value of the
Occurs for circuit 611. And the AND circuit 61
The output when all become “1” at 1 is the latch circuit 6
It is obtained by the timing signal t0 at 12ts0. This and
The output of the latch circuit 612ts0 is the timing signal ts
Output as 0. The latch circuit 612ts1 has a timing
The output of the latch circuit 612ts0 is obtained by the switching signal t0.
Then, it is output as the timing signal ts1. Also,
The latch circuit 612ts2 is latched by the timing signal t0.
The output of the switch circuit 612ts1 is obtained and the timing signal ts2
Output as Subsequent latch circuits 612ts3 to 612
Similarly, ts15 is also provided by the timing signal t0 in the preceding stage.
The output of the latch circuit is obtained, and the timing signals ts3 to ts
15 is output. As described above, the electronic musical instrument 1
The USE information stored in the
Timing signal t1 of each latch circuit forming the pipeline
~ T7 should not occur in the case of an unused channel
And minimize the number of switching of each circuit during this time
Configuration to achieve total power savings.
Can be In particular, configuring a general-purpose sound source LSI
The mainstream is CMOS with large power consumption during switching
Because of this, regardless of the output level Low / High
By reducing the number of switching times of each circuit as much as possible.
Therefore, further power saving can be achieved. Also this
By reducing power consumption, the amount of electromagnetic wave radiation is relatively reduced
Can be reduced. In the above-described embodiment, the aforementioned c
The wave generator 50 is used to generate musical sound data.
In addition, the wave table 60 provided outside the
It is assumed that shape data is obtained.
Generate waveform data inside the generator 50
You may. That is, the present invention provides an externally provided waveform.
Way adopting the method of reading waveform data from ROM
Not only for generators but also for signature synthesis and FM sound sources
It can also be applied to wave generators using formulas
it can. In the above-described embodiment, the speaker
The tone generated by the 80 is emitted.
Headphones or earphones instead of the
Sound from headphones or earphones
No. As a result, further power savings can be achieved.
You. [0098] As described above, according to the present invention, the pronunciation
Channel usage status (whether in use or unused)
Based on the channel information indicating the
Multiple controls for music data generation corresponding to channels
Data (read address of waveform data in waveform memory)
For generating a wavetable address generator,
And an envelope generator for generating envelope values
Latch data for each of multiple
Control means for supplying a latch signal to the
Time of unused sound channels
In the slot, the read address of the waveform memory
Can be held as it is. this
The output of the waveform memory is switched during this time.
And the arithmetic elements inside the device are also switched.
Absent. So, for example, the wavetable address
Music with generator and envelope generator
In the circuit (wave generator) for generating sound data
Because the number of switching of the unit can be reduced, the device
Can achieve total power saving. repeat
However, a general-purpose LSI is most often used for switching.
Since CMOS, which consumes large power, is mainstream,
By applying the present invention, the output level is captured at Low / High.
Minimizing the number of switching of each element
Thus, further power saving can be promoted. This
The amount of electromagnetic radiation can be reduced by
Can also be relatively reduced. Also, unused pronunciation
Previous use in channel time slots
Data obtained in the time slot of the sound channel
Output the same tone data as
You can gate before calculating
Each time data is output, the same tone data is accumulated
Can be prevented. Therefore,
Total power saving can be achieved without any inconvenience. Sa
In addition, in the time slot of the unused sound channel
Cannot receive the latch clock signal to the latch means.
Therefore, the processing circuit after the latch means is not switched.
State. Therefore, further total power saving
Note that here, switching
Shows CMOS as an element that consumes a lot of power
However, the effects of the present invention can be obtained by devices having similar characteristics.
Is not limited to CMOS.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing the configuration of an electronic musical instrument to which an electronic musical tone generator according to the present invention is applied. FIG. 2 is a timing chart showing a timing clock in a wave generator. FIG. 3 is a diagram for explaining a memory format of an assignment memory. FIG. 4 is a block diagram illustrating a configuration of a wavetable address generator. FIG. 5 is a diagram for explaining addresses generated by the Head + Loop method. FIG. 6 is a block diagram illustrating a configuration of an envelope generator. FIG. 7 is a block diagram showing a configuration of an accumulator. FIG. 8 is a block diagram showing a configuration of a system clock generator. [Description of Signs] 1 Electronic musical instrument 10 Keyboard 20 Operation panel 30 Host CPU 40 Sequencer 50 Wave generator 60 Wave table 70 DAC 80 Speaker 100 Assignment memory 200 Wave table address generator 300 Envelope generator 400 Envelope memory 500 Accumulator 600 System clock Generator I51 to I55 I / O terminal

Claims (1)

(57) [Claims] [Claim 1] A plurality of musical sound data is generated by time division,
An electronic tone generator for outputting tone data for a plurality of tone channels, wherein a plurality of control data for generating the plurality of tone data and channel information indicating a use state of the tone channels are externally provided for each tone channel. A storage unit that stores the control unit and controls reading of the storage unit such that a plurality of control data and channel information are read from the storage unit for each sounding channel in synchronization with a time slot of each sounding channel; Latch means for latching a plurality of control data for each sounding channel read from the storage means; and latch signal supply means for selectively supplying a latch signal to the latch means for each sounding channel, The latch signal supply unit is configured to generate an unused sounding channel based on the channel information read from the storage unit. In time slot, La to said latch means
By not supplying the latch signal,
Control means for unused sound channels
An electronic musical tone generating device characterized in that it is not latched .