JP3364784B2 - Information processing device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus for processing information, such as a large computer, and more particularly,
It belongs to an information processing apparatus having a data transfer device that controls transfer of data between a main storage device and a data processing device.

[0002]

2. Description of the Related Art As shown in FIG. 4, a conventional information processing apparatus includes a main storage device 100 for storing data and a data processing device 300 for reading and writing data from the main storage device 100.
And a data transfer device 200 that controls the transfer of data between the main storage device 100 and the data processing device 300.

The transfer in this information processing apparatus is divided into two types: a synchronous transfer that operates in synchronization with the arithmetic processing unit and an asynchronous transfer that operates independently of the arithmetic processing unit. It is possible to transfer by address or logical address. The information processing apparatus includes a data transfer apparatus 200 connected to the main storage apparatus 100 and a data processing apparatus 30 connected via a serial interface.
It is used for data transfer with 0.

Data transfer device 200 and data processing device 3
When data is transferred between 00 and 00 in frame data units, the transfer rate on the serial interface is increased by reducing the data transfer amount of the frame data transferred on the serial interface.

Further, by reducing the amount of data to be transferred, the number of times of data transfer retransmission due to a data error occurring on the serial interface is reduced and the transfer performance is improved.

The main storage device 100 is a data processing device 30.
Read and written by 0. The data transfer device 200 receives data from the main storage device 100 according to an instruction from the data processing device 300.
Read / write control.

The data transfer device 200 has a data transfer control circuit. The data transfer control circuit 210 adds the control information generated by the control information generation circuit 211 to the data 213 read from the main storage device 100.

Further, according to the control information 215 of the frame data transferred from the data processor 300, the main memory 1
The data 216 is written to 00.

FIG. 5 shows an example of frame data. In this example, 8-byte transfer is performed. In FIG.
SD is Start Delimiter, ED is END
It is a Delimiter.

The frame generation circuit 220 provided in the data transfer device 200 generates frame data in which the control information 215 is added to the data format stored in the main storage device 100. The serial conversion circuit 230 included in the data transfer device 200 and the serial conversion circuit 360 included in the data processing device 300 are
Convert frame data to serial data. Parallel conversion circuit 26 provided in the data transfer device 200
0, the parallel conversion circuit 320 included in the data processing device 300 converts serial data into parallel data. A frame conversion circuit 270 included in the data transfer device 200 and a frame conversion circuit 330 included in the data processing device 300 convert parallel data into frame data. The transmission circuit 240 and the reception circuit 250 included in the data transfer device 200, and the 370 and the reception circuit 31 included in the data processing device 300.
0 transmits and receives serial data via the serial interface 1a. The serial interface is an optical fiber cable, an electric cable, or the like.

Next, the operation will be described. Main memory 100
When data is transferred from the data processing device 300 to the data processing device 300, the data transfer control circuit 210 in the data transfer device 200 reads the data stored in the main storage device 100, and the control information generation circuit 211 generates control information.

The frame generation circuit 220 is used for the main memory device 10.
The frame data in which the control information having the meaning in the bit unit is added to the data format stored in 0 is generated. In order to transfer the frame data generated by the frame generation circuit 220 on the serial interface 1a, the serial conversion circuit 230 converts the frame data into serial data, and the transmission circuit 240 transfers the serial interface 1a to the data processing device 300. To send over.

The serial data transmitted from the data transfer apparatus 200 via the serial interface 1a is received by the receiving circuit 310 in the data processing apparatus 300, and the parallel converting circuit 320 converts the serial data into parallel data. The converted parallel data is converted into frame data by the frame conversion circuit 330, and is thereby returned to the frame data generated by the frame generation circuit 220 in the data transfer device 200.
The data processing control circuit 340 processes the data read from the main storage device 100 according to the control information 342.

From data processor 300 to main memory 10
When transferring data to 0, the data processing control circuit 34
From 0 to the main storage device 10 via the data transfer device 200.
In order to transfer the data to 0, the control information generation circuit 344 generates control information for the data to be written in the main storage device 100 in the data processing circuit 340 in the data processing device 300, and the frame generation circuit 350 generates frame data. The frame data generated by the frame generation circuit 350 is converted into serial data by the serial conversion circuit 360 for transfer on the serial interface, and the transmission circuit 370.
To the data transfer device 200 via the serial interface 1a.

The serial data transmitted from the data processing device 300 is received by the receiving circuit 250 in the data transfer device 200.
Receives serial data at the parallel conversion circuit 260
Convert serial data to parallel data with. The converted parallel data is converted into frame data by the frame conversion circuit 270, so that the data processing device 30
The data 216 returned to the frame data generated by the frame generation circuit 350 in 0 and transferred from the data processing device 300 according to the control information 215 in the data transfer control circuit 210 is written in the main storage device 100.

[0016]

Conventionally, in the data transfer method between the data transfer device 200 and the data processing device 300 connected by the serial interface, the frame data is directly converted into the serial data for transfer on the serial interface. Transferring. Therefore, there is a problem that the transfer time is slow according to the data transfer amount between the devices and the data transfer speed is slow.

Further, when a data error occurs on the serial interface, the transferred data is retransmitted, so that the transfer performance is deteriorated.

Therefore, it is an object of the present invention to provide an information processing apparatus capable of checking decoded control information and improving reliability.

[0019]

According to the present invention, there is provided a main storage device for storing data, a data processing device for reading and writing data from the main storage device, and a main storage device and the data processing device. In an information processing device including a data transfer device for controlling the transfer of data, the control information check circuit and the coding circuit are provided on the transmission side so as to transfer the frame data by coding the control information, and the reception side. It is possible to obtain an information processing apparatus characterized in that a decoding circuit and a control information check circuit are provided in the.

[0020]

In the information processing apparatus of the present invention, a large amount of data is transferred in the data transfer of a general-purpose large computer. Therefore, in order to reduce the transfer amount of serial data, a control information check circuit and a coding circuit are provided on the transmission side for checking. The control information is coded according to the result and the frame data is transferred. A decoding circuit and a control information check circuit are provided on the receiving side to check the decoded control information and improve the reliability.

[0021]

BEST MODE FOR CARRYING OUT THE INVENTION Next, an information processing apparatus of the present invention will be described with reference to the drawings. FIG. 1 shows an embodiment of an information processing apparatus of the present invention. Note that the same parts as those of the conventional information processing apparatus shown in FIG.

Referring to FIG. 1, the information processing apparatus according to the embodiment is similar to the conventional information processing apparatus shown in FIG.
It is provided with the encoding circuit 212 provided in the data transmission control circuit 210 and the data processing control circuit 340 so that the control information is encoded if the control information is correct as a result of checking if there is no illegal control information. A coding circuit 345, a decoding circuit 214 provided in the data transmission control circuit 210 so as to decode the control information coded in the data transfer control circuit 210, and a decoding circuit 341 provided in the data processing control circuit 340. , A control information check circuit 21 provided in the data transmission control circuit 210 so as to check whether there is illegal control information.
7 and a control information check circuit 347 provided in the data processing control circuit 340.

The information processing apparatus will be specifically described below with reference to FIG. The main storage device 100 is the data processing device 3
Read and write by 00. The data transfer device 200 is
The main storage device 10 is instructed by the data processing device 300.
Read / write control to 0. Data transfer control circuit 210
Adds the control information generated by the control information generation circuit 211 to the data 213 read from the main storage device 100.

Further, according to the control information 215 of the frame data transferred from the data processor 300, the main memory 1
The data 216 is written to 00.

FIG. 2 shows an example of frame data. In FIG. 2, SD is a Start Delimiter,
ED is an END Delimiter. Referring to FIG. 2, if 8-byte control information is coded, it becomes 6 bits, and 8 bytes have been conventionally transferred, but in the present invention, 1 byte is enough.

The frame generation circuit 220 uses the main memory 1
Frame data in which control information is added to the data format stored in 00. The serial conversion circuits 230 and 360 convert frame data into serial data. The parallel conversion circuits 260 and 320 convert serial data into parallel data. The frame conversion circuits 270 and 330 convert parallel data into frame data. Transmitter circuits 240, 370 and receiver circuit 2
Reference numerals 50 and 310 transmit / receive serial data via the serial interface 1a. The serial interface 1a is an optical fiber cable, an electric cable, or the like.

Next, the operation will be described. Main memory 100
When data is transferred from the data processing device 300 to the data processing device 300, the data control circuit 210 in the data transfer device 200 reads the data stored in the main storage device 100, and the control information generation circuit 211 generates control information.

FIG. 3 shows an example of the fraud control information.
The control information check circuit 217 checks whether there is any illegal control information shown in FIG. As a result of checking,
If the control information is correct, the coding circuit 212 codes the control information. If there is illegal control information, it is reported to the main storage device 100 as a failure without being encoded.

The frame generation circuit 220 is used for the main memory device 10.
The frame data in which the encoded control information is added to the data format stored in 0 is generated. However, when the control information check circuit 216 detects a failure, an error frame is generated. Frame generation circuit 220
In order to transfer the frame data generated in 1 above on the serial interface 1a, the serial conversion circuit 230 converts the frame data into serial data, and the transmission circuit 24
From 0 to the data processing device 300 via the serial interface 1a.

The serial data transmitted from the data transfer device 200 via the serial interface 1a is received by the receiving circuit 310 in the data processing device 300, and the parallel converting circuit 320 converts the serial data into parallel data. The converted parallel data is converted into frame data by the frame conversion circuit 330, and is thereby returned to the frame data generated by the frame generation circuit 220 in the data transfer device 200.
The control information encoded by the decoding circuit 341 in the data processing control circuit 340 is decoded. The decoded control information 342 is checked by the control information check circuit 347 for the presence of illegal control information shown in FIG. If the check result shows that the control information is correct, the control information 342 is displayed.
Data 343 read from the main storage device 100 according to
To process. If the control information is invalid, it is reported to the data transfer device 200 as a failure.

From the data processing device 300 to the main memory 10
When transferring data to 0, the data processing control circuit 34
0 to the main storage device 100 via the data transfer device 200
Data to be written to the main storage device 100 by the data processing control circuit 340 in the data processing device 300, the control information generation circuit 344 generates the control information, and there is no illegal control information shown in FIG. To check. If the check result shows that the control information is correct, the encoding circuit 34
The control information is coded at 5. If the control information is incorrect, it is reported to the data transfer device 200 as a failure without being encoded. The frame generation circuit 350 generates frame data in which control information encoded in the data format stored in the main storage device 100 is added. However, when the control information check circuit 347 detects a failure, an error frame is generated.

The frame data generated by the frame generation circuit 350 is converted into serial data by the serial conversion circuit 360 for transfer on the serial interface, and is transmitted from the transmission circuit 370 to the data transfer device 200 via the serial interface 1a. Send. Regarding the serial data transmitted from the data processing device 300, the receiving circuit 250 in the data transfer device 200 receives the serial data, and the parallel conversion circuit 260 converts the serial data into parallel data. The converted parallel data is converted into frame data by the frame conversion circuit 270 to be returned to the frame data generated by the frame generation circuit 350 in the data processing device 300, and the decoding circuit 214 in the data transfer control circuit 210. Decode the control information encoded in. The decoded control information 215 is checked by the control information check circuit 216 for the presence of illegal control information shown in FIG.

As a result of the check, if the control information is correct, the data 216 transferred from the data processing device 300 according to the control information 215 is written in the main storage device 100. If the control information is invalid, it is reported to the main storage device 100 as a failure.

[0034]

As described above with reference to the embodiment, the information processing apparatus of the present invention reduces the transfer amount of serial data because the transfer data amount of a general-purpose large computer is large. For this purpose, a control information check circuit and a coding circuit are provided on the transmission side, the control information is coded according to the check result to transfer frame data, and a decoding circuit and a control information check circuit are provided on the reception side, so decoding is performed. The control information can be checked and reliability can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of an information processing apparatus of the present invention.

FIG. 2 is an explanatory diagram showing an example of frame data of the present invention.

FIG. 3 is an explanatory diagram showing an example of fraud control information.

FIG. 4 is a block diagram showing a conventional information processing apparatus.

FIG. 5 is an explanatory diagram showing an example of conventional frame data.

[Explanation of symbols]

100 main memory 210 data transfer control circuit 211, 344 Control information generation circuit 212 coding circuit 213,216,343,346 data 214,341 decoding circuit 215, 342 control information 220 frame generation circuit 230 Serial conversion circuit 240,370 Transmitter circuit 250,310 Receiver circuit 260,320 Parallel conversion circuit 270,330 Frame conversion circuit 300 data processor 344 Control information generation circuit 347 Control information check circuit

Claims (3)

(57) [Claims] 1. A main storage device for storing data, a data processing device for reading and writing data from the main storage device, and a data transfer device for controlling data transfer between the main storage device and the data processing device. In an information processing device including: a control information check circuit and a coding circuit are provided on the transmission side and a decoding circuit and a control information check circuit are provided on the reception side so as to transfer the frame data by coding the control information. An information processing device characterized by the above. 2. A main memory device for storing data, a data processing device having a data processing control circuit for reading and writing data from the main memory device, a main memory device having the data transfer control circuit, and the data processing device. In an information processing device that includes a data transfer device that controls the transfer of data to and from the device, check whether there is unauthorized control information,
As a result of the check, if the control information is correct, the encoding circuit provided in the data transmission control circuit so as to encode the control information, the encoding circuit provided in the data processing control circuit, and the data transfer control circuit A decoding circuit included in the data transmission control circuit for decoding coded control information, and a decoding circuit included in the data processing control circuit, and the data transmission to check whether there is illegal control information An information processing apparatus comprising: a control information check circuit provided in a control circuit; and a control information check circuit provided in the data processing control circuit. 3. The information processing apparatus according to claim 1,
The control information check circuit checks whether or not there is illegal control information, and if the control information is correct, the control information is encoded by the encoding circuit, and if there is illegal control information, it is not encoded. An information processing device, which reports to the main storage device as a failure.