JP3364988B2 - Semiconductor device, liquid crystal driving device and electronic equipment - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a structure of a liquid crystal driving device for driving a liquid crystal display device.

[0002]

2. Description of the Related Art Conventionally, in a liquid crystal driving device, in order to freely correspond to a liquid crystal display device, the setting of the address signal and the data signal is performed by a hardware changeover switch. Further, when a control device such as a central processing unit is provided externally to control a plurality of liquid crystal driving devices and the like, in order to select only one liquid crystal driving device, an enable terminal is provided for each liquid crystal driving device. Is provided, and the selection signal is given only to the necessary apparatus to select each apparatus. Further, the liquid crystal driving power source is fixed for each device, and the bias of the liquid crystal driving voltage is fixed in most cases.

[0003]

When a semiconductor device or the like is used as a hardware changeover switch for changing the setting of the above-mentioned address signal and data signal,
Once you switch the switch, you cannot change it again. Therefore, it becomes impossible to meet various demands of users of the liquid crystal display device , and when the liquid crystal drive device is incorporated in the emulation system of the microcomputer having the liquid crystal drive device built therein, the liquid crystal drive allocation is fixed. However, there is a problem that it cannot be arbitrarily set so as to correspond to all switch patterns.

Further, when the pull-down resistor is connected to the input circuit, it is performed by the hardware changeover switch. Therefore, when the pull-down resistor is connected by the changeover switch, it is impossible to remove it after that. there were. Further, in a system in which the control device outputs only signals such as an address signal, a data signal and a write signal like a central processing unit, there is a problem that a dedicated selecting device for selecting the liquid crystal driving device must be provided. there were. In addition, when the liquid crystal driving device is incorporated in a microcomputer emulation system, it is necessary to adapt it to various types of microcomputer systems, but the bias of the liquid crystal driving voltage is fixed in most cases. However, there is a problem that various kinds of liquid crystal driving bias cannot be realized.

An object of the present invention, Ru near to provide a semiconductor apparatus which can be set assignment data arbitrarily. Another object of the present invention is to provide a liquid crystal drive device in which allocation of liquid crystal drive data can be arbitrarily set. Another object of the present invention is to provide a liquid crystal driving device that allows selection of a liquid crystal driving device without providing a dedicated selecting device. Another object of the present invention is to provide a liquid crystal driving device capable of realizing various liquid crystal driving biases. Still another object of the present invention is to provide an electronic device incorporating the above-mentioned semiconductor device or liquid crystal driving device.

[0006]

According to one aspect of the present invention, a semiconductor device (Claim 1) is provided with an allocation address storage device (1104) for supplying and storing allocation addresses, and allocation data is supplied and stored. Allocation data storage device (11
03) with the control address and the allocation address stored in the allocation address storage device, and comparing the both addresses, and sending an output signal when they match, the address comparison device (1106) and the control Selection data (1105), which is supplied with data for control and selects bit information of the control data based on the allocation data stored in the allocation data storage device, and bit information of the control data selected by the data selection device. Is stored based on the output signal of the address comparator (11)
09) and.

According to another aspect of the present invention, there is provided a liquid crystal driving device (claim 2) in which an allocation address storage device (1104) for storing an externally supplied liquid crystal allocation address and an externally supplied liquid crystal allocation data are stored. An allocation data storage device (1103) that compares the address of the liquid crystal display supplied from the outside with the allocation address stored in the allocation address storage device, and outputs an output signal when they match (1106). ), The bit information of the liquid crystal display data supplied from the outside is selected based on the allocation data stored in the allocation data storage device (1105), and the liquid crystal selected by the data selection device. A liquid crystal display data storage device (11) which stores and outputs bit information of display data based on an output signal of the address comparison device. 9) and a. A liquid crystal driving device according to another aspect of the present invention (claim 3) is a plurality of liquid crystal driving circuits (702, provided for driving a liquid crystal display device).
, And each liquid crystal drive circuit has a liquid crystal cell allocation circuit (1001, 1002, ...) Provided corresponding to the signal line of the liquid crystal segment of the liquid crystal display device. The liquid crystal cell allocation circuit is supplied from the outside with an allocation address storage device (1104) which stores the liquid crystal allocation address supplied from the outside, an allocation data storage device (1103) which stores the liquid crystal allocation data supplied from the outside. Address comparing device (1106) which outputs an output signal when the address for liquid crystal display and the assigned address stored in the assigned address storage device are compared with each other, and bit information of liquid crystal display data supplied from the outside. Is selected based on the allocation data stored in the allocation data storage device, and the bit information of the liquid crystal display data selected by the data selection device is based on the output signal of the address comparison device. And a liquid crystal display data storage device (1109) for storing and outputting. According to another aspect of the present invention, there is provided a liquid crystal driving device (claim 4), wherein in the liquid crystal driving device (claim 3), each liquid crystal driving circuit is supplied from the outside with an address setting terminal for setting an address. An address is compared with an address set in the address setting terminal, and a comparison device (802) that outputs according to the comparison result is provided, and is selected as a drive target by the output of the comparison device.

According to another aspect of the present invention, there is provided a liquid crystal driving device (claim 5), which is different from the liquid crystal driving device (claims 3 and 4) in that the power source device outputs a plurality of different voltages. A plurality of different voltages are selected based on bit information stored in a liquid crystal display data storage device and output to a segment signal line (SEG) of a liquid crystal segment.
Second selection device (905) for selecting a plurality of different voltages from the power supply device and outputting the selected voltages to the plurality of common signal lines (COM0 to COM7) of the liquid crystal segment of the liquid crystal display device.
Selection device (1205, 1206). An electronic apparatus according to another aspect of the present invention (claims 6 and 7) has the above-described semiconductor device or liquid crystal driving device built therein.

[0009]

In the semiconductor device according to one aspect of the present invention (claim 1), the allocation address is supplied to the allocation address storage device and stored in advance, and the allocation data storage device is supplied with the allocation data and stored therein. It The address comparison device is supplied with the control address and the allocation address stored in advance in the allocation address storage device, compares the two addresses, and outputs an output signal when they match. The control data is supplied to the data selection device, and bit information of the control data is selected based on the allocation data stored in the allocation data storage device. The selected data storage device stores the bit information of the control data selected by the data selection device based on the output signal of the address comparison device. Thus, the bit information of the control data can be arbitrarily selected and stored on the basis of allocation data, Ru can emulate various devices.

In the liquid crystal drive device according to another aspect of the present invention (claims 2 and 3), the allocation address storage device receives the liquid crystal allocation address from an external device and stores it. Liquid crystal allocation data is supplied from an external device to the allocation data storage device and stored therein. The address comparison device
The liquid crystal display address supplied from the external device is compared with the assigned address stored in the assigned address storage device, and when they match, an output signal is output. Then, the data selection device selects the bit information of the liquid crystal display data supplied from the external device based on the allocation data stored in the allocation data storage device. The liquid crystal display data storage device stores the data selected by the data selection device based on the output signal of the address comparison device. Therefore, since the bit information of the liquid crystal display data supplied from the external device can be arbitrarily selected based on the allocation data, various liquid crystal drive devices can be emulated, and device development and manufacturing for each system can be performed. Is unnecessary. In a liquid crystal drive device according to another aspect of the present invention (claim 4), the comparison device compares the address set in the address setting terminal with the address supplied from the external device, and drives according to the comparison result. The target liquid crystal drive circuit is selected.

In the liquid crystal drive device according to another aspect of the present invention (claim 5), the power supply device outputs a plurality of different voltages. The first selection device stores a plurality of different voltages from a power supply device in the liquid crystal display data storage device.
It is selected based on the bit information and output to the segment signal line (SEG) of the liquid crystal segment. The second selection device also selects a plurality of different voltages from the power supply device and outputs the selected voltages to the common signal lines (COM0 to COM7) of the liquid crystal segment. Therefore, the segment signal line (SEG) of the liquid crystal segment and the common signal lines (COM0 to COM7) of the liquid crystal segment are generated by the first selection device and the second selection device.
The voltage applied to can be set arbitrarily. In a liquid crystal drive device according to another aspect of the present invention (claim 6), a decoder is supplied with a switch data setting address signal from an external device and is decoded to generate a data setting write signal only when a predetermined address signal is received. Is output. When receiving the data setting write signal, the switching data storage unit stores the switching data signal supplied from the outside. Opening / closing of the analog switch is controlled based on the switching data signal. For example, when the analog switch is closed, a pull-down resistor is connected to the input terminal, and when the analog switch is open, the pull-down resistor is invalidated. Therefore, it is possible to arbitrarily enable or disable the pull-down resistor. In an electronic device according to another aspect of the present invention (claims 7 and 8) , the semiconductor device or the liquid crystal driving device described above is built in, and the electronic device can be adapted to various applications.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram showing a configuration in which a liquid crystal drive device according to an embodiment of the present invention is incorporated in a microcomputer system. In the figure, when the program storage device 101 receives an address signal from the central processing unit 102, it outputs stored program instructions to the central processing unit 102. The central processing unit 102 is
When the program command is interpreted and executed, an address signal and a data signal are output to the input / output device 103, the liquid crystal drive device 104 or the data storage device 105 based on the result, and the input / output device 103 or the data storage device is also output. A data signal is taken in from the device 105.

FIG. 2 shows the relationship between the memory map for controlling the peripheral devices of the input / output device 103, the liquid crystal driving device 104 and the data storage device 105 of FIG. 1 and the liquid crystal display device connected to the liquid crystal driving device 104. It is the figure which showed. The memory map in the figure comprises a data memory area 201, a liquid crystal drive memory area 202, and an input / output memory area 203. Data memory area 201 has address 00H
To 7FH, the liquid crystal drive memory area 202 includes memory areas from address 80H to DFH. Further, the input / output memory area 203 is a memory area from addresses E0H to FFH. Among them, for the liquid crystal drive memory area 202,
Each liquid crystal cell of the liquid crystal display device 204 connected to the outside
Corresponding to the pair 1, each liquid crystal cell of the liquid crystal display device 204 can be turned on or off by writing data in the liquid crystal drive memory area 202. Further, the correspondence relationship between the liquid crystal drive memory area 202 and the liquid crystal display device 204 can be arbitrarily set as described later, so that it is possible to support various liquid crystal display devices having various display patterns.

The liquid crystal display device 204 uses 7+ as a display element.
It has one liquid crystal cell and "0" in seven liquid crystal cells.
It is possible to display from "9" to "9". In order to turn on or off each liquid crystal cell and display a number, it is controlled whether or not a potential difference is applied to the SEG signal line and the COM signal line wired for each liquid crystal cell of the liquid crystal display device 204. The table 205 shows the relationship between the SEG signal line and the COM signal line wired in each liquid crystal cell of the liquid crystal display device 204, and the liquid crystal cells 210 to 215 are displayed in order to display “2.”. When lighting, a potential difference may be applied to each of the COM0 signal line and the SEG1 signal line, the COM1 signal line and the SEG1, 2 signal lines, the COM2 signal line and the SEG0 signal line, and the COM3 signal line and the SEG0 and 2 signal lines. It is shown that.

FIG. 3 is a block diagram showing a configuration of a conventional liquid crystal cell allocation system for allocating data in the liquid crystal drive memory area 202 of FIG. 2 to liquid crystal cells. Here, in order to facilitate understanding of later-described embodiments of the present invention, a conventional liquid crystal cell allocation method will be described, and then the corresponding embodiments of the present invention will be described.

In the circuit of FIG. 3, the address signal A80
1 to A83 are decoded address signals output from the central processing unit 102 in FIG. 1, and here, only addresses 80H to 83H are decoded. The AND circuits 301 to 304 obtain an AND logic between the decoded address signal and the NWM signal which is a write signal to each memory, and latch it to the latch circuits 305 to 305.
It is input to the clock terminal 308. The decoded address signal passes through the switch 320 and the AND circuit 30.
1 to 304, the decoded address signals A80 to A83 are appropriately selected by the switch 320 and input to the AND circuits 301 to 304.
Further, with respect to the display data stored in the latch circuits 305 to 308, the data signals D0 to D3 are the switches 321.
Are appropriately selected by the input signal and are input to and stored in the latch circuits 305 to 308. The switches 320 and 321 are fixed once they are switched, and cannot be arbitrarily changed.

The latch circuits 305 to 308 are C respectively.
Corresponding to the OM0 signal line to the COM3 signal line, the display data of the liquid crystal cell is stored as described above. The data stored in these latch circuits 305 to 308 is based on the timing signals LC0 to LC3, and the AND circuits 309 to 309.
After time-division by 312, after passing through the OR circuit 313, the exclusive OR circuit 314 takes the liquid crystal driving frame signal LCF and the exclusive OR logic, and inputs it to the select terminal of the analog selector circuit 315. The liquid crystal drive power supply voltages VA and VB are input to the analog selector circuit 315, and the analog selector circuit 315 selects one of the liquid crystal drive power supply voltages VA and VB based on the output of the exclusive OR circuit 314 and outputs it as a SEG signal. To do.

FIG. 4 is a timing chart showing the state change of the circuit of FIG. 3 when the central processing unit 102 of FIG. 1 writes to the liquid crystal drive memory area 202 of FIG. First, the address signal from the central processing unit 102 in FIG. 1 indicates A9H, and there is no change in the circuit in FIG. 3 under this address signal. After that, when the address signal indicates 81H, the decoded address signal A81 becomes high level, and the AND circuit 302 of FIG.
304 opens, and the NWM signal changes to the latch circuit 306 of FIG.
It is input to the clock terminal of 308. At this time, the data output from the central processing unit 102 is "5", the data signals D0 and D2 are at high level, and the data signals D1 and D3 are at low level. Latch circuit 3
Since high-level data signals are input to both 06 and 308, high-level data is stored.

Next, when the address signal indicates 80H, the decoded address signal A80 indicates a high level, and instead, the decoded address A81 indicates a low level. This opens only the AND circuit 301 in FIG.
When the NWM signal is input, it is input to the clock terminal of the latch circuit 305. At this time, the data output from the central processing unit 102 is "8", and the data signal D3
Only high levels, others low levels. Therefore, the latch circuit 305 to which the data signal D3 is input
Stores high levels of data.

FIG. 5 is a timing chart showing a state until the liquid crystal driving SEG signal is generated based on the data stored in the latch circuits 305 to 308 of FIG. Here, a timing chart in the case where high-level data is stored in the latch circuits 306 and 308 and low-level data is stored in the latch circuits 305 and 307 of FIG. 3 is shown.

The time division signals LC0 to LC3 are output every half cycle of the liquid crystal driving frame signal LCF, and the data stored in the latch circuits 305 to 308 in FIG. 3 are time division according to the time division signals LC0 to LC3. OR circuit 313
Is output to the exclusive OR circuit 314 via the. The frame signal LCF is further input to the exclusive OR circuit 314, the exclusive OR logic of both signals is obtained, and the result is input to the select terminal of the selector circuit 315. The selector circuit 315 selects the liquid crystal driving power supply voltage VA or VB based on the signal input to the select terminal, and always generates and outputs the SEG signal synchronized with the frame signal LCF.

FIG. 6 is a timing chart showing the waveforms of the COM0 signal to the COM3 signal, and the COM0 signal to the COM3 signal having the waveforms shown in the figure are always output.

SEG signal lines and COM signal lines are wired in a matrix in each liquid crystal cell of the liquid crystal display device 204. The SEG signal as shown in FIG. The line has a waveform of COM as shown in Figure 6.
By supplying the 0 signal to the COM3 signal, each liquid crystal cell is turned on and off. From the timing charts of FIGS. 5 and 6, it can be seen that there is a liquid crystal cell to which the maximum voltage is applied once every four cycles. This liquid crystal cell is turned on only when a voltage is applied, but since the response speed of the liquid crystal cell is extremely slow, after that, even if the potential difference disappears, the liquid crystal cell does not turn off immediately but remains on for a while. Therefore, even if a voltage is applied to each liquid crystal cell once every four cycles, each liquid crystal cell looks as if it is continuously lit. Allocation of the conventional liquid crystal cells is performed as described above, and the outline thereof is understood. Next, the allocation system of the liquid crystal cells of the present invention will be described.

FIG. 7 is a block diagram showing the structure of a liquid crystal driving device to which the liquid crystal cell allocation system of the present invention is applied. From the central processing unit 102 to the liquid crystal drive circuits 702 to 70
An address signal, a data signal, other control signals, etc. are supplied to 9. This liquid crystal drive circuit 702-70
9 are all composed of the same circuit, each of which is 1
Built-in 6 SEG signal lines and 8 COM signal lines,
In total, 128 SEG signal lines can be used. The liquid crystal display device 710 includes a liquid crystal drive circuit 702.
.About.709 and the COM signal line from the liquid crystal drive circuit 706, a maximum of 12
It is set so as to be able to drive 8 × 8 liquid crystal cells.

Further, each of the liquid crystal drive circuits 702 to 709 has four input terminals connected to V _DD or V _SS . The state of this input terminal and the central processing unit 10
The upper 4 bits of the allocation address signal output from No. 2 are compared, and the liquid crystal drive circuit 702 uses only the address signal.
~ 709 is selected.

FIG. 8 shows each of the liquid crystal drive circuits 702 to 70 shown in FIG.
9 is a block diagram showing a configuration of No. 9. SEG drive circuit 8
03 to 818 are provided corresponding to each SEG signal line, and drive one SEG signal line, respectively.
When only one of these is selected, the comparison circuit 802 sets the address signals CA8 to CA1 set to the outside.
1 is compared with the allocation addresses SA8 to SA11, and the decoder circuit 801 is enabled only when both match. The address signals SA4 to A7 are decoded by the decoder circuit 801, and the SEG drive circuits 803 to
Any one of 818 is selected.

FIG. 9 shows each SEG drive circuit 803-8 of FIG.
18 is a block diagram showing the configuration of 18. When the SEG drive circuit of FIG. 9 is selected by the decoder circuit 801 of FIG. 8, an enable signal is input to the enable terminal EN of the decoder circuit 901 and the decoder circuit 90
1 is enabled. Accordingly, the decoder circuit 901
Decodes the input address signals SA1 to SA3, and the decoded signals are input to the enable terminals AEN0 to AEN7 of the latch circuit 902, respectively.
The latch circuit 902 includes a latch circuit for the COM0 signal to the COM7 signal, and this data output is input to the selector circuit 903. Selector circuit 90
3 receives the input latched data as a time division signal LC0
~ Time division based on LC7. The data output from the selector circuit 903 is the exclusive OR circuit 904.
, The exclusive OR logic is taken with the frame signal LCF, and the result is the analog selector circuit 90.
5 is input to the select terminal. The analog selector circuit 905 selects the liquid crystal drive power supply voltage VA or VB based on the signal input to the select terminal and outputs the SEG signal.

FIG. 10 is a block diagram showing the configurations of the liquid crystal cell allocating circuit and the synchronizing circuit in the latch circuit of FIG. The allocation circuits 1001 to 1008 are allocation circuits corresponding to the COM0 signal to the COM7 signal, respectively, and the output of the decoder circuit 901 in FIG. 9 is the allocation latch circuits 1001 to 1001.
It becomes the enable signal of 1008. Further, the data signals ED0 to ED7 from the central processing unit 102 of FIG. 7 are input to the allocation circuits 1001 to 1008.

FIG. 11 shows the allocation circuits 1001-10 of FIG.
It is the block diagram which showed the circuit structure of 08. The enable signal EN is a signal finally selected as a result of being decoded in FIGS . 7 to 10 .
Write signal AWM output from central processing unit 102
The AND logic of and is taken by the AND circuit 1101 and input to the selector circuit 1102. Selector circuit 1102
Selects whether to output the input signal to the clock terminal of the latch circuit 1103 or the clock terminal of the latch circuit 1104 based on the state of the address signal SA0. The latch circuit 1103 has a 3-bit length, and the latch circuit 11
Reference numeral 04 denotes an 8-bit length latch circuit, which are allocation data signals SD0 to SD0 output from the central processing unit 102.
SD7 can be captured. Therefore, the allocation addresses SA0 to SA11 output from the central processing unit 102
The latch circuit 1103 or the latch circuit 1104 is selected by, and the allocation data is set in the latch circuit 1103 or the latch circuit 1104 by the allocation data SD0 to SD7 and the data write signal AWM.

Further, liquid crystal driving address signals EA0-E
A7 is input to the comparator circuit 1106, and the liquid crystal driving data signals ED0 to ED7 are input to the selector circuit 1105. Comparator circuit 110
6 compares the liquid crystal driving address signals EA0 to EA7 with the allocation data previously stored in the latch circuit 1104. The selector circuit 1105 determines which data signal line of the liquid crystal driving data signals ED0 to ED7 is selected based on the allocation data previously stored in the latch circuit 1103.

The selector circuit 1107 outputs the output of the selector circuit 1105 to the data terminal of the latch circuit 1109 when the select terminal input is at the low level. The data stored in the latch circuit 1109 becomes the liquid crystal drive data corresponding to each liquid crystal cell. Latch circuit 1108
Outputs the output of the comparator 1106 to the clock terminal of the latch circuit 1109 when the select terminal input is at a low level, and the latch circuit 1109 inputs the output to the data terminal when the clock signal is input to the clock terminal. The output from the selector circuit 1105 is latched and output as liquid crystal drive data. Further, when the FA signal is at a high level, the latch circuits 1105, 110
6, the latch of the latch circuit 1109 can be controlled, and in this case, the allocation is fixed.

FIG. 12 is a block diagram showing the configuration of a circuit for generating the COM signal and the liquid crystal drive power supply voltages VA and VB. In the figure, liquid crystal driving power supply terminals V0 to V
5 is an example in the case of driving the liquid crystal with a ⅕ bias, and the voltage of 5 steps is input. The analog selector circuits 1201 to 1204 are switched by the frame signal NLCF, and
The drive power supply voltages VA and VB output from 02 become liquid crystal drive power supplies for the SEG drive circuit. The exclusive OR circuits 1207 and 1208 are time-division timing signals L
The exclusive OR logic of C0, LC7 and the frame signal NLCF is taken, and the result is output to the select terminals of the analog selector circuits 1205, 1206. The analog selector circuits 1205 and 1206 receive the outputs of the analog selector circuits 1203 and 1204, respectively, switch the input signals based on the select signals from the exclusive OR circuits 1207 and 1208, and output the signals.
Signal and COM7 signal are generated and output. Although not shown, the exclusive OR circuit and the analog selector circuit are respectively provided corresponding to the time division timing signals LC1 to LC6 to generate the COM1 signal to the COM6 signal, and the COM1 signal to the COM6 signal are combined with the above-mentioned signals as a whole. And outputs the COM0 signal to the COM7 signal.

FIG. 13A is a timing chart showing a case where the liquid crystal is driven by a 1/5 bias.
The waveform of the SEG signal and the waveform of the COM signal are shown.
This is achieved by supplying liquid crystal drive power to the V0 to V5 terminals of the liquid crystal drive circuit by a circuit as shown in FIG. In addition, FIG.
6 is a timing chart showing a case where the liquid crystal is driven by four biases, showing the waveform of the SEG signal and the waveform of the COM signal. This is from V0 to V of the liquid crystal drive circuit
For 5 terminals, the circuit as shown in FIG.
It is achieved by supplying liquid crystal driving power. In this way, by controlling the liquid crystal driving power supply supplied from the outside by resistance division or the like, it is possible to arbitrarily set from 1/1 bias to a maximum of 1/5 bias.

Prior to explaining the input circuit of the input / output memory area 202 of the present invention, a conventional input circuit will be described. FIG. 15 is a block diagram showing the configuration of a conventional input circuit in the input / output memory area 202 of FIG. In the figure, input terminals K00, K01, K02 and K03 are respectively input terminals of the semiconductor device, and a level signal is supplied from the outside of the semiconductor device. Input buffer 1510
˜1513 are for supplying signals from the input terminals K00 to K03 as stable level signals into the semiconductor device. Further, the latch circuits 1514 to 1517
Is input buffer 1 in synchronization with timing signal SYN.
The level signals output from 510 to 1513 are captured. In the input / output memory area 203 of FIG. 2, the AE0 signal indicating that the address E0H has been selected,
The NAND logic with the NRM signal indicating that the central processing unit 102 has read from this memory is obtained by the NAND circuit 1522, and the timing signal for opening the tri-state buffers 1518 to 1521 is generated. The level signals taken in by the latch circuits 1514 to 1517 are tristate buffers 1518 to 1521.
Is opened, it is placed on the data bus signal lines ED0 to ED3, and the central processing unit 102 of FIG.
It is possible to process the signal input to the port 03.

However, it is conceivable that stable high level signals and low level signals are not supplied to the input terminals K00 to K03, but only high level signals are supplied or an undefined state occurs. For example, a high-level signal may be supplied to an input terminal only when an external push switch or the like is attached and the switch is pressed, and nothing is connected to this input terminal when the switch is released.
When nothing is connected to this input terminal, the data to be taken in is indefinite, and it becomes impossible to detect the state where the switch is released. Therefore, as shown in the drawing, pull-down resistors 1506 to 1509 are provided in the semiconductor device, and the low level is maintained when nothing is connected to the input terminals K00 to K03, and the input terminals K00 to K03 are held.
When a high level signal is applied to the input terminals, the high level signal is applied as it is to the input terminals K00 to K03.

In the input circuit of FIG. 15, the input terminal K
It is considered that the switches 1523 to 1526 built in the semiconductor device can determine whether to connect the pull-down resistors 1506 to 1509 according to the peripheral circuits connected to 00 to K03. Settings can be made according to the usage in the device. However, when a semiconductor device having the switches 1523 to 1526 set therein is manufactured, the setting of the switch cannot be changed any more. Therefore, when it is desired to change the setting of the switch, it is necessary to remanufacture the semiconductor device.

FIG. 16 is a timing chart showing the operation of the input circuit of FIG. Although not shown in the input circuit of FIG. 15, the SYSTEM signal indicates the basic clock of the semiconductor device, and the circuit operation in the semiconductor device is performed based on this clock. K00, K01, K in the figure
02 and K03 respectively indicate the states of the input terminals of the semiconductor device, and assume that a push switch is connected to the outside. When each switch is pressed, a high level signal is supplied to each input terminal, but nothing is supplied to the input terminal when the switch is released. Here, the switches of the two input terminals K00 and K02 are always separated, and the two of the input terminals K01 and K03 are
The terminal indicates that the push switches are simultaneously pressed only at a fixed timing.

Pulltown resistors 1506-150 of FIG.
Assuming that 9 is connected, the synchronization signal SYN
In synchronization with, the high level signal is supplied when the push switch connected to the outside of the input terminals K00 to K03 is pressed, and the low level signal is supplied when the push switch is separated. As a result, the central processing unit 102 of FIG.
When the reading is executed for the address 0H, that is, the reading timing signal NRM and the address selection signal AE0
When they match, the signal line of the data buses ED0 to ED3 is represented by a hexadecimal number, that is, the signal of AH is carried.

FIG. 17 is a block diagram showing the configuration of an input circuit according to an embodiment of the present invention. In this embodiment, the problem of the conventional input circuit of FIG. 15 is solved.
In this embodiment, whether or not the pull-down resistor is connected is determined by an electrical switch, and this switch is always switchable. In addition, here, the input terminal K
00, the signal output to the terminal IN is supplied to the latch circuit 1514 in FIG.
1, K02 and K03 are also configured by similar circuits.

The analog switch 1702 is connected in series with the pull-down resistor 1703, and the pull-down resistor 17
03 is connected to the input terminal K00, the latch circuit 1
Determined by the output of 704. The switch data setting address signals SA0 to SA12 are decoded by the address decoder circuit 1706, and the address is 10
At address 00H, the data setting write signal AWM becomes a high level signal. Then, the data setting data signal SD0 at that time is stored in the latch circuit 1704.
When the set data is a low level signal, the analog switch 1702 is turned on and the pull-down resistor 1703 becomes effective. When the set data is a high level signal, the analog switch 1702 is turned off and the pull-down resistor 1703 is disabled. Therefore, the switch that has been switched by the conventional fixed type switch can be arbitrarily switched by the data stored in the latch circuit 1704.

FIG. 18 is a timing chart showing the operation of the input circuit of FIG. The SYSTEM signal indicates the basic clock of the semiconductor device, and the circuit operation in the semiconductor device is performed based on this clock. Here, the input terminal K
00 is always in an open state, and the level is indefinite. Data setting address signals SA0 to S
When A12 indicates the address 1000H in hexadecimal and the write signal AWM of the data setting latch circuit 1704 becomes a high level signal, the low level signal of the data setting signal SD0 at that time is stored in the latch circuit 1704 of FIG. It Therefore, the analog switch 1702 of FIG. 17 is turned on, and the pull-down resistor 1703 of FIG. 17 becomes effective. Therefore, the low level signal can be input to the signal line IN even after the input of the input terminal K00 is open, even after the switch setting is performed. With respect to the input terminals K01 to K03, addition of pull-down resistors can be arbitrarily set by the latch circuit with the same circuit configuration.

Although an example of the liquid crystal driving device has been described in the above embodiments, the present invention is similarly applied to a semiconductor device including a circuit which requires data allocation. Further, the present invention is also directed to an electronic device including the semiconductor device or the liquid crystal driving device described above.

[0043]

According to the semiconductor device of one aspect of the present invention (Claim 1), the control address and the pre-stored allocation address are compared with each other, and when they coincide with each other, an output signal is transmitted to output the control data. Since the bit information is selected based on the pre-stored allocation data, and the selected control data is stored based on the output signal,
Bit information of control data can be arbitrarily selected and stored based on the allocation data, and various devices can be emulated. According to the semiconductor device (Claim 2) of another aspect of the present invention, the opening / closing of the analog switch is arbitrarily controlled based on the switching data signal, so that the pull-down resistor can be enabled or disabled. Can be arbitrary.

According to another aspect of the present invention, the liquid crystal drive device (claim 3) selects the bit information of the liquid crystal display data supplied from the external device based on the pre-stored allocation data, and selects the bit information. Since the generated bit information is stored based on the output signal of the address comparison device, the allocation of the liquid crystal display device can be arbitrarily changed, and the following effects are obtained. 1) Since it is not necessary to remanufacture the device according to the allocation of the liquid crystal cell, the manufacturing cost can be reduced. 2) Since the allocation of the liquid crystal cells can be set from the outside, each allocation can be realized by the software of the microcomputer when incorporated in the microcomputer system, and the allocation can be switched while the system is operating. 3) By incorporating it into an emulation system of a microcomputer that incorporates a liquid crystal driving device, it is possible to support a wide variety of microcomputer systems.

According to another aspect of the present invention, the liquid crystal driving device (claim 4) has the following effects by providing the address setting terminal for selecting the liquid crystal driving device. 1) In a system such as a central processing unit of a microcomputer system, which outputs only an address signal and a data signal, a liquid crystal driving device does not require a control circuit.
The cost can be reduced. 2) Many devices can be selected by increasing the number of address setting terminals of the liquid crystal driving device.

Further, according to the liquid crystal drive device (claim 5) according to another aspect of the present invention, it is possible to achieve many liquid crystal drive bias systems with only one device, and the following effects are obtained. . 1) It can be applied to a wide variety of liquid crystal display devices. 2) It is possible to emulate various liquid crystal driving devices that change the liquid crystal driving method such as each bias while operating the system. Further, according to the liquid crystal drive device (claim 6) according to another aspect of the present invention, the opening and closing of the analog switch is arbitrarily controlled based on the switching data signal, so that the pull-down resistor can be enabled or disabled. It can be done arbitrarily. According to another aspect of the present invention, there is provided an electronic device (claims 7, 8 and 9) which incorporates the above-mentioned semiconductor device or liquid crystal drive device, and is compatible with various electronic devices. You can

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration when a liquid crystal driving device according to an embodiment of the present invention is incorporated in a microcomputer system.

FIG. 2 is a diagram showing a relationship between a memory map for controlling each peripheral device of the embodiment of FIG. 1 and a liquid crystal display device.

FIG. 3 is a circuit diagram of a conventional liquid crystal cell allocation method for allocating data in the liquid crystal drive memory area of FIG. 2 to liquid crystal cells.

4 is a timing chart showing a state change when the central processing unit performs writing in the circuit diagram of FIG.

5 is a timing chart showing the steps until a liquid crystal driving SEG signal is generated based on the data stored in the latch circuit in the circuit of FIG.

FIG. 6 is a timing chart showing a waveform of a COM signal.

FIG. 7 is a block diagram showing a configuration of a liquid crystal driving device to which a liquid crystal cell allocation system of the present invention is applied.

8 is a block diagram showing a configuration of the liquid crystal drive circuit of FIG.

9 is a block diagram showing a configuration of the SEG drive circuit of FIG.

10 is a block diagram showing a configuration of a liquid crystal cell allocation circuit and a synchronization circuit of FIG.

11 is a block diagram showing a configuration of an allocation circuit of the liquid crystal cell of FIG.

FIG. 12 is a circuit diagram showing a configuration of a circuit for generating a COM signal and liquid crystal drive voltages VA and VB.

FIG. 13 is a timing chart showing an operation in the case of driving a liquid crystal with a ⅕ bias in the present invention and a circuit diagram for generating the voltage thereof.

FIG. 14 is a timing chart showing an operation in the case of driving a liquid crystal with a quarter bias in the present invention and a circuit diagram for generating the voltage thereof.

15 is a circuit diagram showing a configuration of a conventional input circuit in the input / output memory area of FIG.

16 is a timing chart showing the operation of the input circuit of FIG.

FIG. 17 is a circuit diagram showing a configuration of an input circuit according to an embodiment of the present invention.

FIG. 18 is a timing chart showing the operation of the input circuit of FIG.

[Explanation of symbols]

101 program storage device 102 central processing unit 103 input / output device 104 liquid crystal drive device 105 data storage device 201 data memory area 202 liquid crystal drive memory area 203 input / output memory area 204 liquid crystal display 205 liquid crystal cell correspondence table 210-215 liquid crystal cell 301- 304 AND circuit 305 to 308 Latch circuit 309 to 312 AND circuit 313 OR circuit 314 Exclusive OR circuit 315 Analog selector circuit 702 to 709 Liquid crystal drive circuit 710 Liquid crystal display device 801 Address decoder circuit 802 Address comparison circuit 803 to 818 SEG drive circuit 901 Address Decoder circuit 902 Latch circuit 903 Selector circuit 904 Exclusive OR circuit 905 Analog selector circuits 1001 to 1008 Allocation circuit 1101 AND circuit 102 selector circuits 1103 to 1104 latch circuit 1105 Selector circuit 1106 address comparator 1107-1108 selector circuit 1109 latch circuit 1201 to 1206 analog selector circuit 1207 to 1208 exclusive OR circuit

Claims (7)

(57) [Claims] 1. An allocation address storage device for supplying and storing an allocation address, an allocation data storage device for supplying and storing allocation data, and a control address supplied and stored in the allocation address storage device. The assigned address is supplied, and an address comparison device that sends an output signal when both addresses are compared and coincides with each other, and control data is supplied, and bit information of the control data is stored in the assigned data storage device. A semiconductor device comprising: a data selection device that selects based on allocation data; and a selection data storage device that stores bit information of control data selected by the data selection device based on an output signal of the address comparison device. 2. An allocation address storage device for storing liquid crystal allocation addresses supplied from the outside, an allocation data storage device for storing liquid crystal allocation data supplied from the outside, and a liquid crystal display address supplied from the outside. An address comparison device that outputs an output signal when the allocated addresses stored in the allocated address storage device are compared and coincides with each other, and bit information of liquid crystal display data supplied from the outside,
A data selection device that selects based on the allocation data stored in the allocation data storage device, and bit information of the liquid crystal display data selected by the data selection device is stored based on the output signal of the address comparison device. And a liquid crystal display data storage device for outputting as a liquid crystal display device. 3. A plurality of liquid crystal drive circuits provided for driving the liquid crystal display device, each liquid crystal drive circuit being provided with liquid crystal cell allocation corresponding to a signal line of a liquid crystal segment of the liquid crystal display device. The liquid crystal cell allocating circuit has a circuit, and the liquid crystal cell allocating circuit supplies an externally supplied liquid crystal allocation address, an allocation address storage device, an externally supplied liquid crystal allocation data storage device, and an externally supplied liquid crystal cell allocation data. The liquid crystal display address and the assigned address stored in the assigned address storage device are compared, and an address comparison device that outputs an output signal when they match each other, and bit information of the liquid crystal display data supplied from the outside,
A data selection device that selects based on the allocation data stored in the allocation data storage device, and bit information of the liquid crystal display data selected by the data selection device is stored based on the output signal of the address comparison device. And a liquid crystal display data storage device for outputting as a liquid crystal display device. 4. Each of the liquid crystal drive circuits compares an address setting terminal to which an address is set, an address supplied from the outside, and an address set to the address setting terminal, and responds to the comparison result. 4. The liquid crystal drive device according to claim 3, further comprising: a comparison device that outputs the output, and is selected as a drive target according to the output of the comparison device. 5. A power supply device for outputting a plurality of different voltages, and a plurality of different voltages from the power supply device are selected based on bit information stored in the liquid crystal display data storage device to select a liquid crystal segment. 1st output to segment signal line
And a second selection device for selecting a plurality of different voltages from the power supply device and outputting the selected voltages to a plurality of common signal lines of a liquid crystal segment of the liquid crystal display device. 3. The liquid crystal drive device according to 3 or 4. 6. An electronic device including the semiconductor device according to claim 1. 7. An electronic device including the liquid crystal drive device according to claim 2.