JP3365701B2 - Semiconductor device having charge recycling means - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having charge recycling means for low power consumption operation.

[0002]

2. Description of the Related Art It has been conventionally demanded that a semiconductor device be operated with low power consumption in order to be driven by a battery. In order to perform this low power consumption operation, there has been proposed a method of reusing electric charges stored in a capacitor during operation as much as possible without wasteful discharge. Below, 19
1993 VLSI Circuit Technology Symposium Digest, pp. 41-42 (1993 SYMPOSIUM ON VLSI CIR
The method of reusing charges proposed in CUITS DIGEST OF TECHNICAL PAPERS PP.41-42) will be briefly described with reference to FIGS. FIG. 24 is a circuit diagram showing the concept of the charge recycling method, and FIG. 25 is a diagram showing the state of charges during the operation of FIG. FIG. 26 shows a method of reusing this charge in a DRAM.
Circuit diagram applied during self refresh operation of
FIG. 27 is an operation timing chart in the self-refresh operation of the DRAM of FIG. 26.

First, an outline of a conventional charge recycling method will be described with reference to the circuit diagram of FIG. 24 and the charge state diagram of FIG. In FIG. 24, C1 and C2 are capacitors and S
C1 and SC2 are switches for charging the capacitors C1 and C2, respectively. SD1 and SD2 are switches for discharging charges from the capacitors C1 and C2, respectively. ST is a switch for electrically connecting the capacitors C1 and C2.

The first electrode of the capacitor C1 is connected to the ground voltage, and the second electrode of the capacitor C1 is connected to the power supply voltage via the switch SC1 and to the ground voltage via the switch SD1. Similarly, the first electrode of the capacitor C2 is connected to the ground voltage, the second electrode is connected to the power supply voltage via the switch SC2, and is connected to the ground voltage via the switch SD2. Further, the second electrode of the capacitor C1 and the second electrode of the capacitor C2 are connected via the switch ST. In FIG. 24, arrows indicate the moving directions of the charges at the respective times t1 to t5. Figure 25
Are the capacities C1 and C at the respective times t1 to t5.
The charge amount of 2 is schematically shown.

First, when the switch SC1 is turned on at time t1, the capacitor C1 is charged to the power supply voltage. Then time t
The switch ST is turned on at 2 to transfer the charge of the capacitor C1 to the capacitor C2, thereby reusing the charge. here,
If the capacitors C1 and C2 have the same capacitance value, the charges of the capacitors C1 and C2 are equal. Then at time t3, switch S
D1 and SC2 are turned on to discharge the capacitance C1 and charge the capacitance C2 to the power supply voltage. Next, at time t4, the switch ST is turned on to transfer the electric charge of the capacitor C2 to the capacitor C1 to similarly reuse the electric charge. Next, at time t5, the switches SD2 and SC1 are turned on to discharge the capacitor C2 and charge the capacitor C1 again to the power supply voltage. This returns to the same state as at time t1.

As described above, when the capacitors C1 and C2 are respectively charged and discharged, the capacitors C1 side and the capacitor C2 side are alternately operated to reuse the charges of each other. If the capacitance C1 and the capacitance C2 have the same capacitance value, the charge reuse rate is 50%.

Next, the above method for reusing charges will be described as D
A specific example applied to the self-refresh operation of the RAM will be described with reference to the circuit diagram of FIG. 26 and the operation timing chart of FIG.

In FIG. 26, MA1 and MA2 are memory cell arrays, D1, / D1, D2 and / D2 are data lines, W1 and W2 are word lines, SA1 and SA2 are sense amplifiers, CS is a memory cell capacity, and CD. Is the data line capacity,
PD1 and PD2 are precharge and equalize circuits for data lines, PP1 and PP2 are high level nodes of the sense amplifier, PN1 and PN2 are low level nodes of the sense amplifier, and CC is capacitance of each level node of the sense amplifier.

PS1 and PS2 are precharge and equalize circuits for level nodes, VDH is a high level voltage of the sense amplifier, VDL is a low level voltage of the sense amplifier, and DM1 and DM2 are high level nodes PP1 and PP2 of the sense amplifiers SA1 and SA2. And high level voltage VDH
, And a switch interposed between the low level nodes PN1 and PN2 and the low level voltage VDL, ST is between the sense amplifier SA1 and the sense amplifier SA2 and the high level nodes PP1 and PP2, and the low level node PP
Switch interposed between 1 and PP2, φT, / φT, φ
S1, / φS1, φS2, / φS2 are control signals for each switch, and / φC1, / φC2 are control signals for the precharge and equalize circuits PD1, PD2, PS1, PS2, respectively. The leading "/" of each signal name indicates that it is a negative logic.

The memory cell array MA1 is constructed as follows. The source of the memory cell transistor is connected to the memory cell capacitance CS, the gate is connected to the word line W1, and the drain is connected to the data line D1. A data line precharge / equalize circuit PD1 and a sense amplifier SA1 are connected between the pair of data lines D1, / D1. Further, the precharge and equalize circuit PS1 of the sense amplifier SA1 and the level node is connected between the high level and low level nodes PP1 and PN1.
And are connected. / ΦC1 is input as a control signal for the data line precharge / equalize circuit PD1 and the level node precharge / equalize circuit. In addition, high level and low level nodes PP
1, PN1 is a control signal φS1 or / φS1 at the gate
Is connected to the high level and low level voltages VDH and VDL, respectively.

Similarly, in the memory cell array MA2, the source of the memory cell transistor is connected to the memory cell capacitor CS, the gate is connected to the word line W2, and the drain is connected to the data line D2. A pair of data lines D2, /
A data line precharge / equalize circuit PD2 and a sense amplifier SA2 are connected between D2. A sense amplifier SA2 and a level node precharge / equalize circuit PS2 are connected between the high level and low level nodes PP2 and PN2. / ΦC2 is input as a control signal for the data line precharge / equalize circuit PD2 and the level node precharge / equalize circuit PS2. Node PP
2, PN2 has a control signal φS2, /
Level voltage V is applied through the transistor to which φS2 is applied.
It is connected to DH and VDL. The high-level and low-level nodes PP2 and PN2 are connected to the high-level and low-level voltages VDH and VDL, respectively, through transistors whose gates are supplied with the control signal φS2 or / φS2.

As shown in FIG. 27, when the control signal / RAS for the self-refresh operation becomes the logic voltage "L", the control signal / φC1 also becomes the logic voltage "L". by this,
The precharge of the data lines D1, / D1 and the nodes PP1, PN1 and the operation of the equalize circuits PD1, PS1 are stopped. Next, the word line W1 becomes the logical voltage "H" and the data is read out to the data line D1, and then the control signal φS1 becomes the logical voltage "H" and / φS1 becomes the logical voltage "L". Works. by this,
The high level node PP1 becomes the high level voltage VDH, the low level node PN1 becomes the low level voltage VDL,
At time t1, the refresh operation of the memory cell array MA1 is completed. At this time, the word line W1 becomes the logic voltage "L", the control signal φS1 becomes the logic voltage "L", / φS1 becomes the logic voltage "H", and the nodes PP1 and PN1 are brought into the floating state.

Next, when the control signal / RAS once becomes the logic voltage "H" and then becomes the logic voltage "L", the logic voltage of the control signal / φC2 becomes "L", and the data lines D2, /
The operations of D2 and the precharge of the nodes PP2 and PN2 and the equalizing circuits PD2 and PS2 are stopped. Next, the word line W2 becomes the logic voltage "H", and the data line D
The data is read to 2. Next, from time t2 to period tT
While the control signal φT is at the logical voltage “H”, the control signal / φT
Becomes a logical voltage "L", and the charges of the nodes PP1 and PN1 move to the nodes PP2 and PN2. That is, the sense amplifier SA2 operates a little. Next, the control signal φS2 becomes the logic voltage “H” and / φS2 becomes the logic voltage “L”, and the sense amplifier SA2 operates completely. At this time, the high level node PP2 becomes the high level voltage VDH and the low level node PN2 becomes the low level voltage VDL, and the refresh operation of the memory cell array MA2 is completed at time t3.
At this time, the word line W2 becomes the logic voltage "L", the control signal φS2 becomes the logic voltage "L", and / φS2 becomes the logic voltage "H".
And the nodes PP2 and PN2 are in a floating state. The control signal / φC1 becomes the logical voltage "H", and precharge and equalization of the data lines D1, / D1 and the nodes PP1, PN1 are started.

Similarly, after the control signal / RAS once becomes the logic voltage "H" and then becomes the logic voltage "L",
The control signal / φC1 becomes the logic voltage "L", and the data line D
1, / D1, precharge and equalization of nodes PP1 and PN1 are stopped. Next, the word line W1 becomes the logic voltage "H", and the data is read out to the data line D1. Next, in the period tT from the time t4, the control signal φT becomes the logical voltage “H”, the control signal / φT becomes the logical voltage “L”, and the charges of the nodes PP2 and PN2 move to the nodes PP1 and PN1. That is, the sense amplifier SA1 operates a little. Next, the control signal φS1 becomes the logical voltage “H” and / φS1 becomes the logical voltage “L”, and the sense amplifier SA1 operates completely. This causes the node PP1 to have the level voltage VDH.
Then, the node PN1 becomes the level voltage VDL, and the time t5
Then, the refresh operation of the memory cell array MA1 is completed. Next, the word line W1 becomes the logical voltage "L", the control signal φS1 becomes the logical voltage "L", and / φS1 becomes the logical voltage "H".
Becomes As a result, the nodes PP1 and PN1 are brought into a floating state. The control signal / φC2 becomes the logic voltage "H", the data lines D2, / D2, the node PP2,
Precharge and equalization of PN2 are started.
Thereafter, the refresh operation is performed the required number of times in the same manner. In this way, the charge is reused by moving the charge between the memory cell arrays.

[0015]

Since the conventional charge reusing method for a semiconductor device as described above is performed between a plurality of memory cell arrays, it is effective when performing a sequential refresh operation such as a self refresh operation. However, it cannot be applied to the refresh operation of the same memory cell array like the normal refresh operation. In addition, the charges in the final refresh operation cannot be reused after the required number of self-refresh operations are completed. Further, in the above charge recycling method, the charge recycling rate is 50% at maximum, and 50% or more of the charges are discharged without being recycled.

Therefore, an object of the present invention is to provide a semiconductor device device having a charge reusing means which can increase the charge reusing rate to 50% or more and can be applied to the refresh operation of the same memory cell array. is there.

[0017]

In order to achieve the above-mentioned object, a semiconductor device having a charge reusing means of the present invention has a first configuration, in which a charge / discharge capacity connected to a wiring is
Each of the first to n-th intermittent switches is connected to the wiring.
A plurality of first to n-th plurality of charge recovery capacitors provided
From the charge and discharge capacity charged with electric charge
When recovering charges to multiple charge recovery capacitors,
Then, the first intermittent switch is turned on to discharge the charge.
By connecting only the capacitance and the first charge recovery capacitance,
After the charge is recovered in the first charge recovery capacitor, the first charge recovery capacitor
Turn off the on / off switch, and then connect to the 2nd to nth
The switches are sequentially turned on and off, and the second to the second
n by collecting the charge in the charge collecting capacitor,
A plurality of capacitors for charge recovery are used for the first charge recovery of the highest potential.
Distinguishing from the storage capacitor to the lowest potential nth charge recovery capacitor,
Next, the plurality of charged / discharged charges are discharged into the charge / discharge capacity.
When reusing charges from individual charge recovery capacitors,
To turn on and off the n-th intermittent switch, and
Connect only the charge / discharge capacity and the n-th charge recovery capacity
Then, the charge is reused from the n-th charge recovery capacitor,
The same operation is repeated in the reverse order of the descending and the charge collecting.
Finally, the charge is returned from the first charge recovery capacitor.
By utilizing the plurality of charge recovery capacitors,
The charges are reused in order from the one with the lowest potential, and then
From the charge / discharge capacity charged again,
When recovering charges to a plurality of charge recovery capacitors,
In order from the highest potential of several charge recovery capacitors
To recover the charge.

The second in the structure of the first configuration of the charge recycling means of a semiconductor device having a charge recycling means of the present invention
Is used to maximize the charge recovery rate.
The capacitance value of the charge recovery capacitor is set.

Here, the charge recovery means that the charge charged in the charge charge / discharge capacity is transferred to the charge recovery capacity and stored therein, and the charge reuse is stored in the charge recovery capacity. This means returning the stored charge to the charge / discharge capacity. The semiconductor device having the charge recycling means of the present invention has a charge recycling rate of 50% due to the above configuration.
The above can be done. It can also be applied to the refresh operation of the same memory cell array. After the self-refresh operation is completed, the charge can be saved and reused for the next self-refresh.

The third structure of the semiconductor device having the charge recycling means of the present invention is that the first to n-th intermittent switches for wiring are provided.
First to n-th plurality provided through the respective
Of the first to n-th plurality of charge / discharge capacities
The charge and discharge capacities are respectively the first to nth charge charges.
Can be connected to the power supply for charging the electric charge via the switch for
Configured to operate through the first to nth charge discharging switches.
Configured to connect to a discharge circuit for discharging electric charge.
First, turn on the first charge charging switch.
And charges the first charge / discharge capacity with
Both turn on the n-th charge discharging switch,
After discharging the charge from the nth charge charge / discharge capacity,
A first charge charging switch and the nth charge discharging switch
Switch off and then the first and second intermittent switches.
Only the switch is turned on, and from the first charge / discharge capacity
After collecting the charge in the second charge / discharge capacity,
Turn off the 2nd on / off switch, and then turn off the 3rd to nth
The continuation switch is sequentially turned on and then turned off, and the first charge
From the charge / discharge capacity to the third to nth charge / discharge capacity
To sequentially collect the electric charge, and then the second charge charging switch.
Switch on to charge the second charge / discharge capacity.
Power on and turn on the first charge discharge switch.
Then, the charge was discharged from the first charge charge / discharge capacity.
Then, the second charge charging switch and the first electric charge
Turn off the load / discharge switch, and then charge / discharge the first charge.
From the electric capacity to the second to nth charge / discharge capacities sequentially.
In the same procedure as for collecting the load, the second charge / discharge
From the capacitance to the third to nth charge / discharge capacitances and
The charge is sequentially collected into the first charge / discharge capacity, and further
After that, the third to nth charge / discharge capacities are sequentially charged.
Then, each time, the charge is collected in the remaining charge / discharge capacity.

In a fourth structure of the semiconductor device having the charge reusing means of the present invention, the wiring is provided through an intermittent switch.
At least one charge / discharge capacity that is
For collecting multiple charges provided via an intermittent switch
And one of the plurality of charge recovery capacitors.
Switching of parts or all connected in parallel or in series
It is configured through a switch to enable the charge
Charge is transferred from the charge / discharge capacity to the plurality of charge recovery capacities.
When collecting, the charge recovery capacitors are connected in parallel.
The charge charging / discharging is performed from the plurality of charge recovery capacitors.
When reusing the charge in the capacitor, the charge recovery
Capacitors are connected in series.

[0022]

[0023]

[0024]

[0025]

[0026]

[0027]

[0028]

[0029]

[0030]

[0031]

[0032]

[0033]

[0034]

[0035]

[0036]

[0037]

[0038]

[0039]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the drawings. First, the first embodiment will be described with reference to the circuit diagram of FIG. 1, schematic diagrams showing the state of charge (charged state of each capacitance) of FIGS. 2 to 5, and the timing diagram of FIG. Note that FIG. 7 shows the relationship between the capacity ratio of the charge / discharge capacity and the charge recovery capacity and the charge recovery rate in this embodiment.

In FIG. 1, CR1 is a charge / discharge capacity,
CS1 to CS4 are charge recovery capacitors, SC1 is a charge charging switch, SD1 is a charge discharging switch, ST1 to ST
4 is a switch for connecting / disconnecting the charge recovery capacitor, N10
-N15 have shown each node. The switch SC1 is connected between the power supply voltage and the node N10, and the switch SD1
1 is connected between the ground voltage and the node N10, and the charge / discharge capacity CR1 is connected between the node N10 and the ground voltage. The switches ST1 to ST4 are connected between the node N10 and the nodes N12 to N15, respectively, and the charge recovery capacitors CS1 to CS4 are respectively connected to the node N.
It is connected between 12 to N15 and the ground voltage.

The first charge recovery will be described with reference to FIGS. 2 and 6. In FIG. 6, the charging period P1
The charge / discharge capacity CR1 is charged at the charge recovery period P2
Therefore, the charge of the charge / discharge capacity CR1 is equal to the charge recovery capacity CS1.
~ CS4, charge charge / discharge capacity C during discharge period P3
The residual charge of R1 is discharged. Hereinafter, the operation will be described sequentially in order.

At time t1, the switch SC1 is on and the other switches are off, during which the charge / discharge capacity CR1
Is charged to the power supply voltage. At the next time t2, the switch SC1 is off and the switch ST1 is on, and during this period, a part of the charge of the charge / discharge capacity CR1 is the charge recovery capacity C.
Collected in S1. At the next time t3, the switch ST1 is off, the switch ST2 is on, and the charge / discharge capacity C
A part of the residual charge of R1 is recovered in the charge recovery capacitor CS2. Next, at time t4, the switch ST2 is off and the switch ST3 is on, and a part of the residual charge of the charge / discharge capacity CR1 is recovered in the charge recovery capacity CS3. At the next time t5, the switch ST3 is off and the switch ST4 is on, and a part of the residual charge of the charge / discharge capacity CR1 is recovered in the charge recovery capacity CS4. And next time t6
Thus, while the switch ST4 is off and the switch SD1 is on, the residual charge in the charge / discharge capacity CR1 is discharged.

Next, the first charge recycle will be described with reference to FIGS. In FIG. 6, after the residual charge of the charge / discharge capacity CR1 is discharged in the discharge period P3 as described above, the charge stored in the charge recovery capacitors CS1 to CS4 is discharged in the charge reuse period P4. It is reused and the charge / discharge capacity CR1 is charged again in the charging period P1.

That is, at time t6, the switch SD1 is on and the other charge / discharge capacities CR are on while other switches are off.
After the electric charge of 1 is discharged, at time t7, the switch SD1
Is turned off, the switch ST4 is turned on, and the charge of the charge recovery capacitor CS4 returns to the charge charge / discharge capacitor CR1. At the next time t8, the switch ST4 is off and the switch ST3 is on, and the charge of the charge recovery capacitor CS3 is reused for the charge / discharge capacitor CR1. At the next time t9, the switch ST
3 is off and the switch ST2 is on, and the charge of the charge recovery capacitor CS2 is reused for the charge / discharge capacitor CR1. At the next time t10, the switch ST2 is off and the switch ST1 is on, and the charge of the charge recovery capacitor CS1 is reused for the charge / discharge capacitor CR1. Next time t11
Then, the switch ST1 is off, the switch SC1 is on, and the charge / discharge capacity CR1 is charged to the power supply voltage.

FIG. 4 shows the state of the second charge recovery, and the same operation as the first charge recovery is performed from time t12 to t16 in FIG. In the second charge recovery, the charge recovery capacitors CS1 to CS4 already have charges, and therefore the recovered charge amount is larger than that in the first charge recovery.

FIG. 5 shows a state of the second charge reuse, and the same operation as the first charge reuse is performed from time t16 to tt21 in FIG. In the second charge reuse, the charge recovery capacitors CS1 to CS4 have a larger charge amount than in the first charge reuse, and thus the charge charge / discharge capacitance CR1 has a larger charge amount to be reused.

The above-described operation is repeated to collect and reuse the charges. When the operation of recovering and reusing the charges is repeated, the amount of charges recovered and reused approaches a certain value.

FIG. 7 is a diagram showing the relationship between the capacity ratio of the charge / discharge capacity CRm and the charge recovery capacity CSn and the charge recovery rate. Here, when the number of charge / discharge capacities is 1, m
= 1 and the charge / discharge capacity CRm means CR1. The charge recovery capacitors CSn are charge recovery capacitors CS1 to C.
This is equivalent to S4, and n = 4 when there are four charge recovery capacitors. When m = 1, α = CSn / CRm, and the number of charge recovery capacitors is n, the first charge recovery rate R (α, m) is R (α, m) = 1 / (α + 2) × (1-1 / (1 + α)
^2m ). In FIG. 7, n = 1, 2, 4, 8, 16, 3
In case of 2, α = CSn / CRm and charge recovery rate R (α,
The relationship of m) is shown, and it can be seen that there is an optimum value under each condition. In this embodiment, there are four charge recovery capacitors (n = 4), and when α is approximately 0.5, the first
The charge collection rate for the second time becomes maximum. That is, the value of the charge recovery capacitors CS1 to CS4 is 1 / the value of the charge / discharge capacitor CR1.
If the capacitance value is set to 2, the first charge recovery rate becomes maximum. Further, although the charge recovery rate of the first time is about 40%, the charge recovery rate becomes, for example, 70% when the operation of recovering and reusing the charge is repeated.

In the first embodiment, the charge recovery rate is, for example, 70%, which can be made higher than the conventional 50%, and thus can further contribute to the low power consumption operation. The charge recycling method described here can also be applied to the self-refresh operation of the DRAM shown in the conventional example.

Next, a second embodiment will be described with reference to the circuit diagram of FIG. 8, the schematic diagram showing the charging state of each capacitor of FIG. 9, and the timing diagram of FIG. In FIG. 8, CR1 to
CR4 is used not only as a charge / discharge capacity but also as a charge recovery capacity. SC1 is a charge charging switch, SD
Reference numeral 1 is a charge discharging switch, SR1 to SR4 are switches for connecting a charge / discharge capacity, and N80 to N84 are node names. Switch SC1 is connected between the power supply voltage and node N80, and switch SD1 is connected to the ground voltage and node N80.
And the charge / discharge capacitors CR1 to CR4 are connected between the nodes N80 to N84 and the ground voltage, respectively, and the switches SR1 to SR4 are connected between the node N80 and the nodes N81 to N84, respectively. There is.

At time t1, the switches SC1 and SR1 are on, the other switches are off, and the charge / discharge capacity CR1
Is charged to the power supply voltage. At the next time t2, the switches SR1 and SR2 are turned on and the other switches are turned off, so that the charge of the charge / discharge capacity CR1 is recovered by the charge / discharge capacity CR2. At the next time t3, the switches SR1 and SR3 are on, the other switches are off, and the charge / discharge capacity CR is
The charge of 1 is collected in the charge / discharge capacity CR3. At the next time t4, the switches SR1 and SR4 are turned on and the other switches are turned off, and the charge of the charge / discharge capacity CR1 is collected in the charge / discharge capacity CR4. At the next time t5, the switches SR1 and SD1 are on, the other switches are off,
The charge of the charge / discharge capacity CR1 is discharged. in this way,
After the charge of the charge / discharge capacity CR1 is recovered to the charge / discharge capacity CR2 to CR4 which is another charge / discharge capacity, the charge of the charge / discharge capacity CR1 is discharged.

The same operation is performed for the charge / discharge capacity CR2. At time t6, the switches SC1 and SR2 are on, the other switches are off, and the charge / discharge capacity CR2 is
Is charged to the power supply voltage. Switch S at next time t7
When R2 and SR3 are on and the other switches are off, the charge of the charge / discharge capacity CR2 is collected in the charge / discharge capacity CR3. At the next time t8, the switches SR2 and SR4 are turned on,
The other switches are off, and the charge of the charge / discharge capacity CR2 is collected in the charge / discharge capacity CR4. Next time t9
Then, the switches SR2 and SR1 are turned on and the other switches are turned off, and the charge of the charge / discharge capacity CR2 is recovered in the charge / discharge capacity CR1. At the next time t10, the switches SR2 and SD1 are turned on and the other switches are turned off, and the charge of the charge / discharge capacity CR2 is discharged. And so on
Charge / discharge capacity CR3, CR4, CR1, CR2, CR
The charges of the charge / discharge capacitors CR1 to CR4 are recovered and reused in the order of 3 and CR4.

In the second embodiment, the charge recovery rate can be set to 50% or more as in the first embodiment. Further, since the charge / discharge capacity is also used as the charge recovery capacity, there is an advantage that no special charge recovery capacity is required.

Next, a third embodiment will be described with reference to the circuit diagram of FIG.
This will be described with reference to the timing chart of FIG. CR1
To CR4 are charge / discharge capacities and are also used as charge recovery capacities, SC1 to SC4 are charge charging switches, and S
D1 to SD4 are switches for charge discharge, SR1 to SR4 are switches for connecting charge / discharge capacity, N110 to N11.
4 is a node name, and t1 to t17 are times.

Switches SC1 to SC4 are connected between the power supply voltage and nodes N111 to N114, respectively, and switches SD1 to SD4 are connected to the ground voltage and node N11, respectively.
1 to N114, the charge / discharge capacity CR1
To CR4 are connected between nodes N111 to N114 and the ground voltage, respectively, and switches SR1 to SR4 are connected between node N110 and nodes N111 to N114, respectively.

At time t1, the switches SC1 and SD4 are turned on and the other switches are turned off to charge the charge / discharge capacity CR1 to the power supply voltage and discharge the charge / discharge capacity CR4 to the ground voltage. Next, at time t2, the switch SR
1, SR2 is on and the other switches are off, and the charge of the charge / discharge capacity CR1 is collected in the charge / discharge capacity CR2.
Next, at time t3, the switches SR1 and SR3 are turned on, and the other switches are turned off, so that the charges of the charge / discharge capacity CR1 are collected in the charge / discharge capacity CR3. Next, at time t4, the switches SR1 and SR4 are turned on and the other switches are turned off, and the charge of the charge / discharge capacity CR1 is collected in the charge / discharge capacity CR4. Next, at time t5, the switches SC2 and SD1 are turned on and the other switches are turned off to charge the charge / discharge capacity CR2 to the power supply voltage and discharge the charge / discharge capacity CR1 to the ground voltage. Thus, the charge / discharge capacity C
After the charge of R1 is recovered to the charge / discharge capacity CR2 to CR4 which is another charge / discharge capacity, the charge / discharge capacity CR1
Is discharging the charge. Similarly, charge and discharge capacity C
The charges in the charge / discharge capacitors CR1 to CR4 are recovered and reused in the order of R3, CR4, CR1, CR2, CR3, and CR4.

In the third embodiment, the charge recovery rate can be 50% or more as in the first embodiment. Further, since the charge / discharge capacity is also used as the charge recovery capacity, there is an advantage that no special charge recovery capacity is required. Further, as compared with the second embodiment, different charge / discharge capacities can be charged and discharged at the same time, such as charging of the charge / discharge capacity CR1 and discharge of charge of the charge / discharge capacity CR4 at time T1. The time required to reuse charges can be shortened.

Next, a fourth embodiment will be described with reference to the circuit diagram of FIG. 13 and the schematic diagram of FIG. 14 showing the charged state of each capacitor. In the figure, CR1 to CR4 are charge / discharge capacities, CS1 to CS4 are charge recovery capacities, SC1 to SC4.
Is a charge charging switch, SD1 to SD4 are charge discharging switches, SR1 to SR4 are switches for connecting charge / discharge capacitors, ST1 to ST4 are switches for connecting charge collecting capacitors, and N130 to N138 are node names, t1 to t8 are time.

The switch SC1 is connected to the power supply voltage and the node N13.
0, the switch SD1 is connected between the ground voltage and the node N130, and the charge / discharge capacitors CR1 to CR1 are connected.
CR4 and charge recovery capacitors CS1 to CS4 are connected between the nodes N131 to N138 and the ground voltage, respectively, and switches SR1 to SR4 and ST1 to ST4 are connected between the node N130 and the nodes N131 to N138, respectively. . This circuit operates so as to be in the charged state of each capacitance as shown in FIG. 14 by operating each switch as in the above-described embodiment. This embodiment is a combination of the first embodiment and the second embodiment, and aims to collect charges more efficiently. As in the first embodiment, the charge recovery rate can be set to 50% or more, and since the charge charge / discharge capacity is also used as the charge recovery capacity, there is an advantage that charge recovery can be efficiently performed.

Next, a fifth embodiment will be described with reference to the circuit diagram of FIG. 15 and the schematic diagram of FIG. 16 showing the charged state of each capacitor. This embodiment is characterized by a method of setting a charge recovery capacitor for increasing the charge recovery rate. A case will be described in which the fourth embodiment is simplified to have one charge recovery capacitor.

C0, C1 and C2 are capacities, SC1 and SC2
Are switches for charging the capacitors C1 and C2, respectively. SD1 and SD2 are capacities C1 and C2, respectively.
It is a switch for discharging the electric charge from. ST1, S
T2 is a switch for electrically connecting the capacitors C1 and C0 and C2 and C0.

The first electrode of the capacitor C1 is connected to the ground voltage, the second electrode thereof is connected to the power supply voltage via the switch SC1, and is connected to the ground voltage via the switch SD1. Similarly, the first electrode of the capacitor C2 is connected to the ground voltage, the second electrode is connected to the power supply voltage via the switch SC2, and is connected to the ground voltage via the switch SD2. The first electrode of the capacitor C0 is connected to the ground voltage, and the second electrode of the capacitor C1 and the second electrode of the capacitor C0 are connected to the switch S.
It is connected through T1 and is connected to the second electrode of the capacitor C2 and the capacitor C2.
The second electrode of 0 is connected via the switch ST2. In FIG. 15, the arrows indicate the moving directions of the electric charges at times t1 to t9. In FIG. 16, time t1
The charge amounts of the capacitors C1, C0, and C2 at t9 to t9 are shown.

First, at time t1, the switch SC1 is turned on to charge the capacitor C1 to the full power supply voltage.
Next, at time t2, the switch ST1 is turned on, the charge of the capacitor C1 moves to the capacitor C0, and the charge is collected. Next time t3
Then, the switch SD1 is turned on, and the electric charge of the capacitor C1 is discharged. Next, at time t4, the switch ST2 is turned on, and the capacitance C0
Charges of C move to the capacitor C2 and reuse the charges. Next, at time t5, the switch SC2 is turned on, and the capacitor C2 is charged with electric charges to the full power supply voltage. Next, at time t6, the switch ST2 is turned on, the charge of the capacitor C2 is moved to the capacitor C0, and the charge is collected. Next, at time t7, the switch SD2
Is turned on, and the electric charge of the capacitor C2 is discharged. Next, at time t8, the switch ST1 is turned on, the charge of the capacitor C0 is transferred to the capacitor C1, and the charge is reused. Next, at time t9, the switch SC1
Turns on, and charges the capacitor C1 to the full power supply voltage. This returns to the same state as at time t1.

As described above, when the charges are charged and discharged in the capacitors C1 and C2, respectively, the charge recovery capacitor C0 is used.
To collect the charges of the capacitors C1 and C2,
It is reused in 2. Here, the case where the capacitance C1 side and the capacitance C2 side are alternately operated has been described, but for example, only the capacitance C1 side can be continuously operated to reuse the charges. The charge reuse rate is the capacitance C1,
It depends on the ratio of C2 and the charge recovery capacitor C0 and the number of times of charge recovery.

FIG. 17 shows the relationship between the number of times of charge reuse (recycling) and the potential after charge recycling, regarding the charge recovery rate in the charge recycling method of the present invention. Figure 15
C0 and C in the conceptual circuit diagram of the method of reusing the electric charge of the
The ratio of 1 is α = C0 / C1, and the maximum voltage of the second electrode of the capacitor C1 when the switch SC1 is turned on is VH.
Then, the voltage Vm of the second electrode of the capacitor C1 after the m-th (m is an integer) charge reuse (recycle) is: Vm = α / (1 + 2α) × (1- (α / (1+
α)) ^2m ) × VH. However, when m = 0, Vm = 0. FIG. 17 shows that α = 5, 10, 15, 20, 25, 30
At this time, the horizontal axis shows the number of recycling times m, and the vertical axis shows the value obtained by dividing the voltage Vm of the second electrode of the capacitor C1 after the m-th recycling by VH.

As can be seen from the figure, as the number of recycling times m increases, the voltage Vm / VH after the mth recycling increases. Further, as α is increased, the voltage Vm / VH after recycling is small when m is small, and the voltage Vm / VH after recycling is very large when m is large.
Grows.

Next, assuming that the average post-recycling voltage per one cycle after all the recycles is P times (P is an integer), g (α, P) = Σ (m = 0, (P-1)) Vm / P = [alpha] / P * A * A * ( ^B2P- P * B * B + P-1) * VH where A = (1+ [alpha]) / (1 + 2 [alpha]) B = [alpha] / ( 1 + α). FIG. 18 shows the ratio α of the capacities C0 and C1 and the average post-recycling voltage g (α, P) / VH per time.
Shows the relationship with. This voltage g (α, P) / VH means the charge recovery rate.

For example, when the number of recycles P = 3, α is about 1.5, when P = 10, α is about 3, and when P = 30, α is about 6
By setting to 1, the average post-recycling voltage g (α, P) / VH (charge recovery rate) per time after total recycling can be maximized. For example, when designing a device with the number of recyclings P ≧ 10, design with an appropriate value of α ≧ 3. Further, if a device having a recycling number P of about 100 is designed with α of about 10, the charge recovery rate will be about 44%.

Further, the capacitor C1 is not necessarily one capacitor, but may be composed of a plurality of charge recovery capacitors each having an independent switch as in the first embodiment. Next, a sixth embodiment will be described with reference to the circuit diagram of FIG. 19, the schematic diagram showing the charging state of each capacitor of FIG. 20, and the timing diagram of FIG.

In each figure, CR1 is the charge / discharge capacity,
CS1 to CS4 are charge recovery capacitors, SC1 is a charge charging switch, SD1 is a charge discharging switch, ST1 to ST
Reference numeral 11 is a switch for switching between parallel connection and series connection of the charge recovery capacitors and for switching between charge recovery and reuse, N10 to N19 are node names, and t1 to t5 are times.

The switch SC1 is connected to the power supply voltage and the node N10.
, The switch SD1 is connected between the ground voltage and the node N10, and the switch SR1 is connected to the node N1.
0 is connected between the node N11 and the charge / discharge capacity C
R1 is connected between the node N11 and the ground voltage, and the switches ST1 to ST4 are connected to the node N11 and the node N, respectively.
12 to N15, and is connected to the charge recovery capacitor CS1.
To CS4 are nodes N12 to N15 and node N1, respectively.
6 to N19 and connected to switches ST5 to ST8
Are respectively connected between the nodes N16 to N19 and the ground voltage, and the switches ST9 to ST11 are connected to the node N, respectively.
It is connected between 13-N15 and nodes N16-N18.

First, at time t1, the switches SC1 and SR
1, ST5 to ST8 are on, other switches are off, and the charge / discharge capacity CR1 is charged to the power supply voltage.
At the next time t2, the switch SC1 is turned off and the switch ST is turned on.
1 to ST4 are on, and the charge recovery capacitors CS1 to C in which the charges accumulated in the charge / discharge capacitor CR1 are connected in parallel
Collected in S4. At the next time t3, the switch SD1,
When ST9 to ST11 are on and ST1 to ST7 are off, the charge of the charge / discharge capacity CR1 is discharged, and the charge recovery capacitors CS1 to CS4 are connected in series. At the next time t4, the switch SD1 is off, ST1 is on, and the charge recovery capacitor CS1 is connected in series to the charge charge / discharge capacitor CR1.
The charges are recovered from CS4. At the next time t5, the switches SC1, SR1, ST5 to ST8 are on, and the other switches are off, and the same state as at time t1 is reached, and the charge / discharge capacity CR1 is charged to the power supply voltage. By repeating such an operation, the charge of the charge / discharge capacity CR1 is recovered and reused in the charge recovery capacity.

In the sixth embodiment, at the time of charge recovery, charge recovery capacitors are connected in parallel to lower the potential level so that as much charge as possible can be recovered.
At the time of charge reuse, a charge recovery capacitor is connected in series to increase the potential level so that as much charge as possible can be reused. As a result, the charge recovery efficiency is improved and lower power consumption is realized. In this embodiment, although depending on the capacitance values of the charge / discharge capacity and the charge recovery capacity and the number of the charge recovery capacity, a charge recovery efficiency of 50% or more, for example 70%, can be obtained. The charge recycling method described here can be applied to the self-refresh operation of the DRAM shown in the conventional example.

Next, the seventh embodiment will be described with reference to the schematic diagram showing the charging state of each capacitor in FIG. 22 and the operation timing chart in FIG. The circuit configuration is the same as that of the sixth embodiment shown in FIG.

First, at time t1, the switches SC1 and SR
1, ST5 to ST8 are on, other switches are off, and the charge / discharge capacity CR1 is charged to the power supply voltage.
At the next time t2, the switch SC1 is turned off and the switch ST is turned on.
1 to ST4 are on, and the charges of the charge / discharge capacitor CR1 are recovered in the charge recovery capacitors CS1 to CS4 connected in parallel. At the next time t3, the switch SD1 is turned on, ST
1 to ST4 are off, and the charge of the charge / discharge capacity CR1 is discharged to the ground voltage. At the next time t4, the switch SD1
Is off, ST1 to ST4 are on, and the charge recovery capacitors CS1 to CS4 connected in parallel to the charge charge / discharge capacitor CR1.
Charge is recovered from the. At the next time t5, the switch ST
1 to ST5 and ST7 are off, switches ST9 and ST11
Is on, and the charge recovery capacitors CS1 to CS2 and the charge recovery capacitors CS3 to CS4 are connected in series, respectively.
At the next time t6, the switches ST1 and ST3 are on, and further charges are discharged from the charge recovery capacitors CS1 to CS2 connected in series to the charge charge / discharge capacitor CR1 and from the charge recovery capacitors CS3 to CS4 connected in series. Be recovered. At the next time t7, the switches ST1, ST3, ST7
Is off, the switch ST10 is on, and the charge recovery capacitors CS1 to CS4 are connected in series. At the next time t8, the switch ST1 is on, and the charges are further recovered from the charge recovery capacitors CS1 to CS4 connected in series. At the next time t9, the switches SC1, SR1, ST5 to ST
8 is on and the other switches are off, the state is the same as at time t1, and the charge / discharge capacity CR1 is charged to the power supply voltage. By repeating such an operation, the charge of the charge / discharge capacity CR1 is recovered and reused in the charge recovery capacity.

In the seventh embodiment, as in the sixth embodiment, at the time of charge recovery, charge recovery capacitors are connected in parallel and the potential level is lowered to collect as much charge as possible. At the time of reuse, a charge recovery capacitor is connected in series to increase the potential level so that as much charge as possible can be reused. Further, when reusing the charges, the charge recovery capacitors connected in series are divided to increase the potential level, so that as much charge as possible can be reused.

[0077]

According to the semiconductor device of the present invention, among the plurality of charge recovery capacitors, charges are sequentially recovered from the charge recovery capacitors having a high potential, and the charges are sequentially recovered from the charge recovery capacitors having a low potential. By utilizing the charges, and by sequentially recovering the charges from the one having a higher potential among the plurality of charge charging / discharging capacities and sequentially reusing the charges from the one having a lower potential, the charge reuse rate is 50%. As described above, it is possible to realize smaller power consumption. Further, the charges can be reused in the operation nodes for charging and discharging the charges in the same memory cell array. Also,
By switching the electrical connection of multiple charge recovery capacitors to parallel connection or series connection, the charges are recovered by the charge recovery capacitors in parallel connection, and the charges are reused by the charge recovery capacitors in series connection. As a result, it is possible to recover more electric charge, and thus it is possible to realize smaller power consumption.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a concept of a charge recycling method in a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a schematic diagram showing a charge state of each capacitor during a charge recycling operation in the semiconductor device of FIG.

FIG. 3 is a schematic diagram showing a charge state of each capacitor during a charge recycling operation in the semiconductor device of FIG.

FIG. 4 is a schematic diagram showing a charge state of each capacitor during a charge recycling operation in the semiconductor device of FIG.

5 is a schematic diagram showing a charge state of each capacitor in the charge recycling operation in the semiconductor device of FIG.

6 is an operation timing chart at the time of charge recycling operation in the semiconductor device of FIG. 1;

7 is a graph showing the relationship between the charge collection / discharge capacity and the charge recovery capacity in the semiconductor device of FIG. 1 and the charge recovery rate.

FIG. 8 is a circuit diagram showing a concept of a charge recycling method in a semiconductor device according to a second embodiment of the present invention.

9 is a schematic diagram showing a charge state of each capacitor during a charge recycling operation in the semiconductor device of FIG.

10 is an operation timing chart at the time of charge recycling operation in the semiconductor device of FIG. 8;

FIG. 11 is a circuit diagram showing a concept of a charge recycling method in a semiconductor device according to a third embodiment of the present invention.

12 is an operation timing chart at the time of charge recycling operation in the semiconductor device of FIG.

FIG. 13 is a circuit diagram showing a concept of a charge recycling method in a semiconductor device according to a fourth embodiment of the present invention.

FIG. 14 is a schematic diagram showing a charge state of each capacitor during a charge recycling operation in the semiconductor device of FIG.

FIG. 15 is a circuit diagram showing a concept of a charge recycling method in a semiconductor device according to a fifth embodiment of the present invention.

16 is a schematic diagram showing a charge state of each capacitor during a charge recycling operation in the semiconductor device of FIG.

17 is a graph showing the relationship between the number of times of charge reuse (recycling) and the potential after charge recycling in the semiconductor device of FIG.

18 is a graph showing the relationship between the charge recovery capacity and the charge recycle rate per cycle in the semiconductor device of FIG.

FIG. 19 is a circuit diagram showing a concept of a charge recycling method in a semiconductor device according to a sixth embodiment of the present invention.

FIG. 20 is a schematic diagram showing a charge state of each capacitor during a charge recycling operation in the semiconductor device of FIG. 19;

FIG. 21 is an operation timing chart at the time of charge recycling operation in the semiconductor device of FIG. 19;

FIG. 22 is a schematic diagram showing a charge state of each capacitor during a charge recycling operation in the semiconductor device according to the seventh embodiment of the present invention.

FIG. 23 is an operation timing chart at the time of charge recycling operation in the semiconductor device of FIG. 22;

FIG. 24 is a circuit diagram showing the concept of a charge recycling method in a conventional semiconductor device.

25 is a schematic diagram showing a charge state of each capacitor during a charge recycling operation in the semiconductor device of FIG.

FIG. 26 is a circuit diagram in which the charge recycling method in the semiconductor device of FIG. 24 is applied to DRAM self-refresh operation.

27 is an operation timing chart at the time of charge reuse in the self-refresh operation of the DRAM of FIG.

[Explanation of symbols]

C0-C2, CC, CR1-CR4, CS1-CS4
Capacity SC1 to SC4, SD1 to SD4, SR1 to SR4, S
T, ST1 to ST11 switch DM1, DM2 switch circuit t1 to t21 time P1 to P4 period MA1, MA2 memory cell array D1, / D1, D2, / D2 data line W1, W2 word line SA1, SA2 sense amplifier CS memory cell capacity CD Data line capacitances PD1, PD2, PS1, PS2 Precharge and equalize circuits PP1, PP2, PN1, PN2, N10 to N138
Node name VDH, VDL Level voltage φT, / φT, φS1, / φS1, φS2, / φS2
/ ΦC1, / φC2 control signal

   ─────────────────────────────────────────────────── ─── Continued front page       (56) References JP-A-6-203557 (JP, A)                 JP-A-5-109273 (JP, A)                 JP 62-21311 (JP, A)

Claims (4)

(57) [Claims] 1. A charge / discharge capacity connected to wiring,
Each of the first to n-th intermittent switches is connected to the wiring.
First to n-th plurality of charge recovery capacitors provided as
And a plurality of the plurality of charge / discharge capacities charged with electric charges.
When the charge is collected in the charge collecting capacitor, first, the first intermittent switch is turned on to
Connect only the charge / discharge capacity and the first charge recovery capacity
After recovering the charges in the first charge recovery capacitor,
Turn off the intermittent switch No. 1 and turn on the second to n-th intermittent switches in sequence.
When turned off, the second to n-th charge recovery capacitors are charged.
By collecting the plurality of charge collecting capacitors.
From the highest potential first charge recovery capacitor to the lowest potential n-th
Of the charge collection and discharge capacities, and
When reusing the charges from the individual charge recovery capacitors, first, the n-th intermittent switch is turned on and off,
Only the charge / discharge capacity and the n-th charge recovery capacity are
Connect and reuse charge from the nth charge recovery capacitor
After that, the same operation is repeated in the reverse order of the charge recovery.
Finally, the charge is returned from the first charge recovery capacitor.
By reusing, the plurality of charge recovery capacitors
The charges are reused in order from the one with the lowest potential, and then the charges are re-charged from the charged and discharged capacity.
When recovering charges to the plurality of charge recovery capacitors, is the potential of the plurality of charge recovery capacitors higher?
A semiconductor device having a charge reusing means, characterized in that the charges are sequentially recovered . 2. The charge recycling means according to claim 1 is used.
The plurality of charge recovery units to maximize the charge recovery rate.
A semiconductor device having charge reusing means characterized in that a capacitance value of a capacitance is set . 3. The wiring of the first to n-th intermittent switches
A plurality of first to n-th power electrodes provided via the respective
A plurality of first to n-th charges having a charge / discharge capacity.
The charge and discharge capacities are respectively the first to n-th charge charging capacitors.
Can be connected to the power supply to charge the electric charge via the switch
Configured through the first to nth charge discharging switches
It is configured to be connectable to a discharge circuit for discharging electric charge
Cage, first, turns on the first charge charging switch, before
In addition to charging the first charge charge / discharge capacity with charge,
Turn on the nth charge discharging switch to turn on the nth charge.
After discharging the charge from the charge / discharge capacity, the first charge / discharge
Power switch and the nth charge discharging switch.
Was off, then the first and second only on intermittent switch
The first charge charging / discharging capacity to the second charge charging / discharging capacity.
After the charge is collected in the discharge capacity, the second intermittent switch is used.
Switch off and then turn on the 3rd to nth intermittent switches in sequence.
When turned off, the third charge from the first charge / discharge capacity
The charges are sequentially collected into the nth to nth charge charging / discharging capacities, then the second charge charging switch is turned on, and
The second charge charge / discharge capacity is charged with an electric charge, and
The first charge discharging switch is turned on to turn on the first charge.
After discharging the charge from the charge / discharge capacity, the second charge charging
Switch and the first charge discharge switch are turned off
After that, from the first charge / discharge capacity to the second to nth
The same procedure as when recovering charges sequentially to the charge / discharge capacity of
In order from the second charge / discharge capacity to the third to nth
To the first charge and discharge capacity and the first charge and discharge capacity
The next charge is collected, and thereafter, the third to nth charge charge / discharge capacities are collected.
Sequential charging is performed, and each time the charge is discharged to the remaining charge / discharge capacity.
A semiconductor device having charge reusing means characterized by being stored . 4. The wiring is provided through an intermittent switch.
At least one charge / discharge capacity and intermittent connection to the wiring
Charge recovery capacitors provided via the switch
And a part or all of the plurality of charge recovery capacitors is
Switchable between parallel connection or series connection
And through a switch, from the charge / discharge capacity to the plurality of charge recovery capacity.
When recovering the charge, the plurality of charge recovery capacitors are
Connected in parallel, from the plurality of charge recovery capacitors to the charge / discharge capacitors
When reusing the charges, the plurality of charge recovery capacitors are used.
A semiconductor device having charge reusing means, characterized in that are connected in series .