JP3365914B2 - Synchronous reception control circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to a PHS (Personal).
Handyphone system) and the like, and particularly to a synchronous reception control circuit suitable for use in a mobile station thereof.

[0002]

2. Description of the Related Art PHS scramble processing and π / 4 QPSK (Quadrature Phase Shift Ke
ying) A modulated signal is transmitted and received between the base station mobile stations. Therefore, a modem or a scrambler / descrambler that scrambles / descrambles a transmission / reception signal by π / 4QPSK is required. Especially π / 4Q
If the modem for PSK modulation and demodulation cannot accurately synchronize the frequency and phase with the received signal, the synchronous reception operation will not be established. Therefore, the frequency error information held by the modem is updated only when the received electric field strength is sufficiently high. It is preferable that a DPLL (Digital Phase Locked Loop) built into the modem is operated (phase locked).
In the present application, the circuit for controlling the synchronous receiving operation according to the received electric field strength in this manner is referred to as a synchronous reception control circuit.

3 and 4 show the structure and operation timing of a synchronous reception control circuit conventionally used in a PHS mobile station. The modem 10 in FIG. 3 is the above-mentioned π / 4Q.
It is a modem for PSK modulation / demodulation, and its operation is directly controlled by the modem control unit 12. AFC of control signals given from the modem control unit 12 to the modem 10
Is a signal for automatically controlling the oscillation frequency of the oscillator built in or attached to the modem 10, and this signal is "H".
When the level is the level, the control is executed, and when the level is the "L" level, the control is not executed. That is, only when the AFC is set to the “H” level, the frequency error information held by the modem 10 can be updated based on the received signal related to the current reception time slot. RCW is a signal for controlling the phase pull-in operation by the DPLL built in the modem 10. When this signal is at the "H" level, the phase pull-in operation is executed and is at the "L" level. Sometimes it doesn't run. That is, only when RCW is set to the “H” level, the phase error information held in the DPLL can be updated based on the reception signal related to the current reception time slot.

The term "reception time slot" as used herein refers to the "RX" shown at the top of FIG. In PHS, as shown in this figure, four downlink time slots ("R
X ") and four uplink time slots to the base station (" T "
X ") alternately arrives. On the side of the mobile station, generally, one of a plurality of base stations existing in the vicinity is selected and transmission / reception is performed in synchronization with one of the up / down time slots of the selected base station. Further, each time slot has a ramp bit R and a guard bit G indicating the start and end of the slot, and a start symbol bit preceding the data body, as indicated by "RD" in the center of the figure. SS, preamble bit PR and unique word bit UW, body data bit not shown in the figure,
And CRC (Cyclic Redundanc) that follows the data body
y Check) Bit CR. The circuit shown in FIG. 3 has a timing generator 14 which detects the end timing of this reception time slot and generates a reception interrupt signal RXINT. Therefore, the RXINT generation cycle is 5
ms. RXINT is an interrupt signal for causing the CPU 16 to execute received data processing.
According to the XINT, the main body data and the like received in the reception time slot immediately before that are processed.

The timing generator 14 and the CPU 16 are
It also plays a role in synchronous reception control using the modem control unit 12. That is, the timing generator 14 detects not only the reception time slot end timing described above but also the arrival timing of PR, and generates an electric field measurement request signal in response to this detection. The electric field measurement request signal is sent to the RSSI (Receiving Signal Strength) by the A / D converter 18.
h Indicator) signal is a signal for converting the signal from analog to digital, and the RSSI signal supplied from a radio unit (not shown) is digitized by the A / D converter 18 and then used as a measurement result signal by the CPU 16. Supplied. The CPU 16 compares the value of this measurement result signal with a predetermined reference value in response to the occurrence of RXINT. if,
If the former is higher than the latter, it can be considered that the received electric field strength is good, and if it is lower, it is not so. The CPU 16 gives a command to the modem control unit 12 according to the result. That is, when the value of the measurement result signal exceeds the reference value, the AFC and RCW are set to the “H” value,
If it is below the range, it is set to the “L” value. By doing so, the frequency error information and the phase error information held by the modem 10 and its DPLL can be updated only when the received electric field strength is sufficiently high. The effect of is small.

On the other hand, in this conventional technique, the CPU 16 uses the R
A command to the modem control unit 12 is generated by software according to XINT. By doing so, as shown in the upper half of FIG. 4, for example, AFC and R based on the received electric field strength measured in the receiving time slot “1”
The CW is generated after the timing of the reception time slot “2”. In other words, the received electric field strength variation in a short cycle cannot be dealt with by the interrupt process by the CPU 16. Therefore, when the received electric field strength is changing in a short cycle such as within one frame, AFC and RCW
However, the control that uses s.sub.1 will adversely affect the synchronous reception operation by the modem 10. The CPU 16 shown in FIG.
Is a general control member that realizes the above-mentioned commands related to the received data processing and modem control as well as other functions not shown in the figure. Therefore, in order to use the reception-related processing function in the CPU 16, the RXINT interrupt is used. I have no choice but to use this method.

[0007]

SUMMARY OF THE INVENTION One of the objects of the present invention is to enable the control of the synchronous receiving operation utilizing the measurement result of the received electric field strength to be executed without waiting for the arrival of the next receiving time slot. It is to make it possible to deal with the fluctuation of the received electric field strength in a short cycle that could not be dealt with, and thus to carry out a more stable synchronous receiving operation.

In order to achieve such an object, in the present invention, C which processes received data according to a received interrupt signal is used.
A timing generator, a measurement circuit, and a control unit independent of the PU are provided, and the measurement circuit and control unit are operated prior to the arrival of the data bit related to the current reception time slot. That is, in the present invention, the timing generator detects the end timing and the arrival timing of the preamble bit with respect to each reception time slot of the synchronization destination including the preamble bit and the data bit following the preamble bit,
A reception interrupt signal is generated at the end timing, and a measurement request signal is generated at the arrival timing.
The reception electric field strength in the current reception time slot is measured according to the measurement request signal, the control unit compares the measured reception electric field strength with a predetermined reference value, and when the former exceeds the latter, the reception result of the current reception time slot Based on the current reception
The parameter related to the synchronization in the data bit in the imslot is updated, and when it falls below the value, it is kept as it is. As described above, since the synchronous receiving operation is controlled by using the hardware independent of the CPU, the synchronous receiving operation does not occur until the CPU receives the interrupt by the reception interrupt signal. Therefore, it is possible to cope with the fluctuation of the received electric field strength in a short cycle, which cannot be dealt with by the prior art in which the synchronous receiving operation is not performed until the CPU receives an interrupt by the reception interrupt signal, and thus a more stable synchronous receiving operation. Can be executed.

The above parameters in the present invention are, for example,
It is frequency or phase information for frequency or phase synchronization with the received signal related to the current reception time slot. For example, P
These are frequency error information and phase error information held in the π / 4QPSK modem of the HS mobile station. Therefore, the present invention can be suitably applied to the PHS mobile station. However, the application target of the present invention is not limited to the PHS portable station, and the present invention can be applied to various receivers in which the CPU receives an interrupt and processes received data. Further, it is preferable that the reference value in the present invention can be variably set by the CPU.
Further, although the present invention is described as an invention related to the “synchronous reception control circuit” in the present application, it is understood and expressed as an invention related to other categories such as “synchronous reception control method”, “receiver”, and “mobile station”. Modifications will be apparent to those of ordinary skill in the art having reference to the description of the present application. The gist of the present invention will become clearer in the following description of the embodiments.

[0010]

1 and 2 show the structure and operation timing of a synchronous reception control circuit according to an embodiment of the present invention. It should be noted that the members corresponding to the members shown in FIGS. 3 and 4 are denoted by the same reference numerals, but this is for simplification of description and suggests that the configurations and functions are the same. Not something to do. In the circuit shown in FIG. 1, the timing generator 14 is provided to the CPU 16 as in the prior art described above.
In addition to giving XINT and executing an interrupt for processing received data, the electric field measurement controller 20 is notified of the arrival timing of PR. In response to this, the electric field measurement control unit 20 supplies the electric field measurement request signal to the A / D converter 18, and the A / D converter 18 outputs a signal indicating the measurement result of the electric field strength accordingly. The electric field measurement control unit 20, which is hardware independent of the CPU 16 and the like, detects the signal value obtained from the A / D converter 18 and indicating the electric field strength measurement result, and the CPU 1
Reference value variably set by 6 ("electric field strength comparison value")
Compare with. When the former exceeds the latter, the electric field measurement control unit 20 determines that AFC and RCW are at the “H” level,
When it is below the level, a command is given to the modem control unit 12 so that the level becomes "L" level.

Therefore, in this embodiment, as shown in FIG. 2, the modem control can be executed at an early timing within 30 bits from the first SS, that is, before the data bit in the current reception time slot. As a result, it is possible to prevent the frequency and phase synchronization from being adversely affected by the fluctuation of the received electric field strength in a short cycle. It should be noted that the present invention is not limited to the invention that the function of determining the threshold value of the received electric field strength is separated from the CPU 16 and provided as another hardware. That is, RXINT
While maintaining the conventional framework of interrupting the CPU 16 and processing the received data by the CPU,
Note that it allows the modem control to be performed without affecting the other 16 operations (other than burden reduction).

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a circuit according to an embodiment of the present invention.

FIG. 2 is a timing chart showing the operation of this circuit.

FIG. 3 is a block diagram showing a configuration of a circuit according to a conventional technique.

FIG. 4 is a timing chart showing the operation of this circuit.

[Explanation of symbols]

10 modem, 12 modem control unit, 14 timing generator, 16 CPU, 18 A / D converter, 20
Electric field measurement controller, SS start symbol bit, P
R preamble bit, UW unique word bit, CR CRC bit, RXINT reception interrupt signal.

Front page continued (72) Inventor Masato Mito 5-1-1 Shimorenjaku, Mitaka-shi, Tokyo Nihon Radio Co., Ltd. (72) Inventor Tetsuya Shiobara 5-1-1 Shimorenjaku, Mitaka-shi, Tokyo Nihon Radio Co., Ltd. In-house (56) Reference JP-A-5-344046 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H04B 7/26 H04L 29/02

Claims (3)

(57) [Claims] 1. An end timing and arrival timing of a preamble bit of each synchronization destination reception time slot including a preamble bit and a data bit following the preamble bit are detected, and a reception interrupt signal is generated at the end timing. A timing generator that generates a measurement request signal at the arrival timing, a measurement circuit that measures the received electric field strength in the current reception time slot according to the measurement request signal, and the measured received electric field strength as a predetermined reference value. In comparison, when the former exceeds the latter , the data bit in the current reception time slot is determined based on the reception result of the current reception time slot.
And a control unit that updates the parameter related to synchronization and keeps it as it is when it falls below. The timing generator, the measurement circuit, and the control unit are independent of the CPU that processes the reception data according to the reception interrupt signal. The synchronous reception control circuit is characterized in that the measurement circuit and the control unit operate prior to the arrival of the data bit related to the current reception time slot. 2. The synchronous reception control circuit according to claim 1, wherein the parameter is frequency or phase information for frequency or phase synchronization with a received signal relating to a current reception time slot. 3. The synchronous reception control circuit according to claim 1, wherein the reference value is variably set by the CPU.