JP3366282B2 - Sampling clock phase adjustment system, sampling clock phase adjustment method, and recording medium - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sampling clock phase adjusting technique used for A / D (analog / digital) conversion for converting an analog video signal into a digital signal, and particularly, to quickly find an optimum phase for sampling. The present invention relates to a sampling clock phase adjusting system, a sampling clock phase adjusting method, and a recording medium for reducing the phase adjusting time.

[0002]

2. Description of the Related Art Conventionally, in digital video equipment, sampling is performed by an A / D converter in order to convert an analog video signal into a digital signal. The sampling clock of the A / D converter uses a PLL (Pha
It is created by adding a predetermined delay amount (time delay amount) to the reference clock generated by dividing the frequency with se Locked Loop. If the delay amount at this time is not set to an appropriate value, noise will be superimposed on the video data (digital signal) sampled by the A / D converter. In order to avoid such superposition of noise, it is necessary to obtain an appropriate delay amount.

As such a conventional technique, for example, there is one described in Japanese Patent Application Laid-Open No. 5-173514 (first conventional technique). That is, the first prior art aims to reduce the occurrence of creases in diagonal lines and to increase the resolution higher than the number of pixels in a color matrix display element in which three RGB pixels are arranged continuously. It is a technique for improving apparent horizontal resolution in a liquid crystal panel arranged in a stripe in order, and discloses sampling each RGB signal with two-phase sampling clocks having different phases. Specifically, an image signal (analog video signal) to be displayed is input as three primary color signals, digitally converted and output as A corresponding to each primary color signal.
A D / D converter, a control circuit that takes in a synchronization signal included in an image signal (analog video signal), creates and outputs various timing signals including a sampling clock,
A matrix display panel, a vertical scanning circuit driven by a timing signal from a control circuit to scan the matrix panel in a vertical direction, and a digital signal to be displayed from an A / D converter is input to the matrix while scanning in a horizontal direction. It consists of a horizontal scanning circuit that writes on the panel,
In a matrix display device for displaying an image on a matrix panel, an A / D corresponding to a green primary color signal from a control circuit
Phase shift for shifting the phase of the sampling clock supplied to the converter and the phase of the sampling clock commonly supplied from the control circuit to the two A / D converters corresponding to the respective primary color signals of red and blue by 180 ° It is a matrix display device provided with a circuit. According to such a matrix display device, the phase of the sampling clock used for analog / digital conversion of the input G primary color signal or the phase of the sampling clock used in the horizontal scanning circuit is used for the input B and R primary color signals. 180 for the sampling clock phase
By shifting and sampling the G, B, and R primary color signals accordingly, it is possible to maintain a sufficiently good image quality as compared with the case of sampling with a clock without phase shifting, and the phase shifting of the sampling clock is 12
Compared with the conventional technique of performing 0 °, there is an advantage that the circuit scale can be greatly simplified and the cost can be reduced.
Even when the TFT liquid crystal panel in which the pixel arrangement of the three pixels forming the dots is arranged in the order of R, G, B is applied, the effect of applying the present invention and obtaining the same advantage is disclosed. ing.

Another conventional technique is disclosed in, for example, Japanese Patent Laid-Open No. 10-86312. That is, the second conventional technique aims to reduce the occurrence of creases in diagonal lines and to increase the resolution higher than the number of pixels in a color matrix display element in which three RGB pixels are continuously arranged. This is a technique for improving the apparent horizontal resolution in a liquid crystal panel arranged in order on a stripe. Each of the RGB signals has a different phase.
Sampling with a phase sampling clock is disclosed. Specifically, a three-phase clock having a predetermined cycle is generated from a liquid crystal display panel having pixels of 350,000 pixels or more and pixels arranged in stripes and a synchronization signal included in an image signal (analog video signal). Clock generation means to operate, image signal (analog video signal) red,
A liquid crystal display device comprising: a conversion unit that converts a green signal and a blue signal into a digital signal at each timing of a three-phase clock; and a drive unit that drives a liquid crystal display panel based on the digital signal output from the conversion unit. . According to such a liquid crystal display device, the effect that the resolution in the horizontal direction can be improved and a detailed display can be performed is disclosed.

[0005]

However, in the above-mentioned conventional technique, the same clock is supplied to the three video A / D converters for RGB, and the clocks are gradually shifted to obtain the optimum delay amount. However, there is a problem that it takes a relatively long time to adjust the delay amount.

The present invention has been made in view of the above problems, and an object of the present invention is to quickly obtain an optimum phase at the time of sampling to shorten the phase adjustment time. A sampling clock phase adjusting method and a recording medium are provided.

[0007]

The gist of the invention described in claim 1 is a sampling clock phase adjusting system for quickly obtaining an optimum phase for sampling and shortening the phase adjusting time. Sometimes the red video signal contained in the analog video signal is sampled by the first clock.
A for red image converted to digital signal by pulling
The / D converter and the green video signal included in the analog video signal at the time of phase adjustment are different in phase from the first clock.
And a green video A / D converter for converting into a digital signal by sampling with a second clock, and a blue video signal included in the analog video signal during phase adjustment .
Sump by the 3rd clock whose phase is different from 2 clocks
A / for blue video converted to digital signal by ring
D converter and sampler with three-phase sampling clocks having different phases in the first to third clocks
A means for detecting a ng miss and each of the detected
Asked a sampling clock having a little phase of most sampling errors from sampling error, it was the determined support
The sampling clock to the A / D converter for the red image,
A / D converter for the green image and A / D for the blue image
It consists in sampling clock phase adjustment system, characterized in that it comprises a means for controlling the sampling at the same timing in parallel supplied to each D converter. A second aspect of the present invention is a first delay unit that generates and outputs the first clock having a first phase delay with respect to an input clock, and a second phase with respect to the input clock. characterized in that it has a second delay unit for generating and outputting said second clock having a delay, and a third delay unit for generating and outputting said third clock having a third phase delay with respect to an input clock The sampling clock phase adjusting system according to claim 1 .
Further, the gist of the invention according to claim 3 is that the first clock has a phase delay of 0 ° with respect to a reference clock, and the second clock has a phase delay of 120 ° with respect to the reference clock, The third clock is 24 with respect to the reference clock.
A phase lag of 0 ° is also provided , characterized in that
Exists in the sampling clock phase adjustment system described in 2 . Further, the gist of the invention according to claim 4 is the first
The clock has a phase of 60 ° with respect to the reference clock,
Claims, characterized in that with the second clock has a phase lag of 180 ° with respect to the reference clock, the first 3 300 ° phase delay clock is the reference clock
The sampling clock phase adjusting system described in 1 or 2 exists. The gist of the invention according to claim 5, before
The means for controlling the sampling includes the first clock having a phase delay of 0 ° with respect to the reference clock, the second clock having a phase delay of 120 ° with respect to the reference clock, and the third clock being the reference clock. A state having a phase delay of 240 ° with respect to a clock, and a state in which the first clock has a phase delay of 60 ° with respect to a reference clock and the second clock has a phase delay of 180 ° with respect to the reference clock. claims, characterized in that for switching between the state with the third phase delay of the clock 300 ° with respect to the reference clock
The sampling clock phase adjusting system described in 1 or 2 exists. A sixth aspect of the present invention is a sampling clock phase adjusting method for quickly obtaining an optimum phase for sampling and shortening a phase adjusting time, and a red color included in an analog video signal at the time of phase adjusting. depending the video signal to the sampling by the first clock
And red video for A / D conversion step of converting into a digital signal Te, a second clock having a different phase with green of the video signal first clock included in the analog video signal during phase adjustment
The A / D conversion step for green video, which is converted into a digital signal by sampling by, and the blue video signal included in the analog video signal at the time of phase adjustment are separated from the second clock.
And blue video for A / D conversion step of converting the de <br/> Ijitaru signal by sampling by the third clock having a different phase, before
Note: Detects sampling error in three-phase sampling clocks having different phases in the first to third clocks.
And a sampling clock having a phase with the least sampling error from the detected sampling errors, and the obtained sampling clock
The red image for A / D conversion process, and a step of controlling the sampling at the same timing in parallel supplied to each of the green image for A / D conversion process and the blue image for A / D conversion process A sampling clock phase adjusting method characterized by the above. A seventh aspect of the present invention provides a first delay step of generating and outputting the first clock having a first phase delay with respect to an input clock, and a second phase with respect to the input clock. A second delay step of generating and outputting the second clock having a delay;
7. The sampling clock phase adjusting method according to claim 6 , further comprising a third delay step of generating and outputting the third clock having a third phase delay with respect to the input clock. Further, the gist of the invention according to claim 8 is that the first clock is 0 ° with respect to a reference clock.
Claims of a phase lag, the second clock has a phase lag of 120 ° with respect to the reference clock, and having the first 3 240 ° phase delay clock is the reference clock The sampling clock phase adjusting method described in 6 or 7 exists. Further, the gist of the invention according to claim 9 is that the first clock has a phase delay of 60 ° with respect to a reference clock, and the second clock has a phase delay of 180 ° with respect to the reference clock, The sampling clock phase adjusting method according to claim 6 or 7 , wherein the third clock has a phase delay of 300 ° with respect to a reference clock. Further, according to a tenth aspect of the present invention, the first clock has a phase delay of 0 ° with respect to a reference clock and the second clock has a phase delay of 120 ° with respect to the reference clock. 3 clocks having a phase delay of 240 ° with respect to the reference clock, and the first clock having a phase delay of 60 ° with respect to the reference clock and the second clock having a phase of 180 ° with respect to the reference clock. claims wherein the third clock having a delay and having a step of switching between a state having a phase lag of 300 ° with respect to the reference clock
The sampling clock phase adjusting method described in 6 or 7 exists. Further, the gist of the invention according to claim 11 is a recording medium in which a sampling clock phase adjusting program for quickly obtaining an optimum phase at the time of sampling and shortening the phase adjusting time is recorded. The red video signal included in the signal is used as the first clock
And red video for A / D program code for converting a digital signal by sampling by green of the video signal first clock included in the analog video signal during phase adjustment
And sampling by the second clock with different phase
Green and video for A / D program code, third out of phase from the blue the second clock a video signal included in the analog video signal when the phase adjustment to be converted to a digital signal I
An A / D program code for blue image is converted to a digital signal by sampling by the clock, the first
~ Program code for detecting a sampling error in three-phase sampling clocks each having a different phase in the third clock and the detected respective samplings
The sampling clock having the phase with the least sampling error is obtained from the mistakes, and the obtained sampling clock
Lock the A / D conversion process for the red image, A for the green image
/ D converting step and said sampling clock phase adjustment program characterized by having program code for controlling the sampling <br/> grayed at the same timing in parallel supplied to each of the blue image for A / D conversion process Exists in a recording medium in which is recorded. A twelfth aspect of the present invention provides a first delay program code for generating and outputting the first clock having a first phase delay with respect to an input clock, and a second delay program code for the input clock. A second delay program code for generating and outputting the second clock having a phase delay, and a third delay program code for generating and outputting the third clock having a third phase delay with respect to the input clock.
Claims, characterized in that it comprises a delay program code
The present invention resides in a recording medium on which the sampling clock phase adjustment program according to item 11 is recorded. The gist of the invention according to claim 13 is that the first clock has a phase delay of 0 ° with respect to a reference clock, and the second clock has a phase delay of 120 ° with respect to the reference clock, The recording medium having the sampling clock phase adjustment program according to claim 11 or 12 , wherein the third clock has a phase delay of 240 ° with respect to a reference clock. The gist of the invention according to claim 14 is as follows.
The first clock has a phase delay of 60 ° with respect to a reference clock, the second clock has a phase delay of 180 ° with respect to the reference clock, and the third clock has a phase delay of 300 ° with respect to the reference clock. The recording medium recorded with the sampling clock phase adjusting program according to claim 11 or 12 , having the phase delay of
The invention according to claim 15 is that the first clock has a phase delay of 0 ° with respect to a reference clock, and the second clock has a phase delay of 120 ° with respect to a reference clock. 3 clocks are 240 with respect to the reference clock
And a state in which the first clock has a phase delay of 60 ° with respect to a reference clock, the second clock has a phase delay of 180 ° with respect to the reference clock, and the third clock has 13. A recording medium having a sampling clock phase adjusting program according to claim 11 or 12 , further comprising a program code for switching between a state having a phase delay of 300 ° with respect to a reference clock.

[0008]

BEST MODE FOR CARRYING OUT THE INVENTION The features of the embodiments described below are as follows.
The purpose is to quickly find the optimum phase for sampling (shortening the phase adjustment time).
A / D converter for red video that converts a red video signal included in an analog video signal into a digital signal, A / D converter for green video that converts a green video signal included in an analog video signal into a digital signal, and an analog video signal Blue video A / that converts the included blue video signal into a digital signal
It is possible to shorten the phase adjustment time by supplying to the D converter the clock that the CPU determines to have the least sampling error among the first clock, the second clock, and the third clock that have different delay amounts. To do so. That is, in three red video A / D converters, green video A / D converters, and blue video A / D converters that sample RGB signals, first, three phase sampling clocks (first clocks) having different phases are used. , The second clock, the third clock), and the sampling clock having the phase with the least sampling error among these samplings (that is, any one of the first clock, the second clock, and the third clock). Then, the sampling clock having the phase with the least sampling error is supplied in parallel to the three A / D converters for red image, A / D converter for green image and A / D converter for blue image at the same timing. It has a feature in sampling, and 3 when the video is displayed. Sampling clock (first clock, the second clock, third clock) is characterized in that it has a structure to operate in a single clock selected from among sampling. Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a functional block diagram for explaining a sampling clock phase adjusting system 100 according to an embodiment of the present invention. In FIG. 1, 12 is PL
L (Phase Locked Loop), 14 is a first delay unit, 16 is a second delay unit, 18 is a third delay unit, 20
Is a CPU, 20a is a switch control signal, 22R is an A / D converter for red images, 22G is an A / D converter for green images, 22B is an A / D converter for blue images, 24R is a sampling error detection unit for red images, and 24G. Is a sampling error detector for green image, 24B is a sampling error detector for blue image, 26 is a selector switch, 28 is a matrix switch, 100 is a sampling clock phase adjusting system, a, b, c, d, e, f, g. , H, i are unit switches in the matrix switch 28, R is a red video signal included in the analog video signal, G is a green video signal included in the analog video signal, B is a blue video signal included in the analog video signal, and Φ1 Is the first clock, Φ2 is the second clock, Φ3
Indicates the third clock.

Referring to FIG. 1, the sampling clock phase adjusting system 100 of the present embodiment has a PLL 1
2. A first delay unit 1 that generates and outputs a first clock Φ1 obtained by delaying an input clock by a first phase delay d1.
4. A second delay unit 1 that generates and outputs a second clock Φ2 that is obtained by delaying the input clock by the second phase delay d2.
6. A third delay unit 1 for generating and outputting a third clock Φ3 which is obtained by delaying the input clock by a third phase delay d3.
8. Detect the A / D converter with the least sampling error and execute the phase adjustment mode in which the clock used for sampling with the least sampling error is re-supplied to all A / D converters 22R, 22G and 22B. CPU 20, red image A / D converter 22R for converting a red image signal R included in an analog image signal into a digital signal, green image A / D converter for converting a green image signal G included in an analog image signal into a digital signal 22G, A / for blue video which converts the blue video signal B included in the analog video signal into a digital signal
Red image sampling error detector 24R for detecting sampling error in D converter 22B, red image A / D converter 22, and green image A / D converter 22G
Sampling error detection unit 24G for green image and A / D converter 22 for blue image that detects sampling error in
A selector switch 26 for selectively outputting either one of the output signal from the blue video sampling error detection unit 24B for detecting a sampling error in B, the output signal from the PLL 12 and the first delay unit 14, based on an instruction from the CPU 20, First delay unit 14, second delay unit 16 and third delay unit 18 having switches a, b, c, d, e, f, g, h, i.
1st clock Φ1, 2nd clock Φ2 and 3rd
A / D converter for red image 22 that selectively selects clock Φ3
R, A / D converter for green image 22G, A / D for blue image
The matrix switch 28 that supplies the converter 22B is provided.

In A / D conversion for converting an analog video signal into a digital signal, if a sampling error becomes large, a phenomenon that a difference in brightness between adjacent pixels is reduced or a difference in brightness between a pixel at the same position on the next screen and the like occurs. Phenomena such as getting bigger occur. Therefore, the red video sampling error detection unit 24R, the green video sampling error detection unit 24G, and the blue video sampling error detection unit 24B according to the present embodiment.
Then, the sampling error is detected by using one of these two phenomena.

In the CPU 20 of the present embodiment, the phenomenon that the difference in luminance between adjacent pixels of the red image sampling error detecting unit 24R, the green image sampling error detecting unit 24G and the blue image sampling error detecting unit 24B becomes small. When detecting a sampling error by using the sampling error detecting unit 24R for red image, the sampling error detecting unit 24G for green image and the sampling error detecting unit 24B for blue image
The luminance difference between adjacent pixels is detected via the, and the detected luminance difference is compared to show the largest luminance difference or the smallest luminance difference.
R, the sampling error detector 24G for green image or the sampling error detector 24B for blue image is selected.

Next, the operation (sampling clock phase adjusting method) of the sampling clock phase adjusting system 100 of the present embodiment will be described. Referring to FIG.
In the present embodiment, when the phase adjustment mode is entered, first, the central processing unit (CPU 20) tilts the selector switch 26 located immediately after the PLL 12 to the A side, and the unit switches a, e and i in the matrix switch 28. By closing the switch control signal 20a based on
The first clock Φ1 delayed by 0 ° (first phase delay d1) from the PLL 12 is supplied to the / D converter 22R, and 0 ° from the PLL 12 is supplied to the A / D converter for green video 22G.
The first clock Φ1 having the delay (the first phase delay d1) is delayed by 120 ° (the second phase delay d2) by the second delay unit 16 to supply the second clock Φ2, and the blue video A / D converter 22B is supplied. In the third delay unit 18, the first clock Φ1 with a 0 ° delay (first phase delay d1) from the PLL 12 is input to the second delay unit 18.
The third clock Φ3 delayed by 40 ° (third phase delay d3) is supplied. Then, the red image A / D converter 22R, the green image A / D converter 22G, and the blue image A / D converter 22B each perform sampling with the clocks {Φ1, Φ2, Φ3} out of phase. At this time, the CPU 20 causes the red video sampling error detection unit 24R and the green video sampling error detection unit 24 to operate.
G, which A / D converter (that is, the red video A / D converter 22R, the green video A / D converter 2) based on the detection signal from the blue video sampling error detection unit 24B.
One of the 2G and blue video A / D converters 22B) detects whether there is the least sampling error. Based on this result, the CPU 20 operates the matrix switch 28 again, and the A / D converter (that is, the red image A / D converter) with the least sampling error.
D converter 22R, green video A / D converter 22
The clock supplied to any one of the G and blue video A / D converters 22B is re-supplied to all the A / D converters 22R, 22G, and 22B, and the phase adjustment mode ends.

For example, a blue video A / D converter 22B
When the CPU 20 determines that there is the least sampling error, the unit switches a and e in the matrix switch 28 are opened based on the switch control signal 20a, and
By closing the unit switches g and h in the matrix switch 28 based on the switch control signal 20a, the clock with the least sampling error is supplied to all the A / D converters 22R, 22G and 22B.

By the way, when the jitter of the input signal is small, the phase adjustment is completed only by the sampling clock phase adjusting method, but when the jitter of the input signal is large, there are cases where the sampling clock phase adjusting method alone cannot deal with the phase adjustment. . For example, a sampling error of one A / D converter (that is, one of the A / D converter for red image 22R, the A / D converter for green image 22G, and the A / D converter for blue image 22B) Is very large, and any two of the other two A / D converters (that is, A / D converter 22R for red image, A / D converter 22G for green image, and A / D converter 22B for blue image) This case corresponds to the case where the sampling mistakes of the D converter) are about the same.

In the present embodiment, when the CPU 20 detects such a case, the selector switch 26 immediately after the PLL 12 is tilted to the B side, and the unit switches a, e and i in the matrix switch 28 are switched to the switch control signal 20a. The first clock Φ1 with a delay of 60 ° (first phase delay d1) from the PLL 12 is supplied to the red image A / D converter 22R by closing based on
The / D converter 22G is delayed by 180 ° by delaying the first clock Φ1 delayed by 60 ° (first phase delay d1) from the PLL 12 by the second delay unit 16 by 120 ° (second phase delay d2). Is supplied with the second clock Φ2 delayed by only the above, and the A / D converter 22 for blue video is supplied.
B is delayed by 60 ° from the PLL 12 (first phase delay d
The first clock Φ1 of 1) is further 24 by the third delay unit 18.
The third clock Φ3 delayed by 300 ° is supplied by delaying by 0 ° (third phase delay d3). Subsequently, the red image A / D converter 22R, the green image A / D converter 22G, and the blue image A / D converter 22B each have a phase-shifted clock {Φ1,
Φ2, Φ3} are used for sampling. At this time, C
The PU 20 determines which A / A based on the detection signals from the red video sampling error detection unit 24R, the green video sampling error detection unit 24G, and the blue video sampling error detection unit 24B.
D converter (that is, red image A / D converter 2
2R, A / D converter for green image 22G, A / D for blue image
Any one of the D converters 22B) detects whether the sampling error is the smallest. Based on this result, the CPU 20 operates the matrix switch 28 again, and the A / D with the fewest sampling errors.
Converter (namely, A / D converter 22 for red image)
R, A / D converter for green image 22G, A / D for blue image
Any one of the converters 22B A / D converter)
The clock supplied to the A / D converters 22R, 22G and 22B is supplied again to end the phase adjustment mode.

For example, a blue video A / D converter 22B
When the CPU 20 determines that there is the least sampling error, the unit switches a and e in the matrix switch 28 are opened based on the switch control signal 20a, and the unit switches g and h in the matrix switch 28 are determined based on the switch control signal 20a. Closed to supply the clock with the least sampling error to all the A / D converters 22R, 22G and 22B.

Next, technical differences between the present embodiment and the above-mentioned first and second conventional techniques will be described.

As described above, the first prior art disclosed in Japanese Patent Laid-Open No. 173514/1993 reduces the occurrence of diagonal line creases in a color matrix display element in which three RGB pixels are continuously arranged. This is a technique for improving the apparent horizontal resolution in a liquid crystal panel in which pixels are arranged in stripes in the order of RGB in order to increase the resolution equal to or more than the number of pixels. It is disclosed that the sampling clock is used.

Further, the second prior art described in Japanese Patent Laid-Open No. 10-186312 reduces the occurrence of diagonal line creases and increases the number of pixels in a color matrix display element in which three RGB pixels are continuously arranged. Is a technique for improving the apparent horizontal resolution in a liquid crystal panel in which pixels are arranged in stripes in the order of RGB for the purpose of increasing the resolution of the RGB signals.
Sampling with a phase sampling clock is disclosed.

On the other hand, in this embodiment, three red image A / D converters 22 for sampling the RGB signals are used.
R, A / D converter 22G for green image and A for blue image
In the / D converter 22B, first, three-phase sampling clocks (first clock φ
1, the second clock Φ2, the third clock Φ3), and the sampling clock having the phase with the least sampling error among these samplings (that is, the first clock Φ1, the second clock Φ2, and the third clock Φ3). One of the clocks), and then the three sampling clocks having the phase with the least sampling error are used as the three A / D converters for red image 22R, A / D converter for green image 22G, and A / D converter for blue image. It is characterized in that it is supplied to 22B in parallel and is sampled at the same timing, and the purpose is to quickly find the optimum phase at the time of sampling. . Further, the present embodiment adopts a configuration in which one clock selected from sampling is operated by three-phase sampling clocks (first clock Φ1, second clock Φ2, third clock Φ3) at the time of image display. However, the circuit operation itself is also different.

As described above, according to the present embodiment, it is possible to quickly obtain the optimum phase for sampling and shorten the phase adjustment time.

It should be noted that the present invention is not limited to the above-mentioned embodiments, and it is apparent that the respective embodiments can be appropriately modified within the scope of the technical idea of the present invention. Further, the number, positions, shapes, etc. of the above-mentioned constituent members are not limited to those in the above-mentioned embodiment, and the number, positions, shapes, etc. suitable for carrying out the present invention can be adopted. Moreover, in each figure, the same components are denoted by the same reference numerals.

[0024]

Since the present invention is configured as described above, it is possible to quickly obtain the optimum phase for sampling and shorten the phase adjustment time.

[Brief description of drawings]

FIG. 1 is a functional block diagram for explaining a sampling clock phase adjustment system according to an embodiment of the present invention.

[Explanation of symbols]

12 ... PLL 14 ... 1st delay part 16 ... 2nd delay part 18 ... 3rd delay part 20 ... CPU 20a ... Switch control signal 22R ... Red image A / D converter 22G ... Green image A / D converter 22B ... Blue Video A / D converter 24R ... Red video sampling error detector 24G ... Green video sampling error detector 24B ... Blue video sampling error detector 26 ... Selector switch 28 ... Matrix switch 100 ... Sampling clock phase adjusting system a, b, c, d, e, f, g, h, i ... Unit switch R in matrix switch ... Red video signal G included in analog video signal ... Green video signal B included in analog video signal ... Analog video signal Included blue video signal Φ1 ... First clock Φ2 ... Second clock Φ3 ... Third clock

Claims (15)

(57) [Claims] 1. A sampling clock phase adjustment system for quickly obtaining an optimum phase for sampling to shorten a phase adjustment time, wherein a red video signal included in an analog video signal during phase adjustment is a first clock. A red video A / D converter for converting into a digital signal by sampling with a second video clock having a phase different from that of the first clock for the green video signal included in the analog video signal during phase adjustment .
A / D converter for green video that converts into a digital signal by sampling, and a blue video signal included in the analog video signal at the time of phase adjustment by a third clock having a phase different from that of the second clock.
A / D converter for blue video which is converted into a digital signal by sampling according to sampling and a sampling error in sampling clocks of three phases having different phases in the first to third clocks are detected.
And a sampling clock having a phase with the least sampling error from the detected sampling errors, and the sampling clock thus found is used for the red image A / D converter, the green image A / D converter, and sampling clock phase adjustment system, characterized in that it comprises a means for controlling the sampling at the same timing in parallel supplied to each of the blue video a / D Converters. 2. A first delay unit which generates and outputs the first clock having a first phase delay with respect to an input clock, and the second clock which has a second phase delay with respect to the input clock. a second delay unit for generating and outputting, according to claim 1, characterized in that a third delay unit for generating and outputting said third clock having a third phase delay with respect to an input clock Sampling clock phase adjustment system. 3. The first clock has a phase delay of 0 ° with respect to a reference clock, the second clock has a phase delay of 120 ° with respect to the reference clock, and the third clock is a reference clock. The sampling clock phase adjusting system according to claim 1 or 2 , wherein the sampling clock phase adjusting system has a phase delay of 240 ° with respect to. 4. The first clock has a phase of 60 ° with respect to a reference clock, the second clock has a phase delay of 180 ° with respect to the reference clock, and the third clock has a phase of reference clock. The sampling clock phase adjusting system according to claim 1 or 2 , wherein the sampling clock phase adjusting system has a phase delay of 300 °. 5. The means for controlling the sampling comprises the first clock having a phase delay of 0 ° with respect to a reference clock and the second clock having a phase delay of 120 with respect to the reference clock.
A state in which the third clock has a phase delay of 240 ° with respect to the reference clock and the first clock has a phase delay of 60 ° with respect to the reference clock, and the second clock has 3. The sampling clock phase according to claim 1 , wherein a state in which the third clock has a phase delay of 180 ° with respect to a reference clock and the third clock has a phase delay of 300 ° with respect to the reference clock is switched. Adjustment system. 6. A sampling clock phase adjusting method for quickly obtaining an optimum phase for sampling and shortening a phase adjusting time, wherein a red video signal included in an analog video signal at the time of phase adjustment is a first clock. A / D conversion step for red video which is converted into a digital signal by sampling by the second video signal and a green video signal included in the analog video signal at the time of phase adjustment by a second clock having a phase different from that of the first clock.
A / D conversion step for green video by converting the digital video signal by sampling, and a blue video signal included in the analog video signal at the time of phase adjustment by a third clock having a phase different from that of the second clock.
A / D conversion step for blue video which is converted to a digital signal by sampling according to sampling , and a sampling error in three-phase sampling clocks having different phases in the first to third clocks is detected.
And a sampling clock having a phase with the least sampling error from the detected sampling errors, and the obtained sampling clock is used for the red image A / D conversion step and the green image A / D conversion step. sampling clock phase adjustment method characterized by a step of controlling the sampling at the same timing in parallel supplied to each of the conversion process and the blue image for a / D conversion process. 7. A first delay step of generating and outputting the first clock having a first phase delay with respect to an input clock, and a second clock having a second phase delay with respect to the input clock. a second delay step for generating and outputting, according to claim 6, characterized in that a third delay step of generating and outputting the third clock having a third phase delay with respect to an input clock Sampling clock phase adjustment method. 8. The first clock has a phase delay of 0 ° with respect to a reference clock, the second clock has a phase delay of 120 ° with respect to the reference clock, and the third clock is a reference clock. The sampling clock phase adjusting method according to claim 6 or 7 , wherein the sampling clock phase adjusting method has a phase delay of 240 ° with respect to. 9. The first clock has a phase delay of 60 ° with respect to a reference clock, the second clock has a phase delay of 180 ° with respect to the reference clock, and the third clock is a reference clock. 8. The sampling clock phase adjusting method according to claim 6 , wherein the sampling clock phase adjusting method has a phase delay of 300 ° with respect to. 10. The first clock has a phase delay of 0 ° with respect to a reference clock, the second clock has a phase delay of 120 ° with respect to a reference clock, and the third clock has a phase delay of reference clock. With a phase delay of 240 °, and the first clock is 60 with respect to the reference clock.
And switching the second clock having a phase delay of 180 ° with respect to the reference clock and the third clock having a phase delay of 300 ° with respect to the reference clock. 6. The method according to claim 6, wherein
Or the sampling clock phase adjusting method described in 7 . 11. A recording medium in which a sampling clock phase adjustment program for quickly obtaining an optimum phase for sampling to shorten the phase adjustment time is recorded, and a red image included in an analog image signal at the time of phase adjustment. A / D program code for red video that converts the signal into a digital signal by sampling with the first clock, and a green video signal included in the analog video signal during phase adjustment into a second clock that has a different phase from the first clock. Yo
A / D program code for green video which is converted into a digital signal by sampling and a blue video signal included in the analog video signal at the time of phase adjustment are generated by a third clock having a phase different from that of the second clock.
A / D program code for blue video which is converted into a digital signal by sampling according to the sampling , and a sampling error in the three-phase sampling clocks having different phases in the first to third clocks is detected.
A program code according to the above, and a sampling clock having a phase with the smallest sampling error from the detected sampling errors, and the obtained sampling clock is subjected to the A / D conversion step for the red image and the A / D for the green image. recording medium recorded with the sampling clock phase adjustment program characterized by having program code for controlling the sampling at the same timing in parallel supplied to each of the conversion process and the blue image for a / D conversion process. 12. A first delay program code for generating and outputting the first clock having a first phase delay with respect to an input clock, and a second delay program code having a second phase delay with respect to the input clock. claim, characterized in that it comprises a second delay program code for generating and outputting a clock, and a third delay program code for generating and outputting said third clock having a third phase delay with respect to an input clock A recording medium on which the sampling clock phase adjustment program according to item 11 is recorded. 13. The first clock has a phase delay of 0 ° with respect to a reference clock, the second clock has a phase delay of 120 ° with respect to the reference clock, and the third clock is a reference clock. 11. A phase delay of 240 ° with respect to
A recording medium on which the sampling clock phase adjustment program described in [3] is recorded. 14. The first clock has a phase delay of 60 ° with respect to a reference clock, the second clock has a phase delay of 180 ° with respect to the reference clock, and the third clock is a reference clock. 13. A phase delay of 300 ° with respect to
A recording medium on which the sampling clock phase adjustment program described in [3] is recorded. 15. The first clock has a phase lag of 0 ° with respect to a reference clock, the second clock has a phase lag of 120 ° with respect to the reference clock, and the third clock has a phase lag with respect to the reference clock. With a phase delay of 240 °, and the first clock is 60 with respect to the reference clock.
And a program code for switching between a state in which the second clock has a phase delay of 180 ° with respect to the reference clock and a third clock has a phase delay of 300 ° with respect to the reference clock. A recording medium on which the sampling clock phase adjustment program according to claim 11 or 12 is recorded.