JP3367255B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a double-diffused-Meta transistor (DMOSFET).
l-Oxide-Semiconductor-Field-Effect-Transistor) structure and manufacturing method thereof, and particularly, high breakdown voltage semiconductor device used for motor driver, power supply circuit, in-vehicle drive circuit, flat panel display, etc., and manufacturing method thereof Regarding

[0002]

2. Description of the Related Art Power M is used as an output control power element.
OSFET, IGBT (Insulated-Gate-Bipolar-Trans)
istor), bipolar transistor, SCR (Silicon-
Controled Rectifier) is known. Each of these devices outputs a fixed output when given an input 1
It is a control element corresponding to one-to-one, and the input / output characteristics of the element once built are basically unchanged under the same conditions.

FIG. 6 shows a sectional structure of an LDMOSFET (lateral DMOSFET) as an example of such an output control power element. The N ⁻ type semiconductor substrate 11 has P
Type channel well (ch-Pwell) 13 is provided, and a P ⁺ type contact region 14 and an N ⁺ type source region 15 for applying a potential to this channel well are adjacent to this channel well 13. Is provided. In addition, a thermal oxide film (LOCO) is formed on the substrate 11.
An N ⁺ type drain region 16 is provided so as to be separated from the channel well 13 with an S oxide film 12 interposed therebetween. Further, a gate electrode 18 (G) is provided on the channel well 13 via a gate oxide film 17. Then, the contact region 14 and the source region 15
The source electrode S is provided so as to be in contact with both of them, and the drain electrode D is provided so as to be in contact with the drain region 16.

In the LDMOSFET having such a structure, when a positive voltage is applied to the gate electrode G while a positive voltage is applied to the source electrode S and the drain electrode D, an inversion channel is formed in the surface region of the channel well 13. As a result, a current flows from the drain electrode D to the source electrode S. FIG. 7 shows a gate voltage (input voltage Vin) and a drain current (output current Iout) in the LDMOSFET of FIG.
2] is an input / output characteristic diagram showing a relationship with (1).

[0005]

As is apparent from FIG. 7, in the power element including the conventional LDMOSFET, the input / output characteristics of the element are unchanged under the same conditions. However, the input / output characteristics are affected by environmental changes such as temperature. That is, if the temperature changes for the same input voltage, the output current cannot be kept constant. Alternatively, even with power elements having the same structure, the output current may differ due to variations in manufacturing. Furthermore, even with the same power element, the output current cannot maintain a constant value due to aging.

Further, in the system, in the case of adjusting each output by using a plurality of power elements, it is necessary to design each power element separately or control circuit separately. The present invention has been made in view of the above problems, and an object thereof is to provide a semiconductor device in which individual input / output characteristics can be easily adjusted after manufacturing, and a manufacturing method thereof.

[0007]

[0008]

The invention according to claim 1 is
A first conductivity type semiconductor substrate, a second conductivity type channel well region provided on the main surface of the semiconductor substrate, a thermal oxide film selectively provided on the main surface of the semiconductor substrate, and the channel well. A second conductive type contact region provided in the region and applying a predetermined potential to the channel well region, and a first conductive type source region provided in the channel well region adjacent to the contact region,
A first conductivity type drain region provided on the main surface of the semiconductor substrate so as to be separated from the channel well region via the thermal oxide film, and provided on the channel well region via a gate oxide film. A first gate electrode, a second gate electrode in a potential floating state provided under the source region side end of the first gate electrode and in the gate oxide film, and the contact A source electrode provided so as to contact both the region and the source region, and a drain electrode provided so as to contact the drain region.

[0009]

According to a second aspect of the present invention, a semiconductor substrate of a first conductivity type, a channel well region of a second conductivity type provided on the first main surface of the semiconductor substrate, and a channel well region are provided. It is a second conductivity type contact region for applying a predetermined potential to the channel well region, an emitter region of the first conductivity type provided adjacent to the contact region to the channel well region, of said semiconductor substrate A second conductive type collector region provided on a second main surface opposite to the first main surface; a first gate electrode provided on the channel well region via a gate oxide film; a first second gate electrode of the lower and and potential floating state provided in the gate oxide in the film of <br/> end of the emitter region side of the gate electrode, the contact region and the emitter An emitter electrode provided so that contact with both frequency, characterized by comprising a collector electrode provided in contact with the collector region.

[0011]

According to a third aspect of the present invention, a step of forming a gate oxide film on a semiconductor substrate of the first conductivity type and a step of selectively providing a first polycrystalline silicon layer on the gate oxide film are provided .
Forming the first gate electrode, and
A step of selectively introducing a second conductivity type impurity into the semiconductor substrate by using a pole as a mask to form a second conductivity type channel well region; and the gate oxide film using the first gate electrode as a mask. By removing isotropically
The step of forming a recess in the lower part of the end portion of the first gate electrode , the step of oxidizing the exposed surface of the semiconductor substrate and the first gate electrode with a film thickness of half or less of the gate oxide film, and depositing a second polycrystalline silicon layer, anisotropically removing the second polysilicon layer, top to the recess
A second gate is formed by leaving a second polysilicon layer.
And a step of forming the gate electrode in a self-aligned manner .

[0013]

[0014]

[Action] The invention according to claim 1, on the first gate electrode
It is characterized in that a second gate electrode in a potential floating state is provided below the end portion on the source region side and in the gate oxide film. According to the semiconductor device having such a structure, the threshold voltage can be adjusted by injecting positive or negative charges into the second gate electrode after manufacturing, and the input / output characteristics can be changed after manufacturing. You can

The invention according to claim 2 is characterized in that a second gate electrode in a potential floating state is provided below the end of the first gate electrode on the emitter region side and in the gate oxide film. I am trying. According to the semiconductor device having such a structure, the threshold voltage can be adjusted by injecting positive or negative charges into the second gate electrode after manufacturing, and the input / output characteristics can be changed after manufacturing. You can

The invention according to claim 3 is based on claims 1 to 3.
In manufacturing the semiconductor device according to the first aspect, a gate oxide film is formed, and a first gate electrode is formed on the gate oxide film.
After that, the gate oxide film is isotropically removed by using the first gate electrode as a mask to form a recess under the end portion of the first gate electrode , and thereafter, a film thinner than the gate oxide film is formed. the exposed surface of the semiconductor substrate and the first gate electrode and oxide thickness, further depositing a second polysilicon layer over the entire surface, anisotropically removing the second polysilicon layer, the recess <br By leaving the second polycrystalline silicon layer,
The second gate electrode can be formed in a self-aligned manner.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the accompanying drawings. FIG. 1 is a sectional view according to a first embodiment in which the semiconductor device of the present invention is applied to an N-channel LDMOSFET. In the figure, an N ⁻ type silicon semiconductor substrate 11 is shown.
A thermal oxide film (LOCOS oxide film) 12 is selectively provided on the surface of the. Further, a P-type channel well (ch-Pwell) 13 is provided on the surface of the substrate 11, and the channel well 13 has a P ⁺ -type contact region 14 for applying a predetermined potential to the channel well. And an N ⁺ type source region 15 are provided adjacent to each other. Further, an N ⁺ type drain region 16 is provided on the substrate 11 so as to be separated from the channel well 13 via the thermal oxide film 12.

Further, a gate electrode 18 (G) made of, for example, polycrystalline silicon is provided on the channel well 13 via a gate oxide film 17.
The film thickness of the gate oxide film 17 is, for example, 100 nm. The source electrode S is provided so as to contact both the contact region 14 and the source region 15,
A drain electrode D is provided so as to contact the drain region 16.

In this embodiment, the gate oxide film 1 is also used.
In FIG. 7, a floating gate electrode 19 that is electrically floating is provided at a position corresponding to a partial region of the channel well 13 that is in contact with the source region 15. The floating gate electrode 19 has, for example, 5
The gate oxide film 17 located above the floating gate electrode 19 has a film thickness of 40 nm and the lower film thickness is 10 nm.

FIG. 2 shows the gate voltage (input voltage Vin) and drain current (output current Iou) of the LDMOSFET.
FIG. 4 is an input / output characteristic diagram showing a relationship with t). The characteristic (a) in FIG. 2 is obtained immediately after manufacturing, and corresponds to the input / output characteristic of the conventional LDMOSFET shown in FIG.

Next, the case where the input / output characteristics are changed by adjusting the threshold voltage of the LDMOSFET will be described. First,
Both the source electrode S and the drain electrode D are ground potential (0
V) is given. As a result, the channel well 13, the source region 15 and the drain region 16 are all held at the ground potential. Then, a positive high voltage is applied to the gate electrode 18,
For example, a voltage of 20 V or higher is applied. Then, the potential of the floating gate electrode 19 is set to a value of 0 V or more due to capacitance division due to parasitic capacitances existing between the source region 15 and the floating gate electrode 19 and between the floating gate electrode 19 and the gate electrode 18, respectively. The source region 15 and the floating gate electrode 19
FN (Fauler-Nordheim) tunnel current flows between and. As a result, negative charges are accumulated in the floating gate electrode 19. Then, even if the voltage is not applied to the gate electrode 18, the accumulated charge of the floating gate electrode 19 is maintained as it is.

In this state, even if a voltage for inverting the channel is applied to the gate electrode 18, the negative charges accumulated in the floating gate electrode 19 function to cancel the electric field for inverting. Therefore, the threshold voltage after the charge is accumulated in the floating gate electrode 19 is higher than the threshold voltage before the charge is accumulated in the floating gate electrode 19, and the input / output characteristic in this case is shown in FIG. It changes like (b) of. In this case, the output current becomes small even if the same input voltage as before is applied.

On the other hand, when a negative voltage is applied to the gate electrode 18 with the channel well 13, the source region 15 and the drain region 16 all held at the ground potential, a voltage is applied between the source region 15 and the floating gate electrode 19. A current flows in the opposite direction to the above, and as a result, positive charges are accumulated in the floating gate electrode 19. In this state, even if a lower voltage is applied to the gate electrode 18, the channel will be inverted. Therefore, the threshold voltage after accumulating positive charges in the floating gate electrode 19 becomes lower than the threshold voltage before accumulating charges in the floating gate electrode 19, and the input / output characteristics in this case are as shown in FIG. It changes like (c) in 2. In this case, the output current increases even if the same input voltage as before is applied.

In this way, the threshold voltage can be easily adjusted even after the manufacture, and the above-mentioned temperature change, variation in the threshold voltage at the time of manufacture, and time-dependent change in characteristics can be prevented. The output current can be set arbitrarily.

Next, an LDMOSFET having a structure as shown in FIG.
A manufacturing method for realizing the above will be described. 3A to 3F are cross-sectional views showing a main part in the order of steps when manufacturing the LDMOSFET of FIG.

First, a thermal oxide film (LOCO) having a thickness of, for example, 700 nm is formed on the mirror surface side of the N ^-- type silicon semiconductor substrate 11.
An S oxide film) 12 (shown in FIG. 1) is selectively formed. Similarly, a gate oxide film 17 having a film thickness of 100 nm is formed by a thermal oxidation process. Then, after depositing polycrystalline silicon on the entire surface by the CVD method, PEP (Photo Engraving Proc
The gate electrode 18 is formed by selectively leaving this polycrystalline silicon by using the ess) technique.

Next, boron ions are implanted and thermally diffused using the gate electrode 18 as a mask to form a P-type channel well (ch-Pwell) 13 (FIG. 3).
(A)) Similarly, using the gate electrode 18 as a mask, the gate oxide film 17 is isotropically removed by an isotropic etching technique using a hydrofluoric acid (HF) solution. The amount of removal at this time, that is, the amount of wraparound to the lower side of the gate electrode 18, causes the floating gate electrode 19 to be formed later.
Is determined (FIG. 3 (B)).

Next, the surface of the substrate 11 and the exposed surface of the gate electrode 18 are thermally oxidized to a film thickness not more than half that of the gate oxide film 17 (FIG. 3C). Then, the entire surface is deposited by the CVD method 4
Polycrystalline silicon 19a having a film thickness of 00 nm is deposited (FIG. 3D). At this time, the polycrystalline silicon also wraps around under the gate electrode 18 from which the gate oxide film 17 has been removed and grows.

Next, the reactive ion etching technique (RI
When the polycrystalline silicon 19a is anisotropically etched by an anisotropic etching technique such as E), the polycrystalline silicon 19a is only formed in the region between the gate electrode 18 and the channel well 13, as shown in FIG. Can be left as the floating gate electrode 19 of the remaining polycrystalline silicon.

After that, for example, boron and phosphorus ions are implanted and thermal diffusion is performed to perform the P ⁺ type contact region 14,
N ⁺ type source region 15 and N ⁺ type drain region 16
The element is completed by forming (as shown in FIG. 1) and the like.

In such a manufacturing method, a mask is not required when forming the floating gate electrode 19, and it can be provided in a self-aligned manner with respect to the gate electrode 18 and the channel well 13 and only in a necessary portion. As a result, the parasitic capacitance of the element manufactured can be reduced, and the process variation and the number of processes can be reduced.

FIG. 4 is a sectional view according to a second embodiment in which the semiconductor device of the present invention is applied to a P-channel LDMOSFET. P-channel LDMOSFE of this embodiment
The T is different from the N-channel LDMOSFET in FIG. 1 only in that the conductivity types of the substrate and the semiconductor regions are reversed, and the basic structure is the same.
That is, the P ⁻ type silicon semiconductor substrate 21 is used in place of the N ⁻ type silicon semiconductor substrate 11, and the P type channel well (ch-Pwell) 13 is changed to N type.
Type channel well (ch-Nwell) 23 is used for, using the P ⁺ type contact region 14 and instead of the N ⁺ -type source region 15 N ⁺ -type contact region 24 and the P ⁺ type source region 25, respectively In addition, a P ⁺ type drain region 26 is provided instead of the N ⁺ type drain region 16.

It goes without saying that the semiconductor device according to the present invention can be easily implemented not only in the LDMOSFET as in the above-mentioned embodiments but also in other power elements.
For example, it can be applied to a vertical type DMOSFET in which the drain region is formed on the surface of the substrate facing the source area formation surface.

Next, a case where the present invention is applied to a vertical type IGBT as a power element other than the DMOSFET will be described with reference to the sectional view of FIG. In the figure, N-
A P + type semiconductor region 32 is provided on the back surface of the type silicon semiconductor substrate 31. A thermal oxide film (LOCOS oxide film) 33 is selectively provided on the surface of the substrate 31. Further, a P-type semiconductor region 34 is provided on the surface of the substrate 31, and a P + -type semiconductor region 35 for giving a predetermined potential to the region 34 and an N + -type semiconductor region 34 are provided in the semiconductor region 34. And the semiconductor region 36 are provided adjacent to each other. Here, the semiconductor region 32 is a collector region.
Region, the semiconductor region 35 is a contact region, the semiconductor
The region 36 becomes the emitter region.

Further, a gate electrode 38 (G) made of, for example, polycrystalline silicon is provided on the semiconductor region 34 with a gate oxide film 37 interposed therebetween. An emitter electrode E is provided so as to contact both the semiconductor region 35 and the semiconductor region 36, and a collector electrode C is provided so as to contact the semiconductor region 32 provided on the back surface.

In this embodiment, the gate oxide film 3 is also used.
7, a floating gate electrode 39 that is in a floating state is provided at a position corresponding to a partial region of the semiconductor region 34 that is in contact with the semiconductor region 36.

In the thus constructed IGBT, both the emitter electrode E and the collector electrode C are grounded (0 V).
By applying a positive or negative voltage to the gate electrode 38 in the state of being applied with, the negative or positive charge is accumulated in the floating gate electrode 39, whereby the threshold voltage can be adjusted.

In the embodiment of FIG. 5, the case where the present invention is applied to the vertical type IGBT is explained.
It goes without saying that the semiconductor region corresponding to the collector can be implemented in the lateral type IGBT in which the semiconductor region corresponding to the collector is formed on the same face as the semiconductor region forming face corresponding to the emitter of the substrate, as in the case of the DMOSFET. .

[0039]

As described above, according to the present invention,
It is possible to provide a semiconductor device in which individual input / output characteristics can be easily adjusted after manufacturing, and a manufacturing method thereof.

[Brief description of drawings]

FIG. 1 is an LDMOSFET according to a first embodiment of the present invention.
Sectional view of.

FIG. 2 is an input / output characteristic diagram of the LDMOSFET of FIG.

3A to 3D are sectional views showing a method of manufacturing the LDMOSFET of FIG.

FIG. 4 is an LDMOSFET according to a second embodiment of the present invention.
Sectional view of.

FIG. 5 is a sectional view of an IGBT according to a third embodiment of the present invention.

FIG. 6 is a sectional view of a conventional LDMOSFET.

7 is an input / output characteristic diagram of the LDMOSFET of FIG.

[Explanation of symbols]

11 ... N ^- type silicon semiconductor substrate, 12 ... Thermal oxide film (LOCOS oxide film), 13 ... P type channel well (ch-Pwell), 14 ... P ⁺ type contact region, 15 ... N ⁺ type source Region, 16 ... N ⁺ type drain region, 17 ... gate oxide film, 18 ... gate electrode (G), 19 ... floating gate electrode, 21 ... P ⁻
Type silicon semiconductor substrate, 23 ... N-type channel well (ch-Nwell), 24 ... N + -type contact region, 25 ... P ⁺ -type source region of, 26 ... P ⁺ -type drain region, 31 ... N ^- Type silicon semiconductor substrate, 32 ... P
⁺ Type semiconductor region, 33 ... Thermal oxide film (LOCOS oxide film), 34 ... P type semiconductor region, 35 ... P ⁺ type semiconductor region, 36 ... N ⁺ type semiconductor region, 37 ... Gate oxide film, 38 ... Gate electrode, 39 ... Floating gate electrode.

─────────────────────────────────────────────────── ─── Continuation of front page (56) Reference JP-A-53-117982 (JP, A) JP-A 64-76769 (JP, A) JP-A-6-61256 (JP, A) JP-A 63- 3503 (JP, A) JP 3-214779 (JP, A) JP 4-38878 (JP, A) JP 6-310729 (JP, A) JP 6-163926 (JP, A) Special Table Sho-60-501187 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 29/78 H01L 21/8247 H01L 21/336

Claims (3)

(57) [Claims] 1. A semiconductor substrate of a first conductivity type, a channel well region of a second conductivity type provided on the main surface of the semiconductor substrate, and a thermal oxide film selectively provided on the main surface of the semiconductor substrate. A second conductivity type contact region provided in the channel well region for applying a predetermined potential to the channel well region, and provided in the channel well region adjacent to the contact region. A first conductivity type source region, a first conductivity type drain region provided on the main surface of the semiconductor substrate so as to be separated from the channel well region via the thermal oxide film, and a gate oxide film A first gate electrode provided on the channel well region, and a potential floating provided under the end of the first gate electrode on the source region side and in the gate oxide film. A second gate electrode in a state, a source electrode provided in contact with both the contact region and the source region, and a drain electrode provided in contact with the drain region. Semiconductor device. 2. A semiconductor substrate of a first conductivity type, a channel well region of a second conductivity type provided on a first main surface of the semiconductor substrate, and a channel provided in the channel well region. A second conductivity type contact region for applying a predetermined potential to the well region; a first conductivity type emitter region provided in the channel well region adjacent to the contact region; A second conductive type collector region provided on a second main surface opposite to the first main surface, a first gate electrode provided on the channel well region via a gate oxide film, A second gate electrode, which is provided below the end of the gate electrode on the side of the emitter region and in the gate oxide film and which is in a floating state, and contacts both the contact region and the emitter region. A semiconductor device comprising: an emitter electrode provided so as to be provided; and a collector electrode provided so as to be in contact with the collector region. 3. A step of forming a gate oxide film on a semiconductor substrate of a first conductivity type, and a first polycrystalline silicon layer is selectively provided on the gate oxide film to form a first gate electrode. A step of forming a second conductivity type channel well region by selectively introducing a second conductivity type impurity into the semiconductor substrate using the first gate electrode as a mask; and the first gate electrode. by isotropically removing the gate oxide film as a mask, the first gate electrode
Forming a depression in the lower part of the end of the gate oxide film, oxidizing the exposed surface of the semiconductor substrate and the first gate electrode with a film thickness equal to or less than half of the gate oxide film, and forming a second polycrystalline silicon film over the entire surface. depositing a layer, anisotropically removing the second polysilicon layer, said recess
Only by leaving the second polycrystalline silicon layer above.
And a step of forming the second gate electrode in a self-aligned manner.