JP3367918B2 - Physical layer circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to IEEE 1394.
The present invention relates to a physical layer circuit used in a data transmission method conforming to the standard.

[0002]

2. Description of the Related Art High-speed serial bus IEEE1394-1
P13 under consideration as 995 or its additional specifications
94a is a standard developed for transmitting a large amount of data such as images at high speed between information devices such as computers and digital video cameras. According to this standard, data transmission using a transmission medium composed of four electric signal lines (two twisted pair lines) is realized.

Further, the P1394b standardization committee discusses a data transmission method using two optical fibers as transmission media.

IEEE 1394-1995 or P13
In the 94a, characteristic values such as the maximum transmission rate, the presence / absence of power supply capability, and the maximum repeat delay time that may vary depending on the port are recorded in the physical layer circuit as part of the device information. This information is determined not for each port but for each physical layer circuit. This information can be read from other devices on the bus. Also, based on this information, a packet called self-ID packet for notifying its own capability is generated and transmitted to the bus. It is also becoming.

In P1394b, some of the information is recorded for each port, but it is not all the information unique to the port, and means for reading from other devices and notifying to the bus. Is not specified.

FIG. 9 is a diagram of a self-ID packet when the physical layer circuit has three ports. In this figure, parts other than the port characteristics are omitted.
Reference numeral 11 is called a PHY_SPEED field and describes the maximum transmission rate that can be handled by the physical layer circuit. This value is determined irrespective of the capability of the port, but in reality, the transmission rate may be limited by the capability of the port, so it is a value that should originally be determined for each port. 12
Is called a POWER_CLASS field, and the presence / absence of power supply capability and its capability value are described. This value is also a value that may differ for each port.

Further, although not included in the self-ID packet, the maximum repeat delay time is the device information that may be different for each port. The maximum repeat delay time is the maximum value of the delay time allowed for repeat between ports, which outputs an input from a bus connected to a port to a bus connected to another port.

The maximum repeat delay time is IEEE139
The upper limit is defined in the 4-1995 standard. Further, the maximum value of the delay time allowed until the data from the link layer is output to the bus is defined by the P1394a standard.

The conventional method is illustrated by the physical layer circuit configurations 5-8. Each will be described below.

FIGS. 5 to 7 are circuit diagrams of circuits conforming to IEEE 1394-1995 or P1394a and supporting only electric signal lines as a transmission medium.

FIG. 5 shows the configuration of a physical layer circuit having only one port. 1-5 is a physical layer circuit for communication,
It is connected to the link layer circuit 3, which is the upper layer, and one connector 5. The connector 5 is connected to the bus.
The physical layer circuit is roughly divided into one controller 2 for controlling the entire physical layer circuit and the same number of ports 4 as the connectors 5 for directly exchanging information with the bus. In this example, the port 4 is a port called a DS port, which is connected to a bus composed of electric signal lines. self-ID
The device information 6 referred to when generating a packet is recorded in the controller 2.

Reference numeral 1-6 in FIG. 6 is a block diagram of a physical layer circuit having a plurality of (three in the example of this drawing) DS ports 4.

Similar to FIG. 6, 1-7 in FIG. 7 has all three ports as DS ports, but the maximum transmission rate of ports is 4-1 of 400 MHz and 4-2 of 200 MHz. It is a physical layer circuit in the case of.

Numerals 1-8 in FIG. 8 are P1394b and the like.
It is a physical layer circuit in which S ports and ports with different characteristics called beta ports coexist. 1-5 is different only in that two types of ports, a DS port 4 and a beta port 7, are mixed.

Even in a physical layer circuit having a plurality of ports such as 1-6, 1-7, and 1-8, the device information 6 is recorded in the controller 2 and is only one.

Consider a case where the device actually outputs a self-ID packet. As described above, the self-ID packet is generated based on the device information 6 in the controller. Therefore, the self-ID packet is the same as that transmitted from any port.

There is a problem when the physical layer circuit has one port as in the example of FIG. 5 or when the physical layer circuit has the same characteristics as in the example of FIG. Does not occur. However, as shown in FIGS. 7 and 8, even when ports having different characteristics are mixed, the same self-ID packet is transmitted from all ports,
The problem arises that the correct information is on the bus connected to one port, but incorrect on the bus connected to another port. Specifically, for example, in FIG. 7, the maximum possible transmission rate of the physical layer circuit is 400 MHz, so that PHY_SPEE of the self-ID packet is used.
D field 13 is set to 400MHz,
Actually, since the port 4-2 can handle only the speed up to 200 MHz, the information does not match the actual situation.

As described above, as a method for resolving the contradiction between the actual device state and the device information, Japanese Patent Laid-Open No. 11-9815
There is a method disclosed in Japanese Patent No. In this method, the transmission speed of all ports included in the physical layer circuit is adjusted to the maximum transmission speed of the slowest port, and the corresponding portion of the device information is overwritten at that transmission speed to obtain the device information and port speed. Are matched.

[0019]

As described above, even when ports having different characteristics coexist in one physical layer, the physical layer has only one type of device information. Can have. As a result, problems such as transmitting a self-ID packet containing information that does not match the actual situation and returning incorrect information in response to an access from another device occur.

According to the method disclosed in Japanese Patent Laid-Open No. 11-98159, it is possible to match the device information and the port speed with respect to the transmission speed. However, regarding the device information and the capability value other than the transmission speed, for example, the presence or absence of power supply capability, , You may still have information that does not fit the reality. Also,
Since the overall transmission speed is adjusted to the slowest port, for example, when repeating from the uppermost port 4-1 in FIG. 7 to the middle port 4-1, it is possible to repeat at a transmission rate of 400 MHz. However, this method also has the waste of being able to repeat only at a transmission rate of 200 MHz.

Further, as described above, the standard conforming to IEEE 1394 has an upper limit on the maximum delay time required for repeat between ports and the delay time generated for outputting data from the link layer circuit to the bus. It is not possible to connect a bus made of a transmission medium that requires a time exceeding the upper limit time to repeat between ports or repeat from a link layer to a bus.

The present invention was devised to solve these problems. It provides consistent device information even for devices having ports with different characteristics, and repeat delay time between ports and An object of the present invention is to support a transmission medium whose delay time between the link layer and the bus exceeds the limit of the IEEE 1394-1995 standard.

[0023]

A physical layer circuit according to claim 1 of the present invention is a physical layer circuit for performing communication conforming to IEEE 1394 having one main controller and one or more ports, and at least One or more sub controllers are provided between one port and the main controller.

The physical layer circuit according to claim 2 of the present invention is
The physical layer circuit according to claim 1, wherein the main controller and the sub-controller include at least information specific to a port directly connected to the controller.

The physical layer circuit according to claim 3 of the present invention is
The physical layer circuit according to claim 1 or 2, wherein port-specific information stored in a main controller or a sub-controller closest to each port is returned in response to access to each port from another device. And

One or more controllers (hereinafter referred to as sub-controllers) are connected between at least one port and a normal controller (hereinafter referred to as a main controller) to form a physical layer circuit, and By describing the information of the directly connected port in the device information of the controller, and for access from the bus, by returning the port specific information stored in the controller directly connected to the port connected to the bus, Provides device information that does not conflict with the capabilities of actual devices on the entire bus.

By providing one or more sub-controllers between the ports and the main controller, the maximum repeat delay time between the ports is the sum of the maximum repeat delay times of the device information of all the controllers existing between the ports. The link layer-bus delay time allowed is equal to the sum of the link layer-bus maximum delay time of the main controller and the maximum repeat delay time of all sub controllers provided between the port and the main controller. As a result, it is possible to support a bus composed of a transmission medium in which the repeat delay time between ports and the delay time between the link layer and the bus exceed the limit of the standard.

[0028]

BEST MODE FOR CARRYING OUT THE INVENTION (Embodiment 1) (When Two Types of Ports Coexist) FIG. 1 is a configuration diagram of a physical layer circuit of the present invention when two types of ports coexist.

Of the three ports, two are DS ports 4 and one is a beta port 7. A physical layer circuit 1-1 is configured by connecting a sub-controller 8 that is not connected to the link layer circuit between the beta port 7 and the main controller 2 which have different properties. Sub controller 8
Has a limited function as compared with the main controller 2, and can be configured smaller than the main controller.

In this structure, only one type of port is connected to each of all the controllers including the sub-controller. Since each controller has its own device information 6, by describing the part of the device information of each controller that describes the port characteristics based on the capability of the port directly connected to that controller, the entire bus Can provide correct device information.

(Second Embodiment) (When Two Ports are Connected to One Sub-Controller) FIG. 2 is a modified example of the case where the configuration is basically the same as that of FIG. 1, and the physical layer of FIG. The circuit 1-2 also has two DS ports 4 and one beta port 7 as in 1-1 of FIG. A configuration in which the controller 8 is connected between the two DS ports and the main controller 2 as shown in FIG.

(Third Embodiment) (When Three or More Kinds of Ports Coexist) FIG. 3 shows a case where three kinds of ports coexist. Here, DS port 4
Consider the case where there is an X port 9 having a characteristic that is neither. In this case as well, the physical layer circuit 1-3 is configured by inserting a sub controller between the port having different properties and the main controller. Portions of the device information 6 of each controller that describe the port characteristics are described based on the capabilities of the directly connected ports. By providing a plurality of sub-controllers as in this example, a physical layer circuit in which three or more types of ports are mixed can be configured.

(Embodiment 4) (When connecting to a bus with a long delay time) FIG. 4 shows a transmission medium in which it takes a long time to repeat between ports or to transmit the data received from the link layer to the bus. 6 is a configuration example of a physical layer circuit in the case of supporting the.

As described above, in the standard conforming to IEEE 1394, the maximum delay time required for repeat between ports and the delay time generated for outputting the data from the link layer circuit to the bus have an upper limit. In the above method, it is not possible to connect a transmission medium that requires a time exceeding the upper limit time to repeat between ports or output from the link layer to the bus.

However, as shown in FIG. 4, the sub-controller 8 is connected in series between the main controller 2 and the port 10 connected to the bus using a transmission medium with a large delay, and the physical layer circuits 1-4 are connected. The maximum repeat delay time of the sub-controller is set to a large value (for example, to the maximum value).

By doing so, each controller behaves as if it were one physical layer, and therefore the repeat between ports is limited to the sum of the maximum delay times of all the controllers connected in series. The repeat delay time is now allowed, and the delay time between the link layer and the bus is the maximum delay time between the link layer and the bus of the main controller and the maximum delay time of all the sub controllers provided between the port and the main controller. Since only the sum of repeat delay times is allowed, it is possible to connect to a bus made of a transmission medium with a large delay.

(Common to Embodiments 1 to 4) In the present embodiment, the physical layer circuit that performs communication conforming to the IEEE 1394 standard has been described as an example, but the configuration of the present invention is as follows.
The physical layer circuit has one piece of device information and one or more ports, supports communication of transmission media with different characteristics, repeat delay time per physical layer circuit, data from upper layer Can be applied to any physical layer circuit for performing communication in which the maximum value is set for the delay time until the transmission is transmitted to the communication medium.

[0038]

According to the physical layer circuit of the present invention, since the sub-controller also has the device information, it is possible to provide correct device information for each port.

Further, by providing a plurality of controllers between the ports, it becomes possible to support a transmission medium in which the repeat delay time between the ports and the delay time between the link layer and the bus exceed the standard limit.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a physical layer circuit according to a first embodiment of the present invention,
This is the case where two types of ports are mixed.

FIG. 2 is a configuration diagram of a physical layer circuit according to a second embodiment of the present invention,
This is the case where two ports are connected to one sub-controller.

FIG. 3 is a configuration diagram of a physical layer circuit according to a third embodiment of the present invention,
This is a case where three types of ports are mixed.

FIG. 4 is a configuration diagram of a physical layer circuit according to a fourth embodiment of the present invention,
This is when connecting to a bus with a long delay time.

FIG. 5 is a configuration diagram of a physical layer circuit in the related art.

FIG. 6 is a configuration diagram of a physical layer circuit in the related art, in which a plurality of ports of the same type are connected.

FIG. 7 is a configuration diagram of a physical layer circuit in the related art, in which a plurality of ports of the same type are connected to ports having different transmission rates.

FIG. 8 is a configuration diagram of a physical layer circuit in the related art, in which a plurality of different types of ports are connected.

FIG. 9 is an explanatory diagram of a self-ID packet conforming to IEEE1394.

[Explanation of symbols]

1-1 Physical layer circuit of Embodiment 1 of the present invention (when two types of ports are mixed) 1-2 Physical layer circuit of Embodiment 2 of the present invention (when two ports are connected to one sub-controller) ) 1-3 Physical layer circuit of Embodiment 3 of the present invention (when three types of ports are mixed) 1-4 Physical layer circuit of Embodiment 4 of the present invention (when connecting to a bus having a large delay time) 1- 5 Physical layer circuit in the related art (when one port is connected) 1-6 Physical layer circuit in the related art (when a plurality of ports of the same kind are connected) 1-7 Physical layer circuit in the related art (a plurality of ports) When the ports of the same type and different transmission rates are connected) 1-8 Physical layer circuit in the prior art (when a plurality of different types of ports are connected) 2 Physical layer controller 3 Link layer circuit 4 DS port 4-1 X port 11 speed is DS port 4-2 transmission speed of 400 MHz DS port 5 connector 6 device information 7 beta port 8 sub-controller 9 X port 10 repeat delay 200MHz large feed PHY_SPEED field 12 POWER_CLASS Field

Front page continued (72) Inventor Takashi Nishimura 22-22 Nagaike-cho, Abeno-ku, Osaka-shi, Osaka, within Sharp Corporation (72) Inventor Yuji Ichikawa 22-22 Nagaike-cho, Abeno-ku, Osaka, Osaka (72) ) Inventor Masafumi Takahashi 22-22 Nagaike-cho, Abeno-ku, Osaka, Osaka Prefecture (56) References JP-A-10-336252 (JP, A) JP-A-11-98159 (JP, A) JP-A 11-331215 (JP, A) JP-A-10-290237 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H04L 12/28 H04L 29/08

Claims (3)

(57) [Claims] 1. A physical layer circuit for performing communication conforming to IEEE 1394 having one main controller and one or more ports, comprising at least one sub controller between at least one port and the main controller. A physical layer circuit characterized by that. 2. The physical layer circuit according to claim 1, wherein the main controller and the sub-controller include at least information specific to a port directly connected to the main controller or the sub-controller. 3. The port-specific information stored in the main controller or sub-controller directly connected to each port is returned in response to access to each port from another device. 2 physical layer circuits.