JP3369043B2 - Method for manufacturing semiconductor device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device such as a capacitor element having a two-layer polysilicon structure or a nonvolatile memory having a two-layer polysilicon structure. 2. Description of the Related Art A so-called ONO (Oxide / Nitride / O / O) in which a silicon oxide film, a silicon nitride film, and a silicon oxide film are stacked as an interlayer film of two-layer polysilicon.
xide) In a method of manufacturing a semiconductor device including a capacitor element having a two-layer polysilicon structure having a composite insulating film or a semiconductor device including a nonvolatile memory having a two-layer polysilicon structure having a floating gate, a process is simplified. In many cases, the upper electrode of a two-layer polysilicon element and the gate electrode of a peripheral transistor are formed of the same layer of polysilicon. In the above-described process (hereinafter, referred to as a two-layer polysilicon process), a top oxide film of an ONO composite insulating film and a gate oxide film of a peripheral transistor are simultaneously formed by thermal oxidation. Incidentally, in the case of a nonvolatile memory, the IEEE
E Transactions on Electron
Devices Vol. 2 February 19
91, pages 386 to 391, "ONO Inter-
poly Dielectric Scaling f
or Nonvolatile Memory App
As described in “lications”, the top oxide film of the ONO composite insulating film is required to be at least 30 ° in order to secure data retention characteristics. On the other hand, with the recent miniaturization and speeding up of elements, the gate oxide film has been increasingly thinned and oxidized at low temperatures. For this reason, in the above-mentioned two-layer polysilicon process, the top oxide film on the silicon nitride film of the ONO composite insulating film formed at the same time cannot secure a sufficient film thickness.
There is a problem that the leak characteristic between the layer polysilicons is deteriorated, and the capacitance element characteristic and the data retention characteristic of the nonvolatile memory are remarkably reduced. Further, even if a top oxide film of an ONO composite insulating film having a sufficient thickness is formed in advance by thermal oxidation, and then a gate oxide film of a peripheral transistor is formed, an ONO composite insulating film is formed by a substrate cleaning process before gate oxidation. Of the ONO composite insulating film having a sufficient thickness cannot be obtained by the subsequent gate oxidation. In order to avoid the above problem, a method of forming a third layer of polysilicon which is a gate electrode of a peripheral transistor after covering the formed ONO composite insulating film with an upper electrode polysilicon of a two-layer polysilicon element. (Hereinafter, referred to as a three-layer polysilicon process). However, in the case of the three-layer polysilicon process, not only the number of manufacturing steps is increased, but also it is difficult to perform fine etching of the oxidized surface of the polysilicon film, and the two-layer polysilicon process is performed before the gate oxidation of the peripheral transistor. Even when the element is finely processed, there is a problem that the heat treatment for forming the third-layer polysilicon electrode has a bad influence on the characteristics of the already formed two-layer polysilicon element. Japanese Patent Application Laid-Open No. 6-232414 discloses a method of manufacturing a semiconductor device having an uppermost oxide film having a sufficient thickness, which is not usually performed in a semiconductor manufacturing process. A method has been proposed in which the silicon oxide film is cleaned before forming the upper electrode, and a CVD silicon oxide film is further formed on the thermal oxide film on the silicon nitride film in anticipation of the reduction in the top oxide film of ONO at that time. ing. However, in this method, it is difficult to control the thickness of the oxide film reduced by the cleaning, and it is necessary to set the CVD oxide film on the top oxide film of the ONO composite insulating film to be sufficiently thick. It is inevitable that there will be large variations within. Therefore, there is a problem in that a desired capacitance between the two-layer polysilicon cannot be obtained, or that the capacitance characteristics vary greatly. A method of manufacturing a semiconductor device including a two-layer polysilicon capacitor having a structure in which the breakdown voltage and the leakage current characteristics are not deteriorated is disclosed in Japanese Patent Application Laid-Open No. 5-291499. This method has a problem that, in a two-layer polysilicon element capacitor, an increase in the aspirity at the interface between the polysilicon and the oxide film due to the grain growth of the lower layer polysilicon deteriorates the withstand voltage and leak current characteristics of the two-layer polysilicon element capacitor. Therefore, the interlayer insulating film is formed of a nitride film and a mono-oxide film (NO structure). However, in this method, when the silicon oxide film on the silicon nitride film is formed by thermal oxidation, the interface between the lower polysilicon and the silicon nitride film is seriously affected. Therefore, a polysilicon film is formed on the silicon nitride film by CV.
D is formed thereon, and then converted into an oxide film by thermal oxidation, thereby reducing the adverse effect on the interface. As described above, in order to obtain the above-mentioned interlayer insulating film structure, the silicon nitride film cannot be thermally oxidized, and the silicon oxide film on the silicon nitride film is secondarily formed by the thermal oxidation of the polysilicon film. The polysilicon film should be as thin as possible.
The above-mentioned problem that the thickness of the top oxide film in the layer polysilicon process cannot be sufficiently obtained has not been solved. SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problems.
It is an object of the present invention to provide a method of manufacturing a semiconductor device which prevents deterioration of characteristics and reliability of a two-layer polysilicon element in a single-layer polysilicon process. According to the present invention, there is provided a method of manufacturing a semiconductor device including a two-layer polysilicon element region having a composite insulating film as an interlayer film. Forming a first conductor consisting of, patterning a desired shape, and forming a composite insulating film layer in which a silicon oxide film and a silicon nitride film are laminated on the first conductor, port on the composite insulating film layer
Forming a coercive Mamorumaku layer consisting Rishirikon layer, the area other than the two-layer polycrystalline silicon device area to form a resist pattern to be opened, the protective film layer of the region, the composite insulating layer and said first Removing the conductor, exposing the semiconductor substrate surface in the active region other than the two-layer polysilicon element region, and cleaning the exposed semiconductor substrate surface in the active region other than the two-layer polysilicon element region Forming a gate oxide film on an active region other than the two-layer polysilicon element region , and forming a gate oxide film on the composite insulating film layer
Completely protected polysilicon layer as a protective layer
A step of forming a silicon oxide film , forming a second conductor made of low-resistance polysilicon, patterning it into a desired shape, and forming an upper electrode of the two-layer polysilicon element and the two-layer polysilicon element region Forming a gate electrode of the transistor in a region other than the other region. As described above, according to the present invention, a polysilicon is used as a mask for a substrate cleaning process on an ONO composite insulating film.
The emission layer is formed as a coercive Mamorumaku, followed by performing gate oxidation of the peripheral transistors, can manufacture the semiconductor device without degrading the double-layer polycrystalline silicon device characteristics and reliability remain double-layer polycrystalline silicon process. That is, in the present invention, the top oxide film of the ONO composite insulating film can be set to a stable and desired thickness without being reduced by the protective film in the cleaning process. ONO film between two polysilicon layers
Polysilicon used as a protective film as a top oxide film
Use oxide film completely oxidized during peripheral gate oxidation
The thickness of the top layer, which cannot be obtained by thermal oxidation.
Oxide film can be realized. Therefore, between the two polysilicon layers
ONO film leakage characteristics or non-volatile memory data
Data holding characteristics can be further improved. In addition,
Reduces the time of high-temperature treatment called thermal oxidation on corn nitride film
This is advantageous for lowering the temperature of the process. Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 and FIG. 2 are sectional views for respective steps showing an embodiment when the present invention is applied to a nonvolatile memory. First, an N-well region 10 and a P-well region 11 are formed on a silicon semiconductor substrate 1 by a known method, and then a field oxide film 2 is selectively formed in an element isolation region (see FIG. 1A). ). Subsequently, the surface of the substrate 1 in the active region is exposed, and after cleaning the substrate, a gate oxide film 3 of a memory portion having a thickness of about 100 to 300 ° is formed. This gate oxide film 3
For example, it is formed by wet (WET) oxidation at a temperature of 850 to 950 ° C. (see FIG. 1B). Next, a film thickness 500 to be a floating electrode of the memory
A first polysilicon film 4 of about 3000 ° is formed on gate oxide film 2. The polysilicon film 4 is formed on the substrate by, for example, a CVD method at a temperature of 600 to 800 ° C., and is doped with impurities such as phosphorus, for example, at an acceleration voltage of 30 Ke.
V, introduced under an implantation condition of a dose amount of about 5E15, or introduced by solid-phase diffusion from a known phosphorus glass,
Lower the resistance. Further, patterning for separating floating electrodes between memories is performed (see FIG. 1C). Further, a silicon oxide film having a thickness of 100 to 300 ° is formed on the surface of the polysilicon 4 by, for example, dry (DRY) oxidation at a temperature of 850 to 1000 ° C., followed by a CVD at a temperature of 700 to 800 ° C. By law,
A silicon nitride film is formed, and this silicon nitride film is formed, for example, by WET oxidation at a temperature of 850 to 1000 ° C. to form a silicon oxide film having a thickness of 30 to 50 °, thereby forming an ONO composite insulating film 5 (FIG. d)). Next, a silicon nitride film 6 having a thickness of about 100 to 1000 ° is formed on the ONO composite insulating film 5 as a protective film layer. This silicon nitride film 6 has the same CV
Formed on the ONO composite insulating film 5 by the D method (FIG. 1)
(E)). Subsequently, a resist pattern for opening the peripheral transistor region is formed, and the silicon nitride film 6 and the ONO composite insulating film 5 formed in the peripheral transistor region by the steps shown in FIGS. 1B to 1E. Then, the first polysilicon film 4 is removed, and the surface of the semiconductor substrate 1 in the active region of the peripheral transistor region is exposed by etching the entire surface (see FIG. 2A). Then, after cleaning the substrate, a gate oxide film 7 having a thickness of about 100 to 200.degree. The gate oxide film 7 is formed by, for example, WET oxidation at a temperature of 850 to 950 ° C. (see FIG. 2B). In the cleaning process before the gate oxidation of the peripheral transistor, since the top oxide film of the ONO composite insulating film 5 is covered with the silicon nitride film 6 as a protective film, the film may be reduced or removed. Absent. Therefore, it is possible to prevent the data retention characteristic from deteriorating from that of the second polysilicon film formed on the ONO composite insulating film 5. Thereafter, a second polysilicon film 8 having a thickness of about 2,000 to 4,000 ° serving as a control electrode of the memory and a gate electrode of the peripheral transistor is formed on the entire surface of the substrate 1.
The second polysilicon film 8 has a temperature of 600 to
It is formed by a CVD method at 800 ° C., and impurities such as phosphorus are introduced by solid-phase diffusion from a known phosphorus glass to reduce the resistance (see FIG. 2C). Subsequently, the two-layer polysilicon gate of the memory portion and the gate of the peripheral transistor are finely processed by photolithography and etching twice (see FIG. 2D). Further, source and drain regions of each transistor are formed by a known method, and a semiconductor device is completed by a known wiring process. As described above, in this embodiment,
A semiconductor device that does not degrade data retention characteristics of a nonvolatile memory can be manufactured by a two-layer polysilicon process with a small number of steps. Next, an embodiment in which the present invention is applied to a semiconductor device including a two-layer polysilicon capacitor will be described. FIGS. 3 and 4 are cross-sectional views showing steps in the embodiment in which the present invention is applied to a semiconductor device including a two-layer polysilicon capacitor. First, an N-well region 10 and a P-well region 11 are formed on a silicon semiconductor substrate 1 by a known method, and then a field oxide film 2 is selectively formed in an element isolation region (see FIG. 3A). ). Subsequently, a film thickness 5 to be a lower electrode of the capacitive element
A first polysilicon film 14 of about 00-3500 ° is formed. The first polysilicon film 14 is formed on the entire surface of the substrate 1 by, for example, a CVD method at a temperature of 600 to 800 ° C., and is doped with an impurity such as phosphorus at an acceleration energy of 30 K for example.
Injection under an implantation condition of eV and a dose amount of about 5E15,
Alternatively, it is introduced by known solid-phase diffusion from phosphorus glass to lower the resistance (see FIG. 3B). Further, for example, a DLY oxidation at a temperature of 850 to 1000.degree.
A silicon oxide film of 0 to 300 ° is formed, and then a silicon nitride film is formed on the silicon oxide film by, for example, a CVD method at a temperature of 700 to 800 ° C.
Film thickness 30-50 ° by WET oxidation at 50-1000 ° C
Is formed to form an ONO composite insulating film 15 (see FIG. 3C). Next, a silicon nitride film 16 having a thickness of about 100 to 1000 ° is formed on the ONO composite insulating film 15 as a protective film.
To form This silicon nitride film 16 is formed by the same CVD method as described above (see FIG. 3D). Then, the polysilicon film 14, the ONO composite insulating film 15 and the silicon nitride film 16 formed in the steps shown in FIGS. 3B to 3D in the peripheral transistor region are removed by photolithography and etching. Then, the surface of the substrate 1 is exposed. At the same time, the polysilicon film 14 and the ONO composite insulating film 1 are formed in a desired lower electrode shape in the capacitive element region.
5 and the silicon nitride film 16 are patterned (FIG.
(A)). Subsequently, after cleaning the substrate, for example, at a temperature of 850
950 ° C. by WET oxidation, for example, a film thickness of 100 to 2
Then, a gate oxide film 17 of the peripheral transistor having a thickness of 00 ° is formed (see FIG. 4B). In the cleaning process before the gate oxidation of the peripheral transistor, since the top oxide film of the ONO composite insulating film 15 is covered with the silicon nitride film 16 as a protective film, the film may be reduced or removed. Absent. Therefore, it is possible to prevent the leak characteristic of the ONO film between the two-layer polysilicon layers of the two-layer polysilicon capacitance element from deteriorating. Next, a second polysilicon film 18 having a thickness of about 2,000 to 4,000 degrees is formed to be an upper electrode of the capacitor and a gate electrode of the peripheral transistor. The second polysilicon film 18 is formed, for example, at a temperature of 600 to 800 ° C.
, And impurities such as phosphorus are introduced by solid-phase diffusion from a known phosphorus glass to lower the resistance (see FIG. 4C). Thereafter, the upper electrode of the capacitor and the peripheral transistor gate are finely processed by photolithography and etching at the same time (see FIG. 4D). Further, source and drain regions of each transistor are formed by a known method, and a semiconductor device is completed by a known wiring process. As described above, in this embodiment,
By a two-layer polysilicon process with a small number of steps, a semiconductor device which does not deteriorate the leak current characteristics of a capacitor having a two-layer polysilicon structure can be manufactured. In the above-described embodiment, the silicon nitride films 6 and 16 are used as the protective films, but a polysilicon film may be used as the protective films. When a polysilicon film is used as the protective film, the polysilicon film is partially or entirely oxidized at the time of oxidizing the gate of the peripheral transistor. When the silicon nitride films 6 and 16 are changed to polysilicon films as the protective film, the composite insulating films 5 and 15 may have an ON structure of a silicon oxide film-silicon nitride film. The silicon oxide film formed by complete oxidation serves as an oxide film on the nitride film, that is, a so-called top oxide film, and the composite insulating film between the two-layer polysilicon finally has an ONO structure. As described above, according to the present invention, there is provided a semiconductor device including a capacitance element having a two-layer polysilicon structure having an ONO composite insulating film as a polysilicon interlayer film.
Alternatively, in a method of manufacturing a semiconductor device including a nonvolatile memory having a two-layer polysilicon structure having a floating gate, a peripheral transistor is turned on during a cleaning process before gate oxidation of a peripheral transistor.
Since the O-top oxide film is covered with the protective film, the film is not reduced or removed. Therefore, it is possible to manufacture the semiconductor device by a two-layer polysilicon process with a small number of steps without deteriorating the leak characteristics of the ONO film between the two-layer polysilicon layers of the capacitor element or the data holding characteristics of the nonvolatile memory. it can. Further, as the top oxide film of the ONO film between the two polysilicon layers, an oxide film completely oxidized at the time of peripheral gate oxidation of the polysilicon film used as the protective film is used. A top oxide film having a thickness can be realized. Therefore, ON between two polysilicon layers
The leak characteristics of the O film or the data retention characteristics of the nonvolatile memory can be further improved. Furthermore, the time for high-temperature treatment of thermal oxidation on the silicon nitride film can be reduced, which is advantageous for lowering the process temperature.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a sectional view showing each embodiment of an embodiment in which the present invention is applied to a nonvolatile memory. FIG. 2 is a cross-sectional view showing a process according to an embodiment when the present invention is applied to a nonvolatile memory. FIG. 3 is a cross-sectional view of each step showing an embodiment in which the present invention is applied to a semiconductor device including a two-layer polysilicon capacitor. FIG. 4 is a cross-sectional view showing the embodiment in which the present invention is applied to a semiconductor device including a two-layered polysilicon capacitor; [Description of Signs] 1 semiconductor substrate 2 field oxide film 4, 14 first polysilicon film 5, 15 ONO composite insulating film 6, 16 silicon nitride film (protective film) 8, 18 second polysilicon film

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/8247 H01L 27/115 H01L 29/788 H01L 29/792

Claims (1)

(1) In a method of manufacturing a semiconductor device including a two-layer polysilicon element region having a composite insulating film as an interlayer film, the insulating base is made of low-resistance polysilicon. Forming a first conductor and patterning it into a desired shape; forming a composite insulating film layer in which a silicon oxide film and a silicon nitride film are laminated on the first conductor; forming a coercive Mamorumaku layer of polysilicon layer on the insulating film layer, the area other than the two-layer polycrystalline silicon device area to form a resist pattern to be opened, the protective film layer of the region, the composite insulating film Removing the layer and the first conductor; exposing the semiconductor substrate surface of the active region other than the two-layer polysilicon element region; and exposing the active region other than the exposed two-layer polysilicon element region. A step of cleaning the semiconductor substrate surface, wherein a gate oxide film is formed double-layer polycrystalline silicon element region other than the active region, is and formed on the composite insulating film layer
Completely oxidized the polysilicon layer as a protective layer
A step of the phosphorylation film, the second conductor is formed, the upper electrode and the double-layer polycrystalline silicon device region of patterning to the double-layer polycrystalline silicon element into the desired shape made of low resistance polysilicon Forming a gate electrode of the transistor in a region other than the other region.