JP3369093B2 - Semiconductor integrated circuit design equipment - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an analog semiconductor integrated circuit designing apparatus and designing method using a master slice method.

[0002]

2. Description of the Related Art Conventionally, in order to shorten the development and manufacturing period of a semiconductor integrated circuit, a master slice method has been adopted for the layout design of the semiconductor integrated circuit. The master slice refers to a semiconductor wafer in which a resistance element, a transistor element, a capacitance element, and the like each having a predetermined element value are formed in advance. The master slice method is for each element (hereinafter referred to as a target element) in an electric circuit to be laid out in a semiconductor integrated circuit,
It is a method of designing a semiconductor integrated circuit by allocating real elements formed on a master slice and wiring between the allocated real elements on the master slice based on a connection relationship between target elements on an electric circuit. . When allocating the real element on the master slice to the target element, the real element or a combination of real elements is allocated to the target element so that the element value of the target element can be realized. Further, the region where the group of resistance elements is formed on the master slice is used as a wiring area even if the resistance element is assigned to the target element.

In designing a semiconductor integrated circuit using an actual master slice, since real elements are formed in an array on the master slice and their arrangement is predetermined, the target element to be designed is equivalent to the target element. Allocate to each area of the real element or real element combination on the master slice that realizes such a function, and connect each area of the assigned real element based on the wiring relationship of each target element on the electric circuit, Design an electric circuit.

When allocating a target element to an actual element, the element is manually assigned while taking into consideration such factors as the wiring length, the balance between elements, and the avoidance of concentration of allocation to an actual element in a certain area. There is also a method of automatically allocating elements, but as the order of allocation, one or a plurality of real elements that are equivalent to the target slice in the master slice area are provided according to the order given as information regarding the connection relationship between the target elements. , The real elements in the adjacent or linearly arranged areas are preferentially allocated and connected.

FIG. 16 shows an example of an element allocation method.

FIG. 16 shows a part of a group of real elements formed on the master slice. Each real element on the master slice forms each real element region shown by a dotted rectangle. . Reference numeral 1601 denotes a transistor element already assigned to the transistor T16a of the first target element,
Reference numeral 2 is a transistor element, which is a transistor element already assigned to the transistor T16b of the second target element, and 1603 to 1606 resistance elements.

Now, in the electric circuit, the resistor R16a is connected to one terminal of the transistor T16a,
It is assumed that the resistor R16b is connected to one terminal of 16b. According to the conventional method, when the transistor T16a is earlier than the transistor T16b in the allocation order, the resistance element 1603 located in a region near the transistor 1601 is connected to the transistor element 1601.
And 1604 are assigned (in order to realize the resistance value of the resistor R16a, a combination of 1603 and 1604 is assigned), and then the transistor element 1602.
1605 and 1606 (resistor R
A combination of resistors 1605 and 1606 is assigned to realize a resistance value of 16b). In this case, since the transistor 1601 and the resistance elements 1603 and 1604 are present between the transistor 1602 and the resistance elements 1605 and 1606, wiring processing cannot be performed and there is a possibility that wiring is not performed.

[0008]

According to the conventional method as shown in FIG. 16, the element to which the allocation process is performed later is located far away when the real element in the vicinity is already determined to be allocated. A certain real element is assigned to cause unwiring, and in the transistors arranged in a straight line, the assignment of elements to be connected is concentrated in an adjacent or nearby area. In this way, real elements are allocated from a close order in a fixed allocation order, so it is easy for the real element allocation of elements with a slower allocation order to occur, resulting in inefficient wiring as a whole, and wiring processing may be performed in some cases. However, there is a problem that the wiring is not performed.

According to the present invention, the real elements are allocated to the master slice of the electric circuit element in consideration of the connection relation between the real elements on the master slice, and the wiring distance between the real elements on the master slice is short, It is an object of the present invention to provide a semiconductor integrated circuit design device for designing a semiconductor integrated circuit having efficient wiring that does not complicate the relationship.

[0010]

In order to solve the above-mentioned problems, a semiconductor integrated circuit designing apparatus according to the present invention is arranged so that an electric circuit element whose allocation has not been determined is assigned to another electric circuit element which has not been allocated. And element allocation determining means for attempting allocation by permitting duplication of the element and element allocation determining means for determining, as a result of the processing by the element allocation means, one electric circuit element to be allocated to an actual element whose electric circuit element allocation is overlapping. It is characterized in that the processing by the element allocation determining means is repeated until the allocation of all the electric circuit elements to the actual element array is determined to be one.

With this configuration, the allocation order is not fixed, but the allocation to the actual element that can realize the most efficient wiring for the electric circuit element whose allocation is undecided is duplicated with the element whose allocation is undecided. It is possible to permit the operation, and then to adjust the duplication to determine the electric circuit element to be assigned, and to realize a semiconductor integrated circuit design device having an efficient wiring relationship.

Next, in the semiconductor integrated circuit designing apparatus, when there are a plurality of real element candidates to which the electric circuit element to be tried by the element allocating means can be allocated, an electric circuit element is connected to a terminal of the electric circuit element. Search all connected electric circuit elements as connected electric circuit elements,
The connection reference point of the real element to which the connection electric circuit element is assigned is detected, the center coordinates of a rectangle surrounding the connection reference point are calculated, and the real element at the position where the distance from the center coordinate is the shortest It is preferably an allocating means.

With such a configuration, for an electric circuit element whose allocation is undecided, a real element that can realize the most efficient wiring between the real elements to which the connecting electric circuit element connected on the electric circuit is allocated is selected. Therefore, the semiconductor integrated circuit designing device that can perform the allocation and has an efficient wiring relationship can be realized.

Next, in the semiconductor integrated circuit designing apparatus, when the element allocating means has a plurality of real element candidates to which the electric circuit element to be attempted allocation can be allocated, the terminal of the electric circuit element is connected to the electric circuit. Search all connected electric circuit elements as connected electric circuit elements,
Detecting the connection reference point of the real element to which the connection electric circuit element is assigned, calculating the center coordinates of the rectangle surrounding the connection reference point, the real element at the position where the Manhattan distance from the center coordinates is the shortest. It is preferable that it is a means for allocating to.

Here, the Manhattan distance is the total length of line segments when two points are connected only by horizontal and vertical line segments.

With this configuration, for the electric circuit elements whose allocation is undecided, the actual elements that can realize the most efficient wiring between the real elements to which the connecting electric circuit elements connected on the electric circuit are allocated are selected. Therefore, the semiconductor integrated circuit designing device that can perform the allocation and has an efficient wiring relationship can be realized.

Next, in the semiconductor integrated circuit designing apparatus, when the element allocating means allocates a plurality of real elements in combination in order to realize an element value of an electric circuit element to be attempted to be allocated, a plurality of real elements to be the combination are assigned. It is preferable that the means is assigned to a combination of real elements that minimizes the sum of Manhattan distances between the centers of the elements.

With this configuration, when assigning a combination of a plurality of real elements to realize an element value to an electric circuit element whose assignment is undecided, the wiring between the real elements to be combined is the most efficient wiring. It is possible to select and allocate a real element combination that satisfies the following, and it is possible to realize a semiconductor integrated circuit design device having an efficient wiring relationship.

Next, in the semiconductor integrated circuit designing apparatus, when the element allocating unit has a plurality of real element candidates to which an electric circuit element to be attempted to be allocated, there are other real element candidates. It is preferable that the means is a means for assigning to an actual element with little duplication of assignment of electrical circuit elements.

With such a configuration, efficient wiring can be realized for an electric circuit element whose allocation is undecided, and allocation can be performed for an actual element which has little overlap with other elements whose allocation is undecided. It is possible to realize a semiconductor integrated circuit designing device having an efficient wiring relationship by simplifying the duplication adjustment.

Next, in the semiconductor integrated circuit designing apparatus, when there are a plurality of actual element candidates to which the electric circuit element to be allocated can be allocated by the element allocation means, the terminals of the electric circuit element are arranged on the electric circuit. Search all connected electric circuit elements as connected electric circuit elements,
The connection reference point of the actual element to which the connection electric circuit element is assigned is detected, the center coordinates of a rectangle surrounding the connection reference point are calculated, and the distance from the center coordinates is set as a first parameter, and the center coordinates are set. The second parameter is the Manhattan distance from, and when a plurality of real elements are combined and allocated in order to realize the element value of the electric circuit element to be allocated, the sum of the Manhattan distances between the centers of the plurality of real elements to be combined is the sum. Is used as a third parameter, a plurality of allocation factors of other electric circuit elements with respect to the candidate of the actual element are used as a fourth parameter, and an electric circuit element to be allocated is selected by evaluation using the first to fourth parameters. Is preferred.

With this configuration, the wiring length between the actual elements to which the connecting electric circuit element is allocated, the combined actual element wiring length in the case where a plurality of actual element combinations are used to realize the element value, the overlap, etc. It is possible to perform the allocation in consideration of the plurality of allocations with the electric circuit element in a comprehensive manner, and it is possible to realize a semiconductor integrated circuit designing device having an efficient wiring relationship.

Next, in the above semiconductor integrated circuit designing device, the element allocation determining means sets a real element whose electric circuit element allocation is duplicated as a result of the allocation by the element allocation means to be a temporary allocation prohibited real element. Temporary allocation prohibiting means, duplicate electric circuit element searching means for searching for duplicate electric circuit elements allocated to the temporary allocation prohibiting real element, and the redundant electric circuit element by the element allocating means. The total of the re-allocation means that attempts re-allocation to another real element other than the allocation-prohibited real element, the real elements allocated by the re-allocation means and the detected connection reference points is the temporary allocation-prohibited real element. The provisional allocation prohibition of the electric circuit element having the maximum increment from the total distance from the element to each of the detected connection reference points Decided to assign the device, it is preferable to allocate the actual device other the overlapping electric circuit element is a means for updating the actual element allocated by the reallocation means.

With such a configuration, when adjusting the duplication of the electric circuit elements which are duplicated by the element allocating means, when the electric circuit elements are re-allocated to other actual elements, the wiring distance becomes long and the wiring becomes inefficient. Therefore, it is possible to realize a semiconductor integrated circuit design device having an efficient wiring relationship as a whole semiconductor integrated circuit.

Next, in the above semiconductor integrated circuit designing device, the element allocation determining means sets a real element whose electric circuit element allocation is duplicated as a result of the allocation by the element allocation means to be a temporary allocation prohibited real element. Temporary allocation prohibiting means, duplicate electric circuit element searching means for searching for duplicate electric circuit elements allocated to the temporary allocation prohibiting real element, and the redundant electric circuit element by the element allocating means. The sum of the Manhattan distances between the centers of the reallocation means that tries reallocation other than the real elements other than the allocation-prohibited real elements and the centers of the plurality of real elements calculated by the reallocation means is calculated by the element allocation means. Circuit with the maximum increment from the sum of Manhattan distances between the centers of multiple real elements in different combinations Decided to assign the child to the temporary assignment prohibition actual element, it is preferable to allocate the actual device other the overlapping electric circuit element is a means for updating the actual element allocated by the reallocation means.

With such a configuration, when the duplication of the electric circuit elements duplicated by the element allocating means is adjusted, the Manhattan distance of the wiring in the combination actual element is the longest and the wiring is inefficient when it is reassigned to another actual element combination. Therefore, the semiconductor integrated circuit designing apparatus can be realized, which can be allocated to the electric circuit elements that become the same, and have an efficient wiring relationship as the entire semiconductor integrated circuit.

Next, in the above semiconductor integrated circuit designing device, the element allocation determining means sets a real element whose electric circuit element allocation is duplicated as a result of the allocation by the element allocation means to be a temporary allocation prohibited real element. Temporary allocation prohibiting means, duplicate electric circuit element searching means for searching for duplicate electric circuit elements allocated to the temporary allocation prohibiting real element, and the redundant electric circuit element by the element allocating means. An electric circuit element in which the total of a plurality of re-allocation means for attempting re-allocation to the real element other than the allocation-prohibited real element and the electric circuit element assigned to the real element assigned by the re-allocation means is the largest It is decided to allocate to the temporary allocation prohibited real element, and the real element allocated to the other duplicate electric circuit element is re-allocated. It is preferably a means for updating the actual element allocated by means.

With this configuration, when adjusting the duplication of the electric circuit elements duplicated by the element allocating means, when the electric circuit elements are reassigned to other actual elements, the electric circuit elements that are most overlapped with the other electric circuit elements are the same. Therefore, it is possible to realize a semiconductor integrated circuit designing device that can be allocated to each other and has an efficient wiring relationship as a whole semiconductor integrated circuit.

Next, in the above semiconductor integrated circuit designing device, the element allocation determining means sets a real element whose electric circuit element allocation is duplicated as a result of the allocation by the element allocation means to be a temporary allocation prohibited real element. Temporary allocation prohibiting means, duplicate electric circuit element searching means for searching for duplicate electric circuit elements allocated to the temporary allocation prohibiting real element, and the redundant electric circuit element by the element allocating means. A reallocation unit that attempts reallocation to another real element other than the reallocation prohibited element, and an electric circuit element whose evaluation result calculated by the reallocation means becomes the worst from the evaluation result calculated by the element allocation unit. It is decided to allocate to the temporary allocation prohibited real element, and the real element to which the other duplicate electric circuit elements are allocated is reallocated. It is preferably a means for updating the actual element allocated by means Te.

With this configuration, when adjusting the duplication of the electric circuit elements duplicated by the element allocating means, the wiring length and the element value between the connection of the electric circuit element to be adjusted and the actual element to which the electric circuit element is allocated are realized. Therefore, the combination of multiple real elements is most efficient when re-allocated to other real elements by comprehensively considering the wiring length within the real element and the overlapping weight with other overlapping electric circuit elements. It is possible to allocate to an electric circuit element that deteriorates, and it is possible to realize a semiconductor integrated circuit design device having an efficient wiring relationship.

[0031]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a hardware configuration of a semiconductor integrated circuit designing apparatus according to an embodiment of the invention.

A semiconductor integrated circuit designing apparatus is a CAD (Computer Aided) implemented by a workstation or the like.
Design) device, and the display 101 is a CRT.
(Cathode ray tube), LCD (liquid crystal display device), etc. The input unit 102 is realized by a keyboard, a tablet, or the like. The CPU 103 is a central processing unit that controls the entire semiconductor integrated circuit device. The storage unit 104 is realized by a memory, a hard disk, or the like.

FIG. 2 is a block diagram showing a functional configuration of a semiconductor integrated circuit device which is an embodiment of the present invention.

The semiconductor integrated circuit design device comprises an element allocation section 110, an element congestion degree information addition section 111, an element allocation determination section 112, a control section 113, and a wiring section 114.

Element allocation section 110, element congestion degree information addition section 111, element allocation determination section 112, control section 11
3 and the wiring unit 114 are realized by the CPU 103 executing a program stored in the storage unit 104.

Under the control of the control unit 113, the element allocation unit 110 allocates each target element whose allocation has not been determined to an actual element on the master slice whose allocation has not been determined. At this time, even if the assignments of other target elements overlap, the duplication is allowed and the real elements on the master slice are assigned. In other words, as an initial stage, wiring between actual elements,
A region of an actual element or a combination of a plurality of actual elements that realizes each target element on the electric circuit is selected without worrying about duplication.

The element congestion degree information adding section 111 is a control section 11.
According to the instruction No. 3, the duplication number of the electric circuit element allocation candidates for the real element on each master slice is obtained as the congestion degree information of the real element, and the congestion degree information is associated with each real element on the master slice. . Specifically, information is added as the congestion degree of the element, which is a duplication number assigned with overlapping allowed, that is, a number obtained by subtracting 1 from the number of allocation destination candidates.

The element allocation determining section 112 is a control section 113.
According to the instruction of 1., the allocation target element of the real element on the master slice in which the allocation overlaps is determined. The control unit 113 controls the element allocation unit 110, the element congestion degree information addition unit 111, the element allocation determination unit 112, and the wiring unit 114 to execute the semiconductor integrated circuit design method of the present invention.

The wiring section 114 uses a wiring area secured or designated in advance on the master slice, and in the same manner as a conventional CAD device, for example, the terminal of the actual element based on the connection information of the electric circuit by the maze method or the like. Wiring such as between. Here, the maze method is a method of searching the wiring route in all directions by labeling the wiring grid in the order that ripples spread from the start point, and if there is a wiring route, be sure to find the shortest one. There is a feature that you can

The operation of the semiconductor integrated circuit designing device having the above configuration will be described.

FIG. 3 is a flow chart showing a semiconductor integrated circuit designing procedure by the semiconductor integrated circuit designing apparatus of the present invention.

The element allocation unit 110 performs initial allocation of the real element on the master slice to the target element based on the connection information of the electric circuit element (step S30).
1) Store that information.

Then, the element congestion degree information adding section 111 determines, based on the result of the element allocating section 110 and the result of updating the allocation of each real element on the master slice in the processing in the element allocation determining section 112 which will be described later. The congestion degree of each real element on the master slice is obtained from the number of overlapping destination target elements of each real element on the master slice, and is added as congestion degree information (step S3).
02).

It is judged whether or not the congestion levels of the real elements on the master slice are all 0, that is, whether or not there is duplication of allocation (step S303), and if there is duplication, step S3.
If there is no overlap, the flow proceeds to step S305.

In step S304, the element allocation determining unit 112 determines from the congestion degree added to each real element on the master slice by the element congestion degree information adding unit 111 based on the initial assignment result by the element assigning unit 110. , The real element A1 having the highest congestion degree among the real elements on the master slice is selected, and the duplicate electric circuit elements M1, ... Which are the allocation candidates of the real element A1 are selected.
Search for Mn. Next, the real element A1 is temporarily set as an allocation prohibiting element, and the element allocation unit 110 is used to try to reallocate the retrieved duplicate electric circuit elements to the real elements other than the real element A1. When this tentative reallocation is performed, the electric circuit element M1 in which the conditions of element arrangement and duplication are the worst is selected as the allocation determining element (here, M1) of the actual element A1, and duplication other than M1 is selected. The actual elements assigned to the electric circuit elements M2, ..., Mn are updated to the actual elements assigned by the reallocation, and the results are passed to the congestion degree information adding unit 111 and the process returns to step S302 (step S304).

Next, returning to step S302, step S
Based on the allocation result updated in 304, the element congestion degree information adding unit 111 sets the congestion degree of the real element A1 on the master slice for which the allocation is determined to 0, and as a result of the reallocation, the duplication of electric circuit elements is reduced. The updated congestion degree information of each actual element is updated (step S302).

It is judged whether or not the congestion levels of the real elements on the master slice are all 0, that is, whether there is duplication of allocation (step S303), and if there is duplication, step S304.
Repeat the process of.

In the case of proceeding to step S304, the process of the element allocation determining unit 112 is performed again based on the updated element congestion degree information, and the element in the electric circuit of the actual element on the master slice with the highest congestion degree. To assign to.

Steps S302 and S304 are repeated until the real elements on the master slice are no longer duplicated, and all the real elements on the master slice to the target element are determined.

When there is no overlap, the process proceeds to step S305, where the wiring section 114 performs wiring between the real elements on the master slice based on the connection information (step S30).
5).

As described above, element allocation is performed in step S301, and steps S302 to S304 are performed.
By repeating the steps up to this step, element allocation is prevented from concentrating on a specific area, allocation is performed in consideration of the wiring length and the degree of congestion of actual elements, and wiring is performed in step S305 to design the layout of the semiconductor integrated circuit. It can be done efficiently.

FIG. 4 is a flowchart showing an example of a more detailed processing procedure of element allocation by the element allocation unit 110.

The element allocation section 110 first reads the connection information between the target elements of the electric circuit (step S40).
1). It is determined whether or not there is a target element whose allocation has not been determined (step S402), and if there is an undetermined element, the process proceeds to step S403. Connection electric circuit elements N2, ..., Which are connected to the terminals of the target element N1 for executing allocation
When the real element allocation on the master slice for Nn has already been performed, the real element or the real element set B2, ..., Bn is searched (step S403).
Next, the center coordinates of the overlapping portions of the rectangles surrounding the centers of the real elements or the real element sets N2, ..., Nn on the master slice obtained in step S403 are obtained as connection reference points for allocation (step S404). Next, of the real elements that can be assigned as the target element, the real element closest to the connection reference point obtained in step S404, that is, the size of the distance between the connection reference point and the center point of the actual element to be selected The actual element (here, B1) having the smallest placement reference value indicating is selected (step S405). It is determined whether or not the real element B1 assigned in step S405 satisfies the element value of the target element (step S406). If the value is not satisfied, the connection reference point is updated to the center coordinate of the selected real element B1. (Step S407), the process returns to step S405. In step S405, the real element B1 ′ closest to the real element B1 is selected from among the real elements that can be assigned as the target element, and the element value determination in step S406 is performed again. By repeating this procedure, it is possible to select and allocate the real element on the master slice having the shortest wiring distance.

Here, the allocation reference value will be described in detail.

The allocation reference value is a reference value for allocating the target element to the real element at the optimum position when allocating the target element to the real element on the master slice, and is composed of the following three items. Items will be described with reference to the drawings.

(1) The wiring length (hereinafter referred to as "inter-element wiring length") between the target element and the connection electric circuit element connected to its terminal is obtained.

FIG. 5 is a diagram for explaining the inter-element wiring length when the target element is assigned to the actual element on the master slice.

In FIG. 5, reference numeral 501 is a resistance element group which is a real element on the master slice, 502a to 502c are resistance element groups assigned to the target element R5a, 503 is a transistor element group which is a real element on the master slice, and 5
04 is a transistor element on the master slice assigned to the transistor T5a connected to one terminal of the target element R5a, and 505 and 506 are assigned to the transistor T5b connected to the other terminal of the target element R5a. The transistor element on the master slice.
Realize the element value of. 507 is a real element 5 of the resistor 502
02a and a rectangle surrounding the center of the transistor 504, 508
Is the real element 502c of the resistor 502 and the transistor 505.
And a rectangle surrounding the center of 506.

Here, the resistance element group 502 and the transistor 5
04, a half length of the outer circumference of a rectangle 507, and a rectangle 50 surrounding the resistance element group 502 and the transistors 505 and 506.
The sum of the half length of the outer periphery of 8 is the inter-element wiring length.

(2) Since only real elements having a predetermined value are formed on the master slice, in order to realize the value of the target element, a plurality of real elements on the master slice are combined into one object. Realize the element. The wiring length between these real elements (hereinafter referred to as "element wiring length") is defined, and the real elements required for allocation are selected so as to be adjacent to each other as much as possible.

FIG. 6 is a diagram for explaining the wiring length within the element.
Reference numeral 601 is a resistance group on the master slice. 602a
˜602d are resistors assigned to satisfy the value of the target circuit element R6. The in-element wiring length of the actual element combinations 602a to 602d to which R6 is assigned is 602a.
It is defined as the sum 603 of the distances between the centers of ˜602d.

(3) The element allocation is performed by allowing the real elements on the master slice to be duplicated. However, when different target elements are already allocated to the real elements, 1 is subtracted from the total number of allocated target elements. The defined value is defined as the congestion degree indicating the duplication of actual elements. When allocating an actual element having a low congestion degree in consideration of the congestion degree when allocating elements, concentration of allocation can be prevented.

FIG. 7 is a diagram for explaining the definition of the congestion degree.
701 to 707 are assigned to the resistance elements on the master slice and the target elements T7a, T7b, and T7c in a combination surrounded by a dotted line. That is, 701 is T7a
, 702 is T7a and T7b, 703 is T7a,
704 is assigned to T7b and T7c, and 704 is assigned only to T7b. Here, the respective congestion degrees are 701 = 0, 70
2 is 1, 703 is 2, and 704 is 0.

Next, a detailed flow of the element allocation means will be described.

FIG. 8 is an explanatory diagram showing the connection reference points of the allocation determined in step S404 when the real element on the master slice is allocated to the target element, and the terminals of the target element to be allocated in step S403. 9 shows a procedure for searching for an actual element whose allocation has been determined for the connected electric circuit element connected to the node and determining the connection reference point for allocation.

In FIG. 8, 801 and 802 are real element transistor groups assigned as a combination to the transistor T8a connected to one terminal of the target element M1, 8
03, 804 and 805 are real element transistor groups assigned as a combination to the transistor T8b connected to the other terminal of the target element M1, 806 is a rectangle including the centers of the transistors 801 and 802, and 807 is transistors 803, 804 and 805. A rectangle that contains the center of the. Reference numeral 808 denotes a rectangular area connecting the rectangles 806 and 807,
Reference numeral 809 denotes the center coordinates of the rectangular area 808.

First, a rectangle 806 surrounding the centers of the assigned transistor groups 801 and 802 of the transistor T8a which is the connection electric circuit element of one terminal of the target element M1 is obtained. Next, the assigned transistor group 8 of the transistor T8b which is the connection electric circuit element of the other terminal of the target element
A rectangle surrounding the center coordinates of 03, 804, and 805 is obtained.
Next, a region 80 connecting the respective regions 806 and 807
8 is determined, and the central coordinates of the rectangular area 808 are used as the connection reference points for allocation.

Next, in FIG. 9, a real element having the smallest reference value is selected from the assigned connection reference points determined in step S404, and further, step S405 and step S405.
It is explanatory drawing which shows the result of performing allocation sequentially by giving the process of 406 and step S407.

In FIG. 9, reference numeral 909 denotes step S in FIG.
Connection reference points of allocation determined in 404, 901, 90
Reference numerals 2 and 903 denote resistive element groups on the master slice assigned to the target element. Here, if the reference value is the distance from the connection reference point 909, the actual element at the shortest position from the connection reference point 909 is selected. In this case, first 9
01 is selected. Similarly, if the reference value is the Manhattan distance from the connection reference point 909, the connection reference point 9
The actual element located at the shortest Manhattan distance from 09 is selected.

Next, when the number of allocations is not realizable with one in order to realize the value of the target element to be allocated, the connection reference point is updated from 909 to the central point of the first allocated real element 901. To do. From the updated connection reference point, that is, the center of 901, another real element having the smallest element allocation reference value is selected. In this case, the actual element 9
02 is selected, and the actual element 903 is further selected. By repeating steps S405 to S407 in this way, it is possible to assign a combination of actual elements that minimizes the in-element wiring length of the combination.

In the element allocating step S301, the processing procedure described with reference to FIGS. 5 to 9 is performed for all the target elements in the electric circuit, so that the target element is placed on any of the master slices. It can be assigned to an element. In this element allocation, the allocation of the target element to each real element on the master slice may be duplicated.

Next, FIG. 10 is a flowchart showing an example of a more detailed processing procedure of the congestion degree information addition 111 in step S302.

First, in step S1001, the allocation status of real elements on the master slice is searched based on the result of element allocation. In step S1002, it is determined whether or not there is a real element on the master slice that has not been searched, and if there is a real element that has not been searched, the process proceeds to step S1003. If there is no real element that has not been searched, the processing procedure ends.
In step S1003, the number of electric circuit elements assigned to the real element on the master slice searched in step S1001 is counted, and step S1004
In step S1003, the value obtained by subtracting 1 from the number of electric circuit elements counted is the congestion degree. Next step S1
In 005, the congestion degree obtained in step S1004 is stored in association with the actual element on the master slice.

FIG. 11 is an explanatory diagram showing an example of the congestion degree, which is basically the same as the congestion degree in the element allocation means described in FIG.

In FIG. 11, 1101 to 1106 are resistance element groups formed on the master slice, to which target elements T11a, T11b, T11c in the electric circuit are assigned. 1101 and 1102 are target elements T11a
Is assigned, T11a and T11b are assigned to 1103, T11a is assigned to 1104,
T11b and T11c are assigned, and target elements 1105 and 1106 are not assigned. The congestion degree is a value obtained by subtracting 1 from the number of target elements allocated in the real elements on the master slice as described above, and the congestion degrees of 1101 and 1102 are 0, 1103 is 1,
1104 is 2, and 1105 and 1106 have no congestion because the target element is not allocated.

After the element allocation in the initial stage is completed in the element allocation section 110, the congestion degree information addition section 111 adds the congestion degree information to all the real elements on the master slice.

Next, the element allocation determining unit 112 will be described.

FIG. 12 is a flowchart showing an example of a more detailed processing procedure for determining the allocation in step S304.

The element allocation determining unit 112 first selects the real element A1 on the master slice having a high congestion degree (step S1201). Next, when the congestion degree of the real element A1 selected in step S1201 is 0, since the congestion degree of all the real elements on the master slice is 0, the process is terminated, and the congestion degree of the real element A1 is When it is not 0, that is, when it is 1 or more, the process proceeds to step S1203 (step S1202). , Mn in the electric circuit assigned to the real element A1 are searched, and the evaluation function for these target elements is calculated (step S).
1203). The evaluation function will be described later. Next, assuming that the real element A1 is an allocation-prohibited element, step S120
The target elements M1, ..., Mn retrieved in 3 are again assigned to the actual elements on the master slice, and the evaluation function value is calculated again (step S1204). Step S1203
The evaluation function value calculated in step S1204 is compared with the evaluation function value calculated after the reallocation in step S1204, the target element having the largest deterioration in the evaluation function value is obtained, and the target element to which the real element A1 is allocated (here Then, M1 is set) (step S1205).

As a result of the step S1205, that is, the real element A1 whose allocation has been determined, the target element M1 and the target elements M2, ..., Mn whose allocation has not been determined are reassigned to obtain the congestion information of the real element A1. The congestion information of the real elements other than the real element A1 is updated to 0. (Step S
1206).

Steps S1201 to S120
When the process up to 6 is repeated and the congestion degree of all the real elements on the master slice becomes 0, it means that the allocation of the target element in the electric circuit to the master slice is completed.

Further, the detailed processing procedure of the element allocation determining section 112 will be described in detail.

FIGS. 13A to 13C are diagrams for sequentially explaining the processing procedure of the element allocation determining unit 112. Reference numerals 1301 to 1308 are a part of a resistance element group which is an actual element formed on the master slice. R13
a to R13d are target elements in the electric circuit, and
This is realized by assigning combinations of real elements on the master slice surrounded by dotted lines in (a) to (c).

In the allocation of FIG. 13A, 130
It is assumed that the allocation of the target element is 0 in 1, 1307, and 1308, and the allocation of the target element R13a in the electric circuit is already determined in 1302. Also 1303, 1
The target element R13b in the electric circuit is assigned to 304, and the target elements R13b and R13 in the electric circuit are assigned to 1305.
Three target elements of 13c and R13d are assigned, and 1306 is assigned the target element R13c in the electric circuit. As described above, in the resistance group shown in FIG. 13A, three target elements are assigned to the resistance element 1305, and the congestion degree is 2 and the congestion degree is the highest. The target element R1 assigned to this resistance element 1305,
The evaluation function value of each of R2 and R3 is calculated.

Here, the evaluation function will be described. The evaluation function has the wiring length between the target element and the actual element assigned to the connection electric circuit element, the wiring length within the combined actual element, the wiring length with the wiring assignment determining element, and the congestion degree of the assigned actual element as parameters, The values are obtained by performing necessary weighting calculations, and the results of real element allocation are digitized and used as a guide for optimization processing. Since the inter-element wiring length and the intra-element wiring length have been described above, the wiring length with the wiring allocation determining element and the target element congestion degree will be described here.

FIG. 14 is a diagram for explaining the wiring length with the wiring allocation determining element. The processing procedure for shortening the wiring length with the wiring assignment determining element is a procedure for repeating steps S405 to S407 described in FIG. In FIG. 14, 1401 and 1402 are real elements for which the allocation of the target element M1 is determined, and 1403 and 1404 are further 1401 and 140 in order to realize element values for the target element M1.
It is a real element that is a candidate to be combined with 2. As described above, since only a real element having a predetermined value is formed on the master slice, in order to realize the value of the target element, one real element on the master slice is combined with one target element. To be realized. Therefore, it is necessary to prevent the remaining elements to be further combined with 1401 and 1402, which have been assigned, from being assigned to distant real elements. Therefore, the wiring length with the actual element whose wiring allocation has already been determined is one item of the evaluation function.

Next, the degree of congestion of the target device will be described with reference to FIG.

FIG. 15 is a diagram for explaining the degree of congestion of the target element. Three target elements are assigned to the resistance real element array in an overlapping manner. Since the congestion degree of the real elements on the master slice is defined as a value obtained by subtracting 1 from the number of target elements allocated as described in FIG. 11, the resistance real elements 1503, 1502, and 1504 respectively have the congestion degrees of 0 and 1503. Has a congestion degree of 2. What is the target element congestion degree?
It is defined as the sum of the congestion degrees of the real elements on the master slice to which the target element is assigned. In other words, the high degree of congestion of the target element means that a lot of duplication occurs depending on how the target element is allocated to the real element on the master slice, and the allocation of other target elements is concentrated in the allocated real element. Means that.

Next, FIG. 13 (b) shows a result of reassigning R13b, R13c, and R13d again by temporarily disabling the resistor element 1305 on the master slice having a high congestion degree. In the result shown in FIG. 13 (b),
In R13b, the wiring length in the element is long, and the difference between the values before and after the reallocation of the evaluation function is the largest. That is, considering the efficiency of the entire circuit, it is most preferable to assign the resistance element 1305 on the master slice to the target element R13b.

FIG. 13C is a diagram in which the element for deciding the allocation of the resistance element 1305 on the master slice is R13b. The other target elements R13c and R14d are respectively assigned to real elements on the master slice different from 1305. As described above, since the number of overlapping assignments of R13c and R13d is changed by the reallocation, the congestion degree must be updated. As shown in step S1206 of FIG. 12, the information adding unit 111 performs the congestion degree updating process.

By repeating the processing described with reference to FIGS. 13A to 13C until the congestion degree of all the real elements on the master slice becomes 0, all the target elements in the electric circuit are removed. It becomes possible to allocate to the real element on the master slice without duplication.

The method of reallocating the target element to the real element on the master slice in step S1204 of the element allocation determining unit 112 shown in FIG. 12 is the same as the method used in the element allocation shown in FIG. Are the same.

The wiring section 114 completes the layout design method of the semiconductor integrated circuit by performing wiring between the actual elements on the master slice by using the maze method which is a conventional method.

As described above, according to the present embodiment, the semiconductor integrated circuit first performs the initial allocation of the target element to the real element on the master slice, and then, based on the element congestion degree information, the real degree of congestion is high. Connections are made while avoiding concentration of allocation of target elements by deciding allocation from elements by taking inter-element wiring length, intra-element wiring length, wiring length with allocation decision element, and target element congestion degree into consideration. It is possible to design an efficient layout without making the wiring length with the existing elements redundant.

In this embodiment, the evaluation function employs the sum of the inter-element wiring length, the intra-element wiring length, the wiring length with the real element for which allocation is determined, and the target element congestion degree value as the parameter of the evaluation function. Alternatively, a subset of some parameters may be used, and each item may be weighted and the evaluation item may be prioritized before the processing of the element allocation determination unit 112 is performed.

[0097]

According to the semiconductor integrated circuit designing apparatus of the present invention, electric circuit elements that allow overlapping on the real elements on the master slice are allocated, and priority is given by utilizing the congestion degree regarding the allocation of the real elements. It is possible to avoid concentration of allocation of real elements by selecting real elements whose allocation is to be determined.

Further, according to the semiconductor integrated circuit designing apparatus of the present invention, the allocation determining means reallocates the real element having the highest congestion degree as the allocation prohibiting element,
Optimal allocation becomes possible by introducing an evaluation function and determining the target element to which the actual element is allocated.

Further, according to the semiconductor integrated circuit designing apparatus of the present invention, in the allocation determining means, it is possible to prevent the wiring between the elements from becoming redundant by adding the wiring length between the elements to the evaluation item of the evaluation function. it can. Further, by adding the in-element wiring length to the evaluation item, it is possible to prevent the combined actual elements from becoming far from each other. Furthermore, by adding the congestion degree of the target element to the evaluation item, it becomes possible to more efficiently avoid the concentration of allocation of actual elements. By adding the distance to the allocation decision element to the evaluation items, even if some real elements have already been allocated to the target element, the distance from other real elements that need to be allocated does not become distant, and it is collected. It is possible to assign at different positions.

[Brief description of drawings]

FIG. 1 is a block diagram showing a hardware configuration of a semiconductor integrated circuit designing device according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a functional configuration of a semiconductor integrated circuit device according to an embodiment of the present invention.

FIG. 3 is a flowchart showing a procedure for designing a semiconductor integrated circuit by the semiconductor integrated circuit designing apparatus of the present invention.

FIG. 4 is a flowchart showing an example of a more detailed processing procedure of element allocation in step S301.

FIG. 5 is an explanatory diagram showing an example of the definition of the actual inter-element wiring length.

FIG. 6 is an explanatory diagram showing an example of the definition of the actual element wiring length.

FIG. 7 is an explanatory diagram showing an example of the definition of the actual element congestion degree.

FIG. 8 is an explanatory diagram showing an example of connection reference points for allocation in element allocation.

FIG. 9 is an explanatory diagram showing an example of element allocation from a connection reference point for allocation.

FIG. 10 is a flowchart showing an example of a more detailed processing procedure for adding actual element congestion degree information in step S302.

FIG. 11 is an explanatory diagram showing an example of an actual element congestion degree.

FIG. 12 is a flowchart showing an example of a more detailed processing procedure for determining allocation in step S304.

FIG. 13 is an explanatory diagram showing an example of reallocation of real elements.

FIG. 14 is an explanatory diagram showing an example of a wiring length with an actual element whose allocation has already been determined.

FIG. 15 is an explanatory diagram showing an example of a congestion degree of a target element.

FIG. 16 is an explanatory diagram showing an example of a conventional element allocation method.

[Explanation of symbols]

101 display 102 Input section 103 CPU 104 memory 110 element allocation unit 111 Congestion degree information addition unit 112 element allocation determining unit 113 control unit 114 wiring section

─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-3-79437 (JP, A) JP-A-6-314316 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 27/118

Claims (10)

(57) [Claims] 1. A semiconductor integrated circuit designing apparatus for designing a semiconductor integrated circuit by allocating elements in an electric circuit to be designed as a semiconductor integrated circuit to actual elements preliminarily formed on a master slice and wiring the elements. hand,
Element allocation means for allowing allocation of electric circuit elements for which allocation has not been decided yet to other electric circuit elements to the actual element array for which allocation has not been decided,
As a result of the processing by the element allocating means, an element allocation deciding means for deciding one of the electric circuit elements to be allocated to the real elements in which the allocation of the electric circuit elements is overlapped is provided, and all the electric circuit elements are allocated to the real element array. 2. The semiconductor integrated circuit designing device, wherein the processing by the element allocation determining means is repeated until 1 is determined. 2. The element allocating means, when there are a plurality of real element candidates to which an electric circuit element to be attempted to be allocated is present, all the electric circuit elements connected to the terminals of the electric circuit element on the electric circuit are selected. The connection reference point of the actual element to which the connection electric circuit element is assigned is detected, the center coordinates of the rectangle surrounding the connection reference point are calculated, and the distance from the center coordinates is the shortest. 2. The semiconductor integrated circuit design device according to claim 1, which is a means for allocating to an actual element located at the position. 3. The element assigning means, when there are a plurality of real element candidates to which an electrical circuit element to be attempted to be assigned is present, all the electrical circuit elements connected to the terminals of the electrical circuit element on the electrical circuit are selected. The connection electric circuit element is searched, the connection reference point of the actual element to which the connection electric circuit element is assigned is detected, the center coordinates of a rectangle surrounding the connection reference point are calculated, and the Manhattan distance from the center coordinates is The semiconductor integrated circuit design device according to claim 1, which is a means for allocating to an actual element located at the shortest position. 4. The element allocating means, when allocating a plurality of real elements in combination in order to realize an element value of an electric circuit element to be tried to allocate, a sum of Manhattan distances between centers of the plurality of real elements to be combined. The semiconductor integrated circuit design apparatus according to claim 1, wherein the semiconductor integrated circuit design apparatus is means for allocating to a combination of real elements that minimizes. 5. The element allocating means, when there are a plurality of real element candidates to which an electric circuit element to be tried to be allocated can be found, among the real element candidates, an allocation duplication of other electric circuit elements is small. 2. The semiconductor integrated circuit design device according to claim 1, which is means for allocating to an element. 6. The element allocating means, when there are a plurality of actual element candidates to which an electric circuit element to be tried to be allocated can be found, all the electric circuit elements connected to the terminals of the electric circuit element on the electric circuit are selected. The connection reference point of the actual element to which the connection electric circuit element is assigned is detected, the center coordinates of a rectangle surrounding the connection reference point are calculated, and the distance from the center coordinates is calculated as In the case of assigning a plurality of real elements in combination in order to realize the element value of the electric circuit element that is to be assigned, using the Manhattan distance from the center coordinate as the second parameter The third parameter is the sum of Manhattan distances between the centers of, and 4. The semiconductor integrated circuit design device according to claim 1, which is a means for selecting an electric circuit element to be assigned by evaluation using the first to fourth parameters as the fourth parameter. 7. The tentative allocation prohibiting means, wherein the element allocation deciding means sets a real element whose electric circuit element allocation is duplicated as a result of the allocation by the element allocating means to be a tentative allocation prohibiting real element, and the tentative allocation. A duplicate electric circuit element searching means for searching a duplicate electric circuit element assigned to a prohibited real element, and a duplicate electric circuit element other than the temporary assignment prohibited real element using the element assigning means. A total of distances to the reallocation means for reallocating to the elements, the real elements allocated by the reallocation means and the detected connection reference points is the connection reference detected from the temporary allocation prohibited real element. It is decided to allocate the electric circuit element having the maximum increment from the sum of the distances to the points to the temporary allocation prohibited real element, and 3. The semiconductor integrated circuit design device according to claim 2, which is means for updating another real element assigned to the duplicate electric circuit element to the real element assigned by the reassigning means. 8. The tentative allocation prohibiting means, wherein the element allocation deciding means sets a real element whose electric circuit element allocation is duplicated as a result of the allocation by the element allocating means to be a tentative allocation prohibiting real element, and the tentative allocation. A duplicate electric circuit element searching means for searching a duplicate electric circuit element assigned to a prohibited real element, and a duplicate electric circuit element other than the temporary assignment prohibited real element using the element assigning means. The total of the Manhattan distances between the reallocation means for attempting reallocation to the elements and the centers of the plurality of real elements calculated in the reallocation means is the total number of real elements in the combination calculated in the element allocation means. The electric circuit element having the maximum increment from the total Manhattan distance between the centers is assigned to the provisional allocation prohibited real element. 5. The semiconductor integrated circuit designing device according to claim 4, which is means for deciding to apply and updating the other real elements allocated to the duplicate electric circuit elements to the real elements allocated by the reallocation means. 9. The tentative allocation prohibiting means, wherein the element allocation deciding means sets a real element whose electric circuit element allocation is duplicated as a result of the allocation by the element allocating means to be a tentative allocation prohibiting real element, and the tentative allocation. A duplicate electric circuit element searching means for searching a duplicate electric circuit element assigned to a prohibited real element, and a duplicate electric circuit element other than the temporary assignment prohibited real element using the element assigning means. Assigning to the temporary assignment prohibited real element an electric circuit element having a maximum sum of a plurality of duplications of the reallocation means for reassigning the element and the real circuit element assigned by the reallocation means. And the other real elements assigned to the duplicated electric circuit elements are updated to the real elements assigned by the reassigning means. 6. The semiconductor integrated circuit design device according to claim 5, which is a means for performing the above. 10. The tentative allocation prohibiting means, wherein the element allocation deciding means sets a real element whose electric circuit element allocation is duplicated as a result of the allocation by the element allocating means to be a tentative allocation prohibiting real element, and the tentative allocation. A duplicate electric circuit element searching means for searching a duplicate electric circuit element assigned to a prohibited real element, and a duplicate electric circuit element other than the temporary assignment prohibited real element using the element assigning means. Reallocating means for attempting reallocation to the elements, and allocating an electric circuit element whose evaluation result calculated by the reallocating means becomes the worst from the evaluation result calculated by the element allocating means to the temporary allocation prohibited real element. And the other real elements assigned to the duplicate electric circuit elements are changed to the real elements assigned by the reassigning means. The semiconductor integrated circuit design device according to claim 6, which is a new means.