JP3369353B2 - Semiconductor device protection circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a protection circuit for preventing electrostatic breakdown in an output circuit of a semiconductor device having a multi-level output function.

[0002]

2. Description of the Related Art A certain type of semiconductor integrated circuit is required to have a function of supplying a plurality of voltage level signals to an integrated circuit device at a next stage or a device to be driven. This technology is a dedicated IC that drives various display devices such as liquid crystal panels.
This is an indispensable technique for a microcomputer with a built-in driver, which performs (Integrated Circuit) or arithmetic processing of an input signal and outputs a control signal to another integrated circuit device and at the same time drives a display device.

As a method of realizing the function of supplying a plurality of voltage level signals to the integrated circuit device of the next stage and a device to be driven, the drains of a plurality of transistors whose sources are connected to different levels are drawn to the outside. A method is commonly used in which all the transistors whose sources are connected to a desired level are turned on and the other transistors are turned off, which are commonly connected to the output terminals, that is, connected in parallel. At this time, the level of the substrate on which the individual transistors having different source levels are formed is constant regardless of the source level, and the level of the well in which the transistors of the opposite type are formed is also constant regardless of the source level. Often used as. That is, in the output circuit of the semiconductor device that realizes the function of supplying a plurality of voltage level signals to the next-stage integrated circuit device or the device to be driven, the source and substrate of the transistor and the electrode of the source and the well are separated and It operates by supplying different potentials.

On the other hand, in a circuit for supplying a single voltage level signal which is conventionally provided in more output circuits of semiconductor devices, the potential levels of the source and the substrate of the transistor and the potential level of the source and the well are set. Since it is not necessary to separate them, an electric potential is supplied from one electrode to the source and the substrate, and the source and the well to operate.

[0005]

However, in these two types of transistors, a transistor in which a source and a substrate and a source and a well electrode are separated has a problem in that the electrostatic breakdown resistance is lower than that in a transistor which is not divided. ing. NMOS (N type Metal Oxid
The reason will be described below by taking an eSemiconductor) output circuit as an example.

FIG. 12 is a diagram showing a conventional single-level NMOS output circuit, and FIG. 13 is a diagram showing a multi-level (hereinafter referred to as multi-level) NMOS output circuit (two-level output for simplicity). is there.

As shown in FIG. 12, in a single-level output circuit, an NMOS connected to an electrode connected to a supply level is used.
Output transistor (hereinafter, simply output transistor) 10
The source (N +) of 1 and the substrate or well (P−) in which the output transistor 101 is formed are commonly connected. In FIG. 12, reference numeral 102 denotes a bonding pad provided to be drawn as an external terminal connected to the drain of the output transistor 101, and 103 is provided to be drawn as an external terminal connected to the source and well of the output transistor 101. It is a bonding pad.

On the other hand, in the multi-level output circuit, as shown in FIG. 13, the first source (N +) 105 of the first output transistor 104 is connected to the electrode connected to the first supply level, The second source (N +) 107 of the second output transistor 106 is connected to the electrode connected to the second supply level. Further, the first output transistor 10
4 and the second output transistor 106 are both formed on the substrate or the bonding pad 109 connected to the well (P−) in order to operate the first output transistor 104 and the second output transistor 106. It is connected to the third supply level that does not cause any trouble or the electrode that does not cause any trouble in the first or second supply level.
Reference numeral 108 is a bonding pad.

That is, when the substrate or well is connected to the third supply level, the source of both the first and second output transistors and the substrate or well are separated,
When the substrate or the well is connected to the electrode that does not cause any trouble in the first or second level, the source of the transistor that is not connected and the substrate or the well are separated. In any case, in at least one transistor, it is inevitable that the source and the electrode of the substrate or well are separated.

The characteristics of the transistor when the source and the substrate or well are common or when they are separated will be described below.

A bipolar transistor having a drain as a collector, a substrate or a well as a base, and a source as an emitter is parasitically formed in each output transistor of FIGS. 12 and 13. That is, in the case of FIG. 12 in which the source and the substrate or the well are common, an npn bipolar transistor in which the emitter and the base are short-circuited (hereinafter referred to as the emitter-base short-circuit) is formed.

On the other hand, in the case of FIG. 13 in which the source is separated from the substrate or well, either the base or the emitter is open with respect to the collector. The problem with electrostatic breakdown is when an electrostatic surge is applied between the drain connected to the output pin and the source that is externally supplied as a voltage level, which corresponds to the open base state. An npn bipolar transistor (hereinafter referred to as base open) is formed.

FIG. 14 schematically shows the relationship between the collector voltage and the collector current of the npn bipolar transistor under each of the base open condition and the emitter-base short condition.

By increasing the collector voltage to the positive side,
When a certain voltage is exceeded, a breakdown phenomenon occurs. BVceo is the breakdown voltage when the base is open, and BVces is the breakdown voltage when the emitter-base is short-circuited.
A tendency of ceo <BVces is shown. Further, as the collector voltage is increased, the base potential is also increased by the breakdown current, and the emitter-base is forward biased, so that the base current flows between the base-emitter.

As a result, a collector current also flows between the collector and the emitter. When the collector current flows, the collector voltage drops to the holding voltage all at once. Although the value of this holding voltage differs for each npn bipolar transistor, comparing the same transistor when the base is open and when the emitter-base is shorted, the holding voltage when the base is open is the one when the emitter-base is shorted. It will be lower than the voltage.

Therefore, under the condition that the collector voltage is constant, the collector current (represented by Iceo) when the base is open,
Collector current (Ice when short-circuited between emitter and base)
(represented by s), Iceo> Ices. This relation of Iceo> Ices is the reason why the electrostatic breakdown resistance of the multi-level output circuit becomes lower than that of the single-level output circuit.

That is, when an electrostatic surge is applied to the output terminal, the surge current is absorbed from the drain of the transistor to the source via the substrate or well. At this time, the surge current is absorbed not as the channel current of the MOS transistor but as the collector current of the parasitically formed bipolar transistor. That is, in a multi-level output circuit, the surge current suddenly flows from the drain to the source as a collector current Iceo when the base is open, and in a single-level output circuit, the emitter-
It is absorbed by the source as a collector current Ices when the bases are short-circuited, and as a result, the electrostatic breakdown resistance of the multi-level output circuit becomes lower than that of the single-level output circuit.

In the multi-level output circuit, BVceo <
Due to the relationship of BVces, there is also a problem that the protection circuit is difficult to function. This will be described next.

FIG. 15 is a protection circuit diagram having a conventional NMOS.

As a general method for protecting not only the multi-level output circuit but also the output circuit, a method of connecting the protection transistor 112 as shown in FIG. 15 in parallel with the output transistor 111 is used.

As the protection transistor 112, a transistor whose source and substrate or well are connected to a common electrode and whose gate is fixed so that it is always off is used. The bipolar transistor parasitic on the protection transistor 112 is a short type between base and emitter,
The breakdown voltage is BVces.

Even if this is used for protection of the multi-level output transistor, the breakdown voltage Vceo of the multi-level output transistor 111 is lower than BVces, so that the output transistor 111 on the protected side is protected before the protection transistor 112. Will surrender. Further, regarding the collector current after breakdown, the collector current Iceo of the output transistor 111 is larger than the collector current Ices of the protection transistor 112, so that the output side is easily destroyed, in other words, the protection circuit is hard to function.

In FIG. 15, reference numerals 113, 114 and 115 are bonding pads provided for drawing out as external terminals.

As described above, the semiconductor device having the multi-level output circuit has a lower resistance to electrostatic discharge damage than the semiconductor device having only the single-level output circuit. There are two problems that the protection circuit does not function effectively. In order to give the same destruction resistance as the conventional one, it is unavoidable to increase the protection circuit occupation area by newly installing a dedicated protection circuit. As a result, there was a problem that the unit price of chips increased.

According to the present invention, in a static electricity protection circuit for a semiconductor device having a multi-level output circuit, against the deterioration of the electrostatic breakdown resistance due to the breakdown voltage of the output circuit being lower than the breakdown voltage of the protection circuit, It is an object of the present invention to provide a protection circuit for a semiconductor device excellent in electrostatic discharge resistance, which realizes the electrostatic discharge resistance equal to or higher than that of the above, while suppressing an increase in the protection circuit area without changing the manufacturing process. .

[0026]

In order to achieve the above-mentioned object, the present invention provides: (1) a semiconductor device having an output transistor in an output circuit in which a supply potential to a substrate or a well and a supply potential to a source are different from each other, In a protection circuit for a semiconductor device having a substrate or a well and a protection transistor whose source is connected to the same node, a breakdown voltage BVces at the time of a base-emitter short circuit on the protection transistor side of a breakdown voltage BVceo of the output transistor in a base open state. And the protection transistor side is broken down first against the electrostatic surge to protect the output transistor.

[0027] (2) in the protective circuit of the (1) Symbol mounting of the semiconductor device, and darker well concentration of said protective transistor, in which so as to reduce the well concentration of said output transistor.

( 3 ) A semiconductor device having, in an output circuit, an output transistor having different supply potentials to a substrate or a well and a source, and a first protection transistor in which the substrate or the well and the source are connected to the same node. , The output
A second transistor connected between the source of the transistor and the well
In a protection circuit for a semiconductor device having a protection transistor, a source, a well and a well of the second protection transistor are provided.
Gate is connected to the well of the output transistor.
Together with the drain of the second protection transistor
The first protection connected to the source of the output transistor
Breakdown voltage of transistor and second protection transistor
As the sum threshold voltage of becomes lower than the breakdown voltage of the output transistor data is obtained by so as to respond to the protection circuit above.

[0029] (4) in the protection circuit above SL (3) The semiconductor device according, the source and the well及of the first protection transistor through the well resistance of said output transistor
And the gate is connected to the node to which it is connected.

(5) In the protection circuit for a semiconductor device described in (1) above, the protection circuit side is formed of one-stage transistors and the output circuit side is formed of two or more stages of transistors.

(6) In the protection circuit for a semiconductor device described in ( 3 ) above, the protection circuit side is formed by two stages of transistors and the output circuit side is formed by two or more stages of transistors.

(7) In the protection circuit for a semiconductor device according to the above (5) or (6), the gates of the respective transistors on the output circuit side, which are composed of two or more stages of transistors, are electrically connected to a common signal line. It is designed to be connected.

(8) In the protection circuit for a semiconductor device according to the above (5) or (6), among the transistors on the output circuit side composed of the transistors of two or more stages, the first transistor seen from the drain side is Except for this, the gates of the transistors from the second stage to the final stage are electrically connected to a common signal line that supplies a gate level at which the transistors are always on.

(9) In the protection circuit for a semiconductor device according to (5), (6), (7) or (8) above, the protection circuit is provided on a substrate to form two or more stages of transistors on the output circuit side. The well region to be formed is separately produced for each transistor.

(10) In the semiconductor device protection circuit described in (9), a series resistance is added to each well in which two or more stages of transistors on the output circuit side are formed.

[0036]

(A) According to the semiconductor device (see FIG. 1), the well concentration of the protection transistor is increased to lower the breakdown voltage.
BVces <BVceo was established by decreasing the well concentration of the output transistor and increasing the breakdown voltage. That is, the electrostatic surge current does not flow as the collector current Iceo of the parasitic transistor of the output transistor, but the collector current Ices of the parasitic transistor of the protection transistor and the parasitic p of the output transistor p.
Since an n-junction diode current can be passed to the source of the output transistor, good electrostatic breakdown resistance can be obtained.

In particular, in a manufacturing process using two or more kinds of wells having different concentrations, there is an advantage that it is not necessary to add a manufacturing step and can be realized only by changing the setting condition of the well concentration.

(B) According to the semiconductor device (see FIG. 2),
Since the second protection transistor is newly added to the semiconductor device described in (A) above, the electrostatic surge current does not flow as the collector current Iceo of the parasitic transistor of the output transistor, and the parasitic transistor of the first protection transistor does not flow. Since the collector current Ices and the channel current of the second protection transistor can be made to flow to the source of the output transistor, good electrostatic breakdown resistance can be obtained.

In particular, since the effect of the parasitic pn junction diode of the output transistor of the semiconductor device described in (A) above is replaced by the second protection transistor, it is not affected by the characteristics of the pn junction diode of the output transistor. There is an advantage that the setting conditions of the well density of the protection transistor and the output transistor can be widely changed.

Further, in order to increase the number of parasitic pn junction diodes, it is possible to eliminate the disadvantage of the pattern area such that the output transistor area is intentionally increased when sufficient circuit characteristics are obtained even with an output transistor having a small pattern area. it can.

(C) According to the semiconductor device (see FIG. 3),
A series resistor is newly added to the well in which the output transistor is formed in the semiconductor device described in (B) above. That is, since the node where the source of the first protection transistor is connected to the well and the gate are connected to the well of the output transistor through the resistor, the surge that flows as the collector current Ices of the first protection transistor. The effect of current flowing into the well of the output transistor can be suppressed, and the effect of current flowing into the source of the second protection transistor can be enhanced.

Therefore, the setting conditions of the well density of the protection transistor and the output transistor can be changed more widely than in the semiconductor device described in (B) above.

(D) According to the semiconductor device (see FIG. 4),
Since the protection circuit side is made up of one-stage transistors and the output circuit side is made up of two or more stages of transistors,
Without passing the electrostatic surge current as the collector current Iceo of the parasitic transistor of the first output transistor,
Collector current I of parasitic transistor of protection transistor
ces and a parasitic pn junction diode current of the output transistor (a current flowing through a forward biased pn junction diode is referred to as a diode current) is passed to the source of the output transistor, so that good electrostatic breakdown resistance can be obtained.

In particular, in a manufacturing process using a single well, there is an advantage that it can be realized only by circuit design without adding a manufacturing process.

(E) According to the semiconductor device (see FIG. 5),
A second protection transistor is newly added to the semiconductor device described in (D) above. That is, the drain of the second protection transistor is electrically connected to the source of the second output transistor, and the source, the well, and the gate of the second protection transistor have a common node with the wells of the first and second output transistors. Connected to. By connecting in this way, a protection circuit is constituted by the first protection transistor and the second protection transistor.

Therefore, the electrostatic surge current is converted into the collector current Ic of the parasitic transistor of the first output transistor.
Without flowing as eo, the collector current Ices of the parasitic transistor of the first protection transistor and the channel current of the second protection transistor (the source-drain of the transistor through the channel formed in the MOS transistor in the ON state Since a current that flows is referred to as a channel current) is supplied to the source of the output transistor, good electrostatic breakdown resistance can be obtained.

In particular, the second semiconductor device described in (D) above.
Since the effect of the parasitic pn junction diode of the output transistor of is replaced by the second protection transistor, it is not affected by the characteristics of the pn junction diode of the second output transistor, and the pattern is increased in order to increase the parasitic pn junction diode. When sufficient circuit characteristics are obtained even with an output transistor having a small area, it is possible to eliminate the disadvantage of increasing the area of the output transistor in terms of pattern area.

(F) According to the semiconductor device (see FIG. 6),
The gates of the first output transistor and the second output transistor in the semiconductor device described in (D) or (E) are electrically connected to a common signal line from the inside. Since the output transistor composed of two or more stages can be controlled by one control signal, the control circuit can be simplified.

(G) According to the semiconductor device (see FIG. 7),
Of the gates of the first output transistor and the second output transistor in the semiconductor device according to (D) or (E), all the gates except the first-stage gate (in this example, the gate of the second output transistor) ) Is electrically connected to a common signal line that supplies a gate level at which the transistor is always on. Then, since only the first stage is used as a switch and the second and subsequent stages are in the ON state, a predetermined voltage level is always supplied to the source of the first stage, so that the signal transmission delay can be reduced. Further, since the control signal is controlled to the ON state by one control signal, the control circuit is simple.

(H) According to the semiconductor device (see FIG. 8),
In the four semiconductor devices described in (D) to (G) above, well regions provided on the substrate for forming two or more stages of transistors on the output circuit side are formed separately for each transistor. Since the well in which the output transistor is formed is separated in this way, the layout can be facilitated.

Particularly, since the wells are only separated, there is an advantage that it can be realized only by circuit design without adding a manufacturing process.

(I) According to the semiconductor device (see FIG. 11), the semiconductor device described in (H) above is used (E).
Therefore, in the semiconductor device of (G) above, a series resistance is added to each well in which the first output transistor and the second output transistor are formed.

Therefore, the surge current flowing as the collector current Ices of the protection transistor flows into each well of the first output transistor and the second output transistor, and further the forward current of the parasitic pn junction, that is, the parasitic bipolar transistor. Q2 and Q
4 (see FIG. 9) as a base current. When a base current flows through the parasitic bipolar transistors Q2 and Q4 and both are turned on, a through current flows from the drain of the first output transistor to the source of the second output transistor. This current will destroy the output transistor.

Therefore, a collector current Ices of the protection transistor is connected by connecting a resistor to each of them in series.
It is possible to suppress the effect that the surge current that flows into the wells of the first output transistor and the second output transistor is suppressed, and it is possible to enhance the effect of flowing into the source of the second protection transistor.

Therefore, the protection effect can be further enhanced as compared with the case of the semiconductor device described in (H) above alone.

[0056]

Embodiments of the present invention will be described below with reference to the drawings.

In the following description, an NMOS will be described as an example. Unless otherwise specified, both the output transistor and the protection transistor are NMOS transistors, and the parasitic bipolar transistor means an npn bipolar transistor.

FIG. 1 is a block diagram of a semiconductor device showing a first embodiment of the present invention.

As shown in this figure, the well concentration of the NMOS protection transistor (hereinafter simply referred to as protection transistor) 1 is increased to lower the breakdown voltage, and the well concentration of the NMOS output transistor (hereinafter simply referred to as output transistor) 2 is reduced. The breakdown voltage BVceo when the base of the output transistor 2 is open is reduced by a method of thinning the breakdown voltage and increasing the breakdown voltage.
In this example, the breakdown voltage BVces at the time of short circuit between the base and emitter of the protection transistor 1 side is lowered, and the protection transistor 1 side is broken down first against the electrostatic surge.

The source 11, the well 12 and the gate 13 of the protection transistor 1 correspond to the well 2 of the output transistor 2.
Connect to 2. In this figure, 8 is a bonding pad connected to the source, 21 is the source of the output transistor 2, and 23 is the gate of the output transistor 2.

In FIG. 1, the drain 14 of the protection transistor 1 and the drain 24 of the output transistor 2 are both electrically connected to a bonding pad 6 provided for drawing out as an external terminal. Protection transistor 1
The source 11, the well 12 and the gate 13 are connected to a node common to the well 22 of the output transistor 2, and this node is also electrically connected to the bonding pad 7 provided for drawing out as an external terminal.

The source 21 of the output transistor 2 is electrically connected to the bonding pad 8, and the gate 23
Is connected to the signal line of the internal circuit. Sauce 11
By commonly connecting the well 12 and the gate 13 to each other, the breakdown voltage of the parasitic transistor of the protection transistor 1 becomes BVces, and the collector current after breakdown also becomes Ices.
Becomes Source 21 and well 2 on the output transistor 2 side
Since 2 is isolated, the breakdown voltage is BVceo and the collector current is Iceo.

In this circuit, the well in which the protection transistor 1 is formed is set to a high concentration and the breakdown voltage is B
The well in which Vces is reduced and the output transistor 2 is formed is set to a low concentration, and the breakdown voltage BVce is set.
By increasing o, the relationship of BVces <BVceo is satisfied. When a positive electrostatic surge is applied to the bonding pad 6, BVces <BVceo, so that the protection transistor 1 breaks down first and the collector current Ice.
s flows to the source 11 of the protection transistor 1. This collector current is Ices means that the protection transistor 1
It also has the effect of not being destroyed. The source 11 of the protection transistor 1 is the well 22 of the output transistor 2.
Since it is electrically connected to the collector current Ices
Also flows into the well 22 of the output transistor 2.

Here, the well 22 of the output transistor 2
And the source 21, the well 22 side is the anode, the source 2
A pn junction diode having the cathode on the 1 side is parasitically formed, and the collector current of the positive electrode flowing from the protection transistor 1 forward biases the pn junction diode. A surge current also flows into the well 21 from the well 22.

As described above, in the circuit of this embodiment, the electrostatic surge current does not flow as the collector current Iceo of the parasitic transistor of the output transistor 2,
Collector current I of parasitic transistor of protection transistor
ces and the diode current of the parasitic pn junction of the output transistor 2 flow to the source of the output transistor,
Good electrostatic breakdown resistance is obtained.

In particular, this embodiment has an advantage that in a manufacturing process using two or more types of wells having different concentrations, it is not necessary to add a manufacturing step and can be realized only by changing the well concentration setting condition. .

FIG. 2 is a block diagram of a semiconductor device showing a second embodiment of the present invention. The same parts as those in the above embodiment are designated by the same reference numerals, and the description thereof will be omitted.

This embodiment is a development of the first embodiment, in which a protection transistor (second protection transistor) 3 is added between the source 21 and the well 22 of the output transistor 2, and the protection transistor (first protection transistor) is added. Protection transistor)
1 and the protection transistor 3 form a protection circuit.

In addition, the source 31 of the protection transistor 3,
The well 32 and the gate 33 are connected to the well 22 of the output transistor 2, and the drain 34 is connected to the source 21 of the output transistor 2. Breakdown voltage BVceo of output transistor 2 and breakdown voltage BV of protection transistor 1
ces and the threshold voltage Vth of the protection transistor 3 are BV
The well concentrations of the output transistor 2 and the protection transistor 1 are set so as to satisfy the relationship of ceo> BVces + Vth. In FIG. 2, 34 is the drain of the protection transistor 3.

As described above, in this embodiment, a protection transistor is newly added to the first embodiment. That is, in FIG. 2, the drain 34 of the protection transistor 3 is
Is electrically connected to the source 21 of the output transistor 2,
The source 31, the well 32, and the gate 33 of the protection transistor 3 are connected to a common node with the well 22 of the output transistor 2. By connecting like this,
The protection transistor 1 and the protection transistor 3 form a protection circuit.

With this structure, the protection transistor 1 has the source 11 and the well 1 as in the first embodiment.
Since 2 and the gate 13 are commonly connected, the breakdown voltage of the parasitic transistor is BVces, and the collector current after breakdown is Ices. Similarly, on the output transistor side, since the source 21 and the well 22 are separated, the breakdown voltage is BVceo and the collector current is Iceo.
Is.

In this embodiment, the breakdown voltage BVces of the protection transistor 1, the breakdown voltage BVceo of the output transistor 2, and the threshold voltage Vth of the protection transistor 3 satisfy BVces + Vth <BVceo. When a positive electrostatic surge is applied to the bonding pad 6, BVces <BVceo (Vth
> 0), the protection transistor 1 breaks down first, and the collector current Ices flows to the source 11 of the protection transistor 1.

Needless to say, the fact that the collector current is Ices also has the effect of not destroying the protective transistor 1 itself. The source 11 of the protection transistor 1 is also connected to the well 22 of the output transistor 2, but the source 31 and the well 3 of the protection transistor 3 are connected.
2 and the gate 33 will also be connected. By being connected to the protection transistor 3, the collector current I
ces is the output transistor 2 unlike the first embodiment.
Of the protection transistor 3 rather than flowing into the well 22 of the protection transistor 3.

Since the source 31, the well 32 and the gate 33 of the protection transistor 3 are connected in common, the channel current flows between the source 31 and the drain 34 in the ON state at the positive threshold voltage. Since the collector current flowing from the protection transistor 1 is a positive electrode and turns on the protection transistor 3, a surge current can be flown into the source 21 of the output transistor 2 as a channel current.

As described above, in the circuit of this embodiment, the electrostatic surge current does not flow as the collector current Iceo of the parasitic transistor of the output transistor 2,
Since the collector current Ices of the parasitic transistor of the protection transistor 1 and the channel current of the protection transistor 3 are passed to the source 21 of the output transistor 2, good electrostatic breakdown resistance can be obtained.

In particular, in this embodiment, the effect of the parasitic pn junction diode of the output transistor 2 used in the first embodiment is replaced by the protection transistor 3, so that it is affected by the characteristics of the pn junction diode of the output transistor 2. There is an advantage that the setting conditions of the well concentration of the protection transistor 3 and the output transistor 2 can be widely changed. Further, in order to increase the number of parasitic pn junction diodes, when sufficient circuit characteristics are obtained even with the output transistor 2 having a small pattern area, the disadvantage of the pattern area such as intentionally increasing the area of the output transistor 2 can be eliminated. it can.

FIG. 3 is a block diagram of a semiconductor device showing a third embodiment of the present invention. The same parts as those in the above embodiment are designated by the same reference numerals, and the description thereof will be omitted.

This embodiment is a development of the second embodiment, and a resistor 25 is added to the well 22 in which the output transistor 2 is formed.

In this embodiment, a resistor 25 is newly added to the well 22 in which the output transistor 2 in the second embodiment is formed. That is, in FIG. 3, the source 11 of the protection transistor (first protection transistor) 1
The node to which the well 12 and the gate 13 are connected, and the well 22 of the output transistor 2 are connected via the resistor 25.

By connecting the resistor 25 in series, the surge current flowing as the collector current Ices of the protection transistor 1 is suppressed from flowing into the well 22 of the output transistor 2 and the protection transistor (second protection transistor) 3 is protected. The effect of flowing into the source 31 can be enhanced. Therefore, the setting conditions of the well concentrations of the protection transistor and the output transistor can be changed more widely than in the second embodiment.

In this embodiment, the larger the resistance 25 is, the greater the effect is. Therefore, since the well resistance having originally high resistivity can be used as it is, the area of the output transistor is increased to add the resistance. There is no area disadvantage.

FIG. 4 is a block diagram of a semiconductor device showing a fourth embodiment of the present invention. The same parts as those in the above embodiment are designated by the same reference numerals, and the description thereof will be omitted.

In this embodiment, the protection circuit side is composed of one transistor stage, and the output circuit side is composed of two or more transistor stages, so that BVces <BVce of the present invention.
This is an example of performing o. For example, the protection transistor 1 has one stage, and the output transistor 2 is further connected with an output transistor (second output transistor) 4 in series.

In this embodiment, BVceo is the breakdown voltage between the drain of the first stage and the source of the final stage, and the source of the nth stage output transistor and the drain of the (n + 1) th stage output transistor are sequentially connected. The source 11, the well 12 and the gate 13 of the protection transistor 1 are connected to the common wells 22 and 42 in which the output transistor (first output transistor) 2 and the output transistor (second output transistor) 4 are formed. 41 is the source of the output transistor 4, 42 is the well of the output transistor 4,
Reference numeral 43 is a gate of the output transistor 4, and 44 is a drain of the output transistor 4.

In this embodiment, the protection circuit side is formed of one-stage transistors and the output circuit side is formed of two or more stages of transistors. Here, an example in which the output circuit side is composed of two stages of transistors will be described. First, the protection circuit side will be described.

In FIG. 4, the drain 14 of the protection transistor 1 is electrically connected to the bonding pad 6 provided as an external terminal, and the source 11, the well 12, and the gate 13 are also provided as external terminals. Is electrically connected to the bonding pad 7.

On the other hand, of the two output transistors, the drain 24 of the output transistor (first output transistor) 2 is electrically connected to the bonding pad 6, the gate 23 is connected to the signal line of the internal circuit, and the source is connected. Two
1 is connected to the drain 44 of the output transistor (second output transistor) 4, the source 41 of the output transistor 4 is electrically connected to the bonding pad 8 provided for drawing out as an external terminal, and the gate 43 is an internal circuit. Wells 22 and 42 of the output transistors 2 and 4 are both connected to the signal line of the bonding pad 7
Electrically connected to.

In this circuit, the breakdown voltage of the parasitic transistor of the protection transistor 1 is BVces, and the collector current after breakdown is Ices as in the previous embodiment. Since the sources and wells of the output transistors 2 and 4, that is, the source 21 and the well 22 and the source 41 and the well 42, are isolated from each other, the breakdown voltage is BVceo and the collector current is Iceo.

By the way, the breakdown voltage on the output circuit side is the drain 24 of the first stage transistor and the final stage (here, 2).
Since it is the breakdown voltage between the sources 41 of the transistors in the (stage), the output in this circuit is double that in the case where the output is configured in one stage.

In this embodiment, the number of stages on the output circuit side is set to BVc.
It is set to es <(BVceo = BVceo × stage number). When a positive electrostatic surge is applied to the bonding pad 6, BVces <BVceo ′, so that the protection transistor 1 breaks down first. The surge current flows as the collector current Ices of the protection transistor 1 into the well 42 of the output transistor 4 and finally into the source 41 via the parasitic pn junction diode of the output transistor 4.

As described above, in the circuit of this embodiment, the electrostatic surge current does not flow as the collector current Iceo of the parasitic transistor of the output transistor 2,
Since the collector current Ices of the parasitic transistor of the protection transistor 1 and the diode current of the parasitic pn junction of the output transistor 1 are made to flow to the source of the output transistor 4, good electrostatic breakdown resistance can be obtained.

In particular, this embodiment has an advantage that it can be realized only by circuit design in a manufacturing process using a single well without adding manufacturing steps.

FIG. 5 is a block diagram of a semiconductor device showing a fifth embodiment of the present invention. The same parts as those in the above embodiment are designated by the same reference numerals, and the description thereof will be omitted.

This embodiment is a development of the fourth embodiment, and a protection transistor (second transistor) is provided between the source 41 and the well 42 of the output transistor (second output transistor) 4 at the final stage as seen from the drain side. Protection transistor) 3 is added, and the protection transistor (first protection transistor) is added.
1 and the protection transistor 3 form a protection circuit.

The source 31, the well 32 and the gate 33 of the protection transistor 3 are connected to the well 42 of the output transistor (second output transistor) 4 and the drain 3
4 is connected to the source 41 of the output transistor 4. The entire breakdown voltage BVce from the first output transistor 2 to the final output transistor 4 when viewed from the drain 34 side.
o and the breakdown voltage BVces of the protection transistor 1 and the threshold voltage Vth of the protection transistor 3 are BVceo> BVc
The number of output transistor stages is set so as to satisfy the relationship of es + Vth.

In this embodiment, a protection transistor 3 is newly added to the fourth embodiment. That is, in FIG.
The drain 34 of the protection transistor 3 is electrically connected to the source 41 of the output transistor 4,
Source 31, well 32, and gate 33 are connected to a common node with wells 22 and 42 of output transistors 2 and 4. With such connection, the protection transistor 1 and the protection transistor 3 form a protection circuit.

In this embodiment, the breakdown voltage BVces of the protection transistor 1 and the output transistors 2 and 4 are set.
Of the total breakdown voltage BVceo ′ and the threshold voltage Vth of the protection transistor 3 is BVces + Vt.
h <BVceo '. The effect of this protection circuit is similar to that of the second embodiment, and by being connected to the protection transistor 3, the collector current Ices flows into the source 31 of the protection transistor 3 rather than into the well 42 of the output transistor 4. .

Since the source 31, the well 32 and the gate 33 of the protection transistor 3 are commonly connected, the source 31 and the drain 34 are turned on by the positive threshold voltage.
This is because the channel current flows between them. The positive collector current flowing from the protection transistor 1 turns on the protection transistor 3 and a surge current can flow into the source 41 of the output transistor 4 as a channel current.

As described above, in the circuit of this embodiment, the electrostatic surge current does not flow as the collector current Iceo of the parasitic transistor of the output transistor 2,
Since the collector current Ices of the parasitic transistor of the protection transistor 1 and the channel current of the protection transistor 3 flow to the source of the output transistor, good electrostatic breakdown resistance can be obtained.

Particularly, in this embodiment, since the effect of the parasitic pn junction diode of the output transistor 4 used in the fourth embodiment is replaced by the protection transistor 3, it is affected by the characteristics of the pn junction diode of the output transistor 4. In order to increase the number of parasitic pn junction diodes, it is possible to eliminate the pattern area demerit that the output transistor area is intentionally increased when sufficient circuit characteristics are obtained even with an output transistor having a small pattern area. .

FIG. 6 is a block diagram of a semiconductor device showing a sixth embodiment of the present invention. The same parts as those in the above embodiment are designated by the same reference numerals, and the description thereof will be omitted.

This embodiment is a development of the fourth embodiment or the fifth embodiment, and all the gates 23 and 43 of the output transistors 2 and 4 on the output circuit side which are composed of two or more stages.
Are connected to a common signal line 9.

In this embodiment, as shown in FIG. 6, the gates of the output transistor (first output transistor) 2 and the output transistor (second output transistor) 4 in the fourth or fifth embodiment are It is electrically connected to the common signal line 9 from the inside. Since the output transistor composed of two or more stages can be controlled by one control signal, there is an effect that the control circuit can be simplified.

FIG. 7 is a block diagram of a semiconductor device showing a seventh embodiment of the present invention. The same parts as those in the above embodiment are designated by the same reference numerals, and the description thereof will be omitted.

This embodiment is a development of the fourth embodiment or the fifth embodiment, and the drains 24 and 44 of the output transistors 2 and 4 on the output circuit side which are composed of two or more stages are provided.
The gates of all the transistors from the second stage to the final stage except the first output transistor 2 when viewed from the side are connected to a common signal line that supplies a gate level at which the transistors are always on.

In this embodiment, as shown in FIG. 7, the output transistors 2 and 4 in the fourth or fifth embodiment are used.
Of all the gates except the first-stage gate (gate 43 of the output transistor 4 in this example) are electrically connected to a common signal line 10 that supplies a gate level at which the transistors are always on. . Since only the first stage is used as a switch and the second and subsequent stages are in the ON state, a predetermined voltage level is always supplied to the source of the first stage, which has the effect of reducing the signal transmission delay. Further, since the control signal is controlled to the ON state by one control signal, the control circuit is simple.

FIG. 8 is a block diagram of a semiconductor device showing an eighth embodiment of the present invention. The same parts as those in the above embodiment are designated by the same reference numerals, and the description thereof will be omitted.

This embodiment is an extension of the four embodiments from the fourth embodiment to the seventh embodiment, in which the output transistors 2 and 4 on the output circuit side each having two or more stages are formed. All wells 22 and 42 are formed separately.

As shown in FIG. 8, this embodiment is provided on a substrate in order to form two or more stages of transistors on the output circuit side in the four embodiments of the fourth to seventh embodiments. The well region to be formed is separated for each transistor. The effect of separating the well will be described with an example of a two-stage output transistor.

The drain 24 of the output transistor 2 is connected to the bonding pad 6, the source 21 is connected to the drain 44 of the output transistor 4, and the source 41 of the output transistor 4 is connected to the bonding pad 8. The wells provided on the substrate for forming are separated.

The wells 22 of the output transistors 2 and 4,
When 42 is separated, the sectional structure on the output circuit side becomes as shown in FIG. 9, and parasitic bipolar transistors Q2 and Q4 are formed in each output transistor. Where Q2
The drain 24 of the output transistor 2 serves as the collector, the source 21 serves as the emitter, and the well 22 serves as the base. For Q4, the drain 44 of the output transistor 4 serves as the collector, the source 41 serves as the emitter, and the well 42 serves as the base. The breakdown voltages of the parasitic bipolar transistors Q2 and Q4 are both BV
ceo, which is twice as large as when the output is composed of one stage.

On the other hand, when the wells 22 and 42 of the output transistors 2 and 4 are not separated, the sectional structure on the output circuit side is as shown in FIG. 10, and the bipolar transistor Q2 parasitic on the output transistors 2 and 4 is formed. And Q4
In addition, a bipolar transistor Q5 is also formed. Here, the parasitic bipolar transistors Q2 and Q4 are the same as in the case where the wells are separated, but the parasitic bipolar transistor Q5 has the drain 24 of the output transistor 2 as the collector and the well 22 and the well 42 as a common base.
It is a parasitic bipolar transistor having the source 41 of the output transistor 4 as an emitter.

The breakdown voltages of the parasitic bipolar transistors Q2, Q4 and Q5 are both BVceo, and the effect of the parasitic bipolar transistor Q5 must be suppressed in order to fully exert the effect of making the output transistor into two stages. Therefore, the parasitic bipolar transistor Q
2 and Q4, that is, the installation interval between the output transistors 2 and 4 must be widened.

In this embodiment, since the well in which the output transistor is formed is separated, the layout problem as described above can be solved and the effective circuit of the present invention can be realized.

In particular, since the present invention only separates wells, it has an advantage that it can be realized only by circuit design without adding manufacturing steps.

FIG. 11 is a block diagram of a semiconductor device showing a ninth embodiment of the present invention. The same parts as those in the above embodiment are designated by the same reference numerals, and the description thereof will be omitted.

This embodiment is a development of four embodiments from the fifth embodiment to the eighth embodiment, and the output transistors 2 and 4 on the output circuit side which are constituted by two or more stages are formed. Resistors 25 and 45 are added to the wells 22 and 24.

This embodiment differs from the fifth to seventh embodiments using the eighth embodiment in that the resistors 2 are formed in the wells 22 and 42 in which the output transistors 2 and 4 are formed, respectively.
Add 5 and 45 respectively.

That is, in FIG. 11, the source 11 of the protection transistor 1, the node to which the well 12 and the gate 13 are connected, and the well 2 of the output transistors 2 and 4 are connected.
2 and 42 are connected via resistors 25 and 45, respectively.

By connecting the resistors 25 and 45 in series, the surge current flowing as the collector current Ices of the protection transistor in the eighth embodiment flows into the wells 22 and 42 of the output transistors 2 and 4, and the parasitic pn is further added. The forward current of the junction, that is, the base current of the parasitic bipolar transistors Q2 and Q4 in FIG. 11 is suppressed. When a base current flows through the parasitic bipolar transistors Q2 and Q4 and both are turned on, a through current flows from the drain 24 of the output transistor 2 to the source 41 of the output transistor 4.
This current will destroy the output transistor.

By connecting the resistors 25 and 45 in series, it is possible to suppress the effect that the surge current flowing as the collector current Ices of the protection transistor flows into the wells 22 and 42 of the output transistors 2 and 4, and to the source 31 of the protection transistor 3. The effect of flowing can be enhanced. Therefore, as compared with the case of the eighth embodiment alone,
The protective effect can be enhanced.

In this embodiment, the larger the resistances 25 and 45 are, the larger the effect is. Therefore, the well resistance having originally high resistivity can be used as it is. Therefore, the area occupied by the output transistor is increased to add the resistance. There is no disadvantage in terms of pattern area.

The present invention is not limited to the above embodiments, and various modifications can be made based on the spirit of the present invention, and these modifications are not excluded from the scope of the present invention.

[0124]

As described in detail above, according to the present invention, the following effects can be achieved.

(1) According to the first aspect of the invention, in the electrostatic protection circuit of a semiconductor device having a multi-level output circuit mounted therein, the base of the output side of the protection transistor is higher than the breakdown voltage BVceo of the output transistor in the open state. It is possible to reduce the breakdown voltage BVces at the time of short-circuiting between the emitters, and to breakdown the protection transistor side first against an electrostatic surge to protect the output transistor.

( 2 ) According to the second aspect of the invention, the well concentration of the protection transistor is increased to lower the breakdown voltage,
Since the well concentration of the output transistor is made thin and the breakdown voltage is increased so that BVces <BVceo, the electrostatic surge current does not flow as the collector current Iceo of the parasitic transistor of the output transistor, and the parasitic transistor of the protection transistor does not flow. Since the collector current Ices and the diode current of the parasitic pn junction of the output transistor can be made to flow to the source of the output transistor, good electrostatic breakdown resistance can be obtained.

In particular, in a manufacturing process using two or more kinds of wells having different concentrations, there is an advantage that it is possible to realize it by only changing the setting condition of the well concentration without adding a manufacturing step.

( 3 ) According to the invention described in claim 3 , since the second protection transistor is newly added to the invention described in (1) above, the electrostatic surge current is changed to the collector current of the parasitic transistor of the output transistor. Since the collector current Ices of the parasitic transistor of the first protection transistor and the channel current of the second protection transistor can be supplied to the source of the output transistor without flowing as Iceo, good electrostatic breakdown resistance can be obtained.

Particularly, since the effect of the parasitic pn junction diode of the output transistor of the invention described in (1) above is replaced by the second protection transistor, the p of the output transistor is reduced.
There is an advantage that it is not affected by the characteristics of the n-junction diode and the setting conditions of the well concentration of the protection transistor and the output transistor can be widely changed. Further, in order to increase the number of parasitic pn junction diodes, it is possible to eliminate the disadvantage of the pattern area such that the output transistor area is intentionally increased when sufficient circuit characteristics are obtained even with an output transistor having a small pattern area.

(4) According to the invention described in claim 4, a resistor is newly added to the well in which the output transistor in the invention described in (1), (2) or (3) is formed. The node of the source of the first protection transistor, the well and the gate of which are connected to each other, and the well of the output transistor are connected to each other via a resistor.
By connecting these resistors in series, it is possible to suppress the effect of the surge current flowing as the collector current Ices of the first protection transistor flowing into the well of the output transistor and enhance the effect of flowing into the source of the second protection transistor. .

Therefore, the setting conditions of the well density of the protection transistor and the output transistor can be changed more widely than in the invention described in (1), (2) or (3) above.

(5) According to the invention described in claim 5, the protection circuit side is formed by one-stage transistor and the output circuit side is formed by two transistors.
Since the transistors are formed in more than one stage, the electrostatic surge current does not flow as the collector current Iceo of the parasitic transistor of the first output transistor, and the collector current Ice of the parasitic transistor of the protection transistor does not flow.
Since a diode current of the parasitic pn junction between s and the output transistor is passed to the source of the output transistor, excellent electrostatic breakdown resistance can be obtained.

Particularly, in a manufacturing process using a single well, there is an advantage that it can be realized only by circuit design without adding manufacturing steps.

(6) According to the invention described in claim 6, a second protection transistor is newly added to the invention described in ( 3 ) above. That is, the drain of the second protection transistor is electrically connected to the source of the second output transistor, and the source, the well, and the gate of the second protection transistor have a common node with the wells of the first and second output transistors. Connected to. By connecting in this way, a protection circuit is constituted by the first protection transistor and the second protection transistor.

Therefore, the electrostatic surge current is converted into the collector current Ic of the parasitic transistor of the first output transistor.
Since the collector current Ices of the parasitic transistor of the first protection transistor and the channel current of the second protection transistor are passed to the source of the output transistor without flowing as eo, excellent electrostatic breakdown resistance can be obtained.

In particular, since the effect of the parasitic pn junction diode of the second output transistor of the invention described in (4) above is replaced by the second protection transistor, the effect of the characteristics of the pn junction diode of the second output transistor is reduced. To increase the number of parasitic pn junction diodes
When sufficient circuit characteristics are obtained even with an output transistor having a small pattern area, it is possible to eliminate the disadvantage of the pattern area such that the output transistor area is intentionally increased.

(7) According to the invention described in claim 7, the gate of each transistor on the output circuit side, which is composed of the two or more stages of transistors in the invention described in (5) or (6), has a common signal. Since the output transistor which is electrically connected to the line and has two or more stages can be controlled by one control signal, the control circuit can be simplified.

(8) According to the invention described in claim 8, from the drain side of the transistors on the output circuit side which are composed of the two or more stages of transistors in the invention described in (5) or (6) above. Except for the first transistor to look at,
The gates of the transistors from the second stage to the final stage are electrically connected to a common signal line that supplies a gate level at which the transistors are always on. And, since only the first stage is used as a switch and the second and subsequent stages are in the ON state,
Since the predetermined voltage level is always supplied to the source of the first stage, the signal transmission delay can be reduced. Further, since the control signal is controlled to the ON state by one control signal, the control circuit is simple.

(9) According to the invention of claim 9, in the four inventions of (5), (6), (7) or (8) above, two or more stages of transistors on the output circuit side are formed. In order to achieve this, the well region provided on the substrate is manufactured separately for each transistor. Since the well in which the output transistor is formed is separated in this way, the layout can be facilitated.

In particular, the present invention has an advantage that it can be realized only by circuit design without adding a manufacturing process, since it only separates wells.

(10) According to the invention of claim 10,
In the invention described in (9) above, the output circuit side 2
A series resistance is added to each well in which transistors of more than two stages are formed.

Therefore, the surge current flowing as the collector current Ices of the protection transistor flows into the wells of the first output transistor and the second output transistor, and the forward current of the parasitic pn junction, that is, the parasitic bipolar transistor. Q2 and Q
4 (see FIG. 9) as a base current. When a base current flows through the parasitic bipolar transistors Q2 and Q4 and both are turned on, a through current flows from the drain of the first output transistor to the source of the second output transistor. This current will destroy the output transistor. By connecting a resistor in series with each, the collector current Ice of the protection transistor is
It is possible to suppress the effect that the surge current flowing as s flows into the wells of the first output transistor and the second output transistor, and enhance the effect of flowing into the source of the second protection transistor. Therefore, the protective effect can be further enhanced as compared with the case of the invention described in (9) alone.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a semiconductor device showing a first embodiment of the present invention.

FIG. 2 is a configuration diagram of a semiconductor device showing a second embodiment of the present invention.

FIG. 3 is a configuration diagram of a semiconductor device showing a third embodiment of the present invention.

FIG. 4 is a configuration diagram of a semiconductor device showing a fourth embodiment of the present invention.

FIG. 5 is a configuration diagram of a semiconductor device showing a fifth embodiment of the present invention.

FIG. 6 is a configuration diagram of a semiconductor device showing a sixth embodiment of the present invention.

FIG. 7 is a configuration diagram of a semiconductor device showing a seventh embodiment of the present invention.

FIG. 8 is a configuration diagram of a semiconductor device showing an eighth embodiment of the present invention.

FIG. 9 is a diagram showing a structure of a parasitic bipolar transistor of an output transistor when a well (substrate) is separated.

FIG. 10 is a diagram showing a structure of a parasitic bipolar transistor of an output transistor when a well (substrate) is not separated.

FIG. 11 is a configuration diagram of a semiconductor device showing a ninth embodiment of the present invention.

FIG. 12 is a diagram showing a conventional single-level NMOS output circuit.

FIG. 13 is a diagram showing a conventional multi-level NMOS output circuit.

FIG. 14 is a diagram schematically showing a relation between a collector voltage and a collector current of an npn bipolar transistor under each condition of a conventional base open and an emitter-base short circuit.

FIG. 15 is a protection circuit diagram having a conventional NMOS.

[Explanation of symbols]

1 Protection transistor (NMOS) 2 output transistors (NMOS) 3 Protection transistor (second protection transistor) 4 output transistor (second output transistor) 6 Bonding pad (external terminal) 7 Bonding pad (well / substrate) 8 Bonding pad (source) 9,10 signal line 11,21,31,41 Source 12, 22, 32, 42 wells 13,23,33,43 gates 14,24,34,44 drain 25,45 resistance

Continuation of the front page (56) Reference JP-A-5-109991 (JP, A) JP-A-2-77153 (JP, A) JP-A-3-148866 (JP, A) JP-A-57-204162 (JP , A) (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 27/085-27/092 H01L 21/8234-21/8238 H01L 27/04 H01L 29/72

Claims (10)

(57) [Claims] 1. A semiconductor device having, in an output circuit, an output transistor in which a potential supplied to a substrate or a well is different from a potential supplied to a source, and a semiconductor device having a protection transistor in which the substrate and the well are connected to the same node. Of the output transistor, the breakdown voltage BV when the base of the output transistor is open.
A semiconductor characterized in that the breakdown voltage BVces at the time of short-circuiting between the base and the emitter on the protection transistor side is lower than that on ceo, and the protection transistor side is broken down first against an electrostatic surge to protect the output transistor. Device protection circuit. 2. A protection circuit as claimed in claim 1 Symbol placement, darkening the well concentration of said protection transistor,
A protection circuit for a semiconductor device, wherein the well concentration of the output transistor is reduced. 3. A semiconductor device having, in an output circuit, an output transistor having different supply potentials to a substrate or a well and a source, and a first protection transistor having the substrate or the well and the source connected to the same node . The output tiger
Second protection connected between the source of the transistor and the well
A protection circuit for a semiconductor device having a transistor , comprising: a source, a well, and a gate of the second protection transistor.
Is connected to the well of the output transistor
The drain of the second protection transistor to the output
Connect to the source of the transistor and connect the first protection transistor
The sum of the breakdown voltage and the threshold voltage of said second protection transistor of register is set lower than the breakdown voltage of the output transistor capacitor, a semiconductor device is characterized in that so as to respond to the protection circuit above Protection circuit. 4. The protection circuit for a semiconductor device according to claim 3 , wherein the well of the output transistor is connected through a resistor.
The source, the well and the gate of the first protection transistor.
A protection circuit for a semiconductor device, wherein the protection circuit is connected to a node to which the switch is connected. 5. The semiconductor device protection circuit according to claim 1, wherein the protection circuit side is formed of one-stage transistors, and the output circuit side is formed of two or more stages of transistors. Device protection circuit. 6. The semiconductor device protection circuit according to claim 3 , wherein the protection circuit side is formed by two stages of transistors, and the output circuit side is formed by two or more stages of transistors. Device protection circuit. 7. The protection circuit for a semiconductor device according to claim 5, wherein the gates of the respective transistors on the output circuit side, which are composed of the two or more stages of transistors, are electrically connected to a common signal line. A semiconductor device protection circuit characterized by the above. 8. The protection circuit for a semiconductor device according to claim 5, wherein among the transistors on the output circuit side formed of the transistors of two or more stages, two stages except the first transistor seen from the drain side are provided. A protection circuit for a semiconductor device, characterized in that the gates of the transistors from the eye to the final stage are electrically connected to a common signal line that supplies a gate level at which the transistors are always on. 9. A protection circuit for a semiconductor device according to claim 5, 6, 7 or 8, wherein a well region provided on a substrate for forming two or more stages of transistors on the output circuit side is separated for each transistor. A protection circuit for a semiconductor device, which is manufactured by 10. The semiconductor device protection circuit according to claim 9, wherein a series resistance is added to each well in which two or more stages of transistors on the output circuit side are formed. Device protection circuit.