JP3370057B2 - Method for manufacturing semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming an element isolation insulating film.

[0002]

2. Description of the Related Art With the recent trend of higher integration and higher density of ULSI, the demand for miniaturization of element isolation film is increasing more and more. The conventional element isolation technology includes a selective oxidation method (Local Oxidation of Silicon: LOCOS method).
However, in the LOCOS method, since the element isolation portion inevitably rises, the flatness of the substrate surface is significantly impaired, and a photolithography process is performed when a semiconductor element is formed in the element formation region of the semiconductor substrate. However, there is a problem that it is difficult to perform fine processing.

Therefore, as a method for solving such a problem, a shallow groove is previously formed by etching in a region where a device isolation insulating film is to be formed in a silicon substrate.
After that, a technique has been proposed in which an insulating film is formed by oxidation by the LOCOS method to reduce a step caused by the oxidation. This technique is called a lysest LOCOS method, and is disclosed in, for example, Japanese Patent Laid-Open No. 9-330923.

[0004]

[Problems to be Solved by the Invention] Conventional resist LOC
Problems in the OS method will be described with reference to FIG. In the conventional resist LOCOS method, the element isolation insulating film 51 is formed.
The (111) crystal face (facet) 55 of the silicon substrate 54 appears in the vicinity of the boundary with the element formation region 53 in the formation region 52, and an oxidation suppression layer called a white ribbon is formed near the tip of the bird's beak peculiar to LOCOS. Occur. The (111) crystal plane of silicon appears because the edge portion of the element isolation insulating film formation region 52 adjacent to the element formation region 53 is thick oxidation resistant to prevent the element formation region 53 from being oxidized during oxidation. Since it is covered with a mask (not shown), it is considered that the volume expansion accompanying the oxidation is not allowed and the oxidation does not occur even if the oxidizing species come. Further, it is considered that the white ribbon is formed by oxidizing a part of the oxidation resistant mask (silicon nitride film) by the oxidizing species to generate ammonia, and the generated ammonia nitrides silicon of the substrate material. .

After removing the oxidation resistant mask, an oxide film called a sacrificial oxide film is formed in the element forming region 53, but the element forming region 53 near the bird's beak is oxidized by the presence of the white ribbon described above. Is suppressed. For this reason, a convex portion is formed in the region where the white ribbon was present, and the (111) plane is connected to the convex portion,
A steep corner portion 56 is formed at the boundary between the element forming region 53 and the element isolation insulating film forming region 52, and as a result, the following problems occur.

(1) Since the gate oxide film formed in the element formation region 53 does not uniformly oxidize at the corners 56, the oxide film in that portion becomes thin, which causes the breakdown voltage of the gate oxide film. Become. (2) In the case where a MOS transistor having a structure in which the gate electrode extends to the upper part of the element isolation insulating film 51 is formed, the corner portion 5
6, the electric field is concentrated, and the off-leakage characteristic and the narrow channel characteristic of the transistor are deteriorated.

The present invention relates to a method of manufacturing a semiconductor device,
The purpose is to eliminate such a problem.

[0008]

According to a first aspect of the present invention, there is provided a semiconductor device manufacturing method, wherein an element formation region is formed by forming at least two trenches in a semiconductor substrate, and the element formation region is subjected to acid resistance. A method of forming an element isolation insulating film by oxidizing the bottom of the trench by covering the trench with an oxidation mask, and the ratio (W / t) of the width W to the thickness t of the oxidation resistant mask is 3.8. The above is the summary.

As described above, the width W and the thickness t of the oxidation resistant mask are
By setting the ratio (W / t) to and above 3.8,
When the bottom of the trench is oxidized, the oxidation-resistant mask is likely to be elastically deformed. Therefore, in the vicinity of the boundary with the element formation region in the formation region of the isolation insulating film, the silicon substrate (1
11) Crystal planes (facets) do not appear, and the boundary between the element formation region and the element isolation insulating film formation region has a rounded shape. As a result, the corners of the boundary between the element formation region and the element isolation insulating film formation region do not become steep.

Further, in this case, on the substrate,
When the element forming regions having different widths are formed, the thickness of the oxidation resistant mask formed on the element forming region having a small width is smaller than the thickness of the oxidation resisting mask formed on the element forming region having a large width. Is desirable. By doing so, it is possible to reduce stress applied to the element formation region having a small width from the oxidation resistant mask formed thereon.

A method of manufacturing a semiconductor device according to a second aspect of the present invention includes at least two steps of forming an oxidation resistant mask on a semiconductor substrate and thinning a partial region of the oxidation resistant mask. In the step of forming a trench, the etching resistant mask and the semiconductor substrate are etched so that the thinned oxidation resistant mask exists between the trenches, and a region corresponding to the thinned portion is formed. , A step of defining a narrow first element formation region and a region corresponding to a non-thinned portion defining a wide second element formation region, and element isolation by oxidizing the bottom of the trench. And a step of forming an insulating film for use,
The gist is that the ratio (W / t) between the width W and the thickness t of the oxidation resistant mask is set to 3.8 or more.

The oxidation temperature is 1050 ° C. to 115 ° C.
It is desirable to set it to 0 ° C. By doing so, the operation of the present invention can be obtained more reliably. Further, it is preferable that a buffer layer is formed under the oxidation resistant mask before oxidizing the bottom of the trench. Accordingly, when the bottom of the trench is oxidized, the stress applied to the substrate by the oxidation resistant mask can be relieved.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION (First Embodiment) A first embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a sectional view of a semiconductor device 1 according to the first embodiment. In the figure, a p-type single crystal silicon substrate 2
The element formation region 4 is defined by the element isolation insulating film 3. In the element formation region 4, a MOS type transistor 8 having an LDD structure composed of a gate oxide film 5, a gate electrode 6 and source / drain regions 7, 7 is formed. Sidewall spacers 9 are formed on the sidewalls of the gate electrode 6.

[0014]

According to a first aspect of the present invention, there is provided a semiconductor device manufacturing method, wherein an element formation region is formed by forming at least two trenches in a semiconductor substrate, and the element formation region is subjected to acid resistance. A method of forming an element isolation insulating film by oxidizing the bottom of the trench by covering the trench with an oxidation mask, and the ratio (W / t) of the width W to the thickness t of the oxidation resistant mask is 3.8. The above is set to 6.667 or less as the gist.

Next, a method of manufacturing the semiconductor device 1 according to the first embodiment will be described with reference to process sectional views shown in FIGS. 1 and 2 to 8. Step 1 (see FIG. 2): On the p-type single crystal silicon substrate 2,
After forming the silicon oxide film 12 (film thickness 10 nm) by using a thermal oxidation method (for example, dry oxidation using a temperature of 950 ° C.), a CVD method (a low pressure CVD method, a plasma CVD method, a high density plasma) is formed thereon. CVD method or atmospheric pressure CVD method)
Is used to form the silicon nitride film 13 in this order.

Step 2 (see FIG. 3): Silicon nitride film 13
After the resist pattern 14 is formed on the silicon oxide film 12, the silicon nitride film 13 and the silicon oxide film 12 are adjusted using the resist pattern 14 as a mask and adjusting the etching gas.
The silicon substrate 2 and then the silicon substrate 2
nm etching to form a trench 15 in the substrate 2.
... to form. In the substrate 2, each trench 15 ... Becomes an element isolation insulating film formation planned region, and each trench 15 ...
The region sandwiched between is the element formation region 4. At this time, in the first embodiment, the patterned silicon nitride film 1 is formed.
The respective dimensions are set so that the ratio (W / t) of the width W of 3 to the film thickness t is 3.8 or more. Specifically, the width W of the silicon nitride film 13 is set to 500 nm and the film thickness t is set to 1
It is set to 30 nm.

Step 3 (see FIG. 4): Resist pattern 1
After removing 4, the element isolation insulating film 3 (thickness: 350 nm) is formed in the trench 15 by performing thermal oxidation at a temperature of 1050 ° C. or higher in an oxygen atmosphere. This time,
Since the silicon nitride film 13 functions as an oxidation resistant mask, the element formation region 4 covered with the silicon nitride film 13 is formed.
Is not oxidized. Further, the silicon oxide film 12 functions as a buffer layer for relieving the stress applied to the substrate 2 by the silicon nitride film 13 during oxidation.

In the first embodiment, as described above, the ratio of the width W of the silicon nitride film 13 to the film thickness t (W /
Since t) is set to be 3.8 or more, the silicon nitride film 13 is easily elastically deformed during oxidation,
No (111) crystal plane (facet) of silicon appears in the vicinity of the boundary between the element isolation insulating film 3 and the element formation region 4. Therefore, in the silicon substrate 2, the corner portion 2b at the boundary between the element formation region 4 and the element isolation insulating film 3 has a rounded shape and is not steep.

Table 1 shows the angle θ of the corner portion 2b of the boundary between the element forming region 4 and the element isolation insulating film 3 with respect to the vertical line in FIG. 4, the width W of the silicon nitride film 13 and the film thickness t. It shows the result of measurement while changing the ratio (W / t).

[0020]

[Table 1]

The angle θ when the (111) crystal plane (facet) of silicon appears on the inclined surface 2a of the silicon substrate 2 in the vicinity of the boundary between the element isolation insulating film 3 and the element formation region 4 is 34.5 degrees. Yes, and when W / t is less than 3.8, the angle is almost close to a facet. On the other hand, when W / t is set to 3.8 or more, the angle θ sharply increases. That is, it can be seen that the corner portion 2b at the boundary between the element formation region 4 and the element isolation insulating film 3 has a rounded shape and is not steep.

As described above, by setting W / t to be 3.8 or more, the silicon nitride film 13 has elasticity so as to be deformed according to the volume expansion when the silicon resistance is oxidized, which is different from the conventional one. Since the volume expansion is allowed differently, the generation of the (111) crystal plane of silicon and the formation of a sharp corner unlike the conventional example do not occur at the same time. Step 4 (see FIG. 5): The silicon nitride film 13 is removed using a hot phosphoric acid solution at 150 to 160 ° C. Further, after removing the silicon oxide film 12, the surface of the substrate 2 is thermally oxidized to form a sacrificial oxide film 16 in the element formation region 4. At this time, since the formation temperature of the element isolation insulating film 3 is set to 1050 to 1150 ° C. in step 3, an oxidation suppression layer such as a white ribbon is not formed around the element isolation insulating film 3, No unevenness due to the oxidation suppressing layer is generated on the surface of the element forming region 4.

Step 5 (see FIG. 6): Impurity ions for adjusting wells and threshold values are implanted into the substrate 2 through the sacrificial oxide film 16. Step 6 (see FIG. 7): After removing the sacrificial oxide film 16, the gate oxide film 5 is formed again on the surface of the substrate 2 by using the thermal oxidation method. At this time, as described above, in the silicon substrate 2, the corner portion 2b of the boundary portion between the element formation region 4 and the element isolation insulating film 3 has a rounded shape and is not steep. Is relatively uniformly oxidized, and the film thickness of the gate oxide film 5 in this portion does not become particularly thin.

Step 7 (see FIG. 1): A MOS transistor 8 having an LDD structure including a gate oxide film 5, a gate electrode 6 and source / drain regions 7 and 7 in an element forming region 4 by using a conventionally known method. To form. After that, MO
An interlayer insulating film 10 made of a silicon oxide film is formed on the entire surface of the substrate 2 including the S-type transistor 8 and the element isolation insulating film 3, and a contact hole 11 is formed in the interlayer insulating film 10.
11 are formed, and aluminum electrode wirings 12 and 12 are connected to the source / drain regions 7 and 7 through the contact holes 11 and 11, respectively.

As described above, in the first embodiment, in the silicon substrate 2, the corner portion 2b at the boundary between the element formation region 4 and the element isolation insulating film 3 has a rounded shape and is steep. Since this is not present, oxidation is relatively evenly performed in this corner portion 2b, and the gate oxide film 5 in this portion is oxidized.
Does not become particularly thin. Therefore, it is possible to prevent the occurrence of a breakdown voltage failure of the gate oxide film 5 and improve the reliability of the semiconductor device 1.

Although not shown in the first embodiment, even in the case where the MOS transistor 8 having a structure in which the gate electrode 6 extends to the upper portion of the element isolation insulating film 3 is formed, the corner portion 2b is also formed. Concentration of electric field is suppressed,
There is no concern that the off-leakage characteristic and the narrow channel characteristic of the transistor will deteriorate. (Second Embodiment) A second embodiment of the present invention will be described with reference to the drawings. The second embodiment differs from the first embodiment only in the process corresponding to the above process 2, and the other processes are the same. Therefore, here, only the process corresponding to the above process 2 will be described with reference to the process sectional views shown in FIGS.

Step 2a (see FIG. 8): Silicon nitride film 1
After the resist pattern 20 is formed on the silicon nitride film 3, the silicon nitride film 13 is used as a mask.
Is partially etched to thin this portion. Step 2b (see FIG. 9): After removing the resist pattern 20, the resist pattern 21 is formed again on the silicon nitride film 13, and the silicon nitride film 1 is formed using the resist pattern 21 as a mask and adjusting the etching gas.
3 and the silicon oxide film 12 are etched, and then the silicon substrate 2 is further etched by 50 nm to form trenches 15 in the substrate 2.

In the second embodiment, the narrow element forming regions 4 are formed on the substrate 2 by the trenches 15 ...
The element formation region 4a having a narrow width is formed in the region a in which the silicon nitride film 13 is thinned in the step 2a. That is, in the second embodiment, the film thickness of the silicon nitride film 13 as the oxidation resistant mask covering the narrow element forming region 4a is set to the silicon film serving as the oxidation resisting mask covering the wide element forming region 4b. It is smaller than the film thickness of the nitride film 13. Specifically, in the narrow element formation region 4a, the width W1 of the silicon nitride film 13 is set to 350 nm and the film thickness t1 is set to 80 nm, and in the wide element formation region 4b, the width W2 of the silicon nitride film 13 is set. Is 1000 nm and the film thickness t2 is 150 nm.

In the narrow element forming region 4a, the cross-sectional aspect ratio (W / t) of the oxidation-resistant mask becomes small and the oxidation-resistant mask itself is less likely to be elastically deformed. 13 is a silicon substrate 2
However, in the second embodiment, the ratio of the width W of the silicon nitride film 13 to the film thickness t (W /
Since the thickness of the silicon nitride film 13 is adjusted according to the width of the element formation region 4 within a range in which t) is 3.8 or more, the effect of the first embodiment can be obtained more effectively. it can.

[0030]

As described in detail above, according to the present invention,
A good element isolation structure can be obtained, and a highly reliable semiconductor device can be provided.

[Brief description of drawings]

FIG. 1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment that embodies the present invention.

FIG. 2 is a schematic cross-sectional view showing the manufacturing process of the semiconductor device according to the first embodiment of the present invention.

FIG. 3 is a schematic cross-sectional view showing the manufacturing process of the semiconductor device according to the first embodiment of the present invention.

FIG. 4 is a schematic cross-sectional view showing the manufacturing process of the semiconductor device according to the first embodiment of the present invention.

FIG. 5 is a schematic cross-sectional view showing the manufacturing process of the semiconductor device according to the first embodiment of the present invention.

FIG. 6 is a schematic cross-sectional view showing the manufacturing process of the semiconductor device according to the first embodiment of the present invention.

FIG. 7 is a schematic cross-sectional view showing the manufacturing process of the semiconductor device according to the first embodiment of the present invention.

FIG. 8 is a schematic cross-sectional view showing the manufacturing process of the semiconductor device according to the second embodiment of the invention.

FIG. 9 is a schematic cross-sectional view showing the manufacturing process of the semiconductor device according to the second embodiment of the invention.

FIG. 10 is an enlarged cross-sectional view of a main part of a semiconductor device for explaining a conventional problem.

[Explanation of symbols]

1 Semiconductor device 2 Silicon substrate 3 Insulation film for element isolation 4 element formation area 5 Gate oxide film 6 Gate electrode 7 Source / drain region 8 MOS type transistor 12 Silicon oxide film 13 Silicon nitride film 15 trench 16 Sacrificial oxide film

─────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-60-74640 (JP, A) JP-A-60-98640 (JP, A) JP-A-10-50690 (JP, A) JP-A-3- 159240 (JP, A) JP 59-41851 (JP, A) Kiyoo Ito, Advanced Electronics Series I-9 VLSI memory, Japan, Baifukan, November 5, 1994, p. 10 (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 21/70-21/74 H01L 21/76-21/765 H01L 21/77

Claims (5)

(57) [Claims] 1. An element isolation region is formed by forming at least two trenches in a semiconductor substrate, covering the element formation region with an oxidation resistant mask, and oxidizing the bottom of the trench. A method of forming a film, wherein a ratio (W / t) of the width W and the thickness t of the oxidation resistant mask is set to 3.8 or more and 6.667 or less . 2. The element forming regions having different widths are formed on the substrate, and the thickness of the oxidation resistant mask formed on the element forming regions having a small width is formed on the element forming regions having a large width. The method for manufacturing a semiconductor device according to claim 1, wherein the thickness is smaller than the thickness of the oxidation resistant mask. 3. A step of forming an oxidation resistant mask on a semiconductor substrate, a step of thinning a partial region of the oxidation resistant mask, and a step of forming at least two trenches, wherein The oxidation resistant mask and the semiconductor substrate are etched so that the thinned oxidation resistant mask exists, and a region corresponding to the thinned portion defines a narrow first element formation region. A region corresponding to a portion which is not thinned, defining a wide second element formation region; and forming an element isolation insulating film by oxidizing the bottom of the trench, A method of manufacturing a semiconductor device, wherein a ratio (W / t) of the width W and the thickness t of the oxidation resistant mask is set to 3.8 or more. 4. The temperature of the oxidation is 1050 ° C. to 1150.
4. The method according to any one of claims 1 to 3, wherein the temperature is set to ° C.
A method of manufacturing a semiconductor device according to item. 5. The method of manufacturing a semiconductor device according to claim 1, wherein a buffer layer is formed under the oxidation-resistant mask before oxidizing the bottom of the trench. .