JP3370269B2 - Insulated gate field effect transistor - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an insulated gate field effect transistor.

[0002]

2. Description of the Related Art Conventionally, an insulated gate field effect transistor described below with reference to FIG. 13 has been proposed. That is, an impurity having the first and second main surfaces 1a and 1b and giving p-type as the first conductivity type is 1 × 10 ¹⁸ cm ^−3.
A single crystal semiconductor layer having a p-type conductivity as a first conductivity type introduced at a relatively low concentration of less than, and surrounded by an element isolation insulating film 2 made of silicon oxide. Has 1.

Then, in the single crystal semiconductor layer 1, a first
From the main surface 1a side thereof, an impurity which gives n-type as the second conductivity type opposite to the p-type as the first conductivity type is 5 × 10 ¹⁹ c
The source region 3 and the drain region 4 having the n-type as the second conductivity type, which is introduced at a relatively high concentration such as m ⁻³ or more, leave a channel region 5 therebetween. It is formed to a depth reaching the main surface 1b.

The first main surface 1a of the single crystal semiconductor layer 1
Element isolation is performed so that the gate electrode 7 made of a polycrystalline silicon layer in which impurities imparting conductivity are introduced at a high concentration is opposed to the channel region 5 via the gate insulating film 8 made of silicon oxide. First insulating film 9 made of silicon oxide and extended on the insulating film 2 for insulation
Are formed so as to cover the gate electrode 7, the gate insulating film 8 and the element isolation insulating film 2. In this case, the surface of the first insulating film 9 opposite to the single crystal semiconductor layer 1 side is a flat surface 9
It is said to be a.

Further, the first insulating film 9 is adhered on its flat surface 9a side to a support substrate 30 made of single crystal silicon, quartz, Pyrex, silicon carbide, aluminum nitride, diamond, sapphire or the like.

Further, the second main surface 1b of the single crystal semiconductor layer 1
A second insulating film 10 made of silicon oxide is formed thereon, and a window 13 for exposing the source region 3 and the channel region 5 to the outside is formed in the second insulating film 10, and Window 1 for exposing drain region 4 to the outside
4 are formed.

Further, a source / back gate voltage application electrode 23 connected to the source region 3 and the channel region 5 through the window 13 is formed on the second insulating film 10, and the drain is also provided through the window 14. A drain electrode 24 connected to the region 4 is formed. In this case, the source / back gate voltage applying electrode 23 is a metal selected from molybdenum, scandium, europium, yttrium, titanium, hafnium, vanadium, chromium, lead, nickel, platinum, cobalt, tungsten, and aluminum, Alternatively, it is made of its silicide or nitride. The source / back gate voltage applying electrode 23 is made of such a material, while the source region 3 is
× 10 ¹⁹ cm ^-3 have a relatively high impurity concentration of the above, by the channel region 5 has a relatively low impurity concentration of less than 1 × 10 ¹⁸ c m ^-3, and the back gate voltage source The connection of the application electrode 23 to the source region 3 and the channel region 5 described above is a connection by ohmic junction and Schottky junction, respectively. Further, the drain electrode 24 is used as a source / back gate voltage applying electrode 23.
Made of the same material as. The drain electrode 24 is made of such a material, while the drain region 3 is 5 × 10 ¹⁹ cm.
^Since the drain electrode 24 has a relatively high impurity concentration of ⁻³ or more, the drain electrode 24 is connected to the drain region 4 by ohmic junction.

Although not shown, the element isolation insulating film 2 is also provided.
And a window for exposing the gate electrode 7 to the outside is formed in the second insulating film 10 and the second insulating film 1
A conductive layer for leading the gate electrode, which is connected to the gate electrode 7 through the window, is formed on the gate electrode 0.

The above is the structure of the conventionally proposed insulated gate field effect transistor.

According to the conventional insulated gate field effect transistor having such a structure, the source / back gate voltage applying electrode 23 is connected to the ground, and the drain electrode 24 and the source / back gate voltage applying electrode are provided. A load (not shown) is connected between the electrodes 23 via a power source (not shown) having the positive electrode side as the drain electrode 24 side, and
Between the gate electrode leading conductive layer and the source / back gate voltage applying electrode 23 connected to the gate electrode 7,
A control voltage that obtains a positive voltage based on the source / back gate voltage application electrode 23 and a zero or negative voltage lower than the positive voltage as “1” and “0” in binary display, respectively. If a source (not shown) is connected, when the control voltage from the control voltage source takes "0" in binary display, almost no n channel is formed in the channel region 5 from the gate insulating film 8 side. Even if it is formed with a slight spread, the control voltage from the control voltage source takes "1" in the binary display, the channel region 5 is from the gate insulating film 8 side, the n channel is the source region 3 It extends between the drain region 4 and the drain region 4, and is formed to be wider than the case where the control voltage takes "0" in the binary display. Therefore, the control voltage takes "1" or "0" in the binary display. Depending on , Between the source region 3 and the drain region 4 can be controlled to a state called an ON state or a state called an OFF state, and thus the current in the load has a large value "1". It is possible to obtain a function as an insulated gate field effect transistor in which it is possible to control whether to supply by "" or by supplying "0" of binary display having a sufficiently small value.

Further, according to the conventional insulated gate field effect transistor shown in FIG. 13, since the source / back gate voltage applying electrode 23 is connected to the source region 3 and the channel region 5, the channel region 5 is formed. In addition, the back gate voltage can be applied at a value sufficiently close to the potential of the source region 3, so that the function as an insulated gate field effect transistor can be stably obtained.

Further, conventionally, an insulated gate field effect transistor described below with reference to FIG. 14 has also been proposed. That is, the portions corresponding to those in FIG. 13 are denoted by the same reference numerals, and detailed description thereof will be omitted.
From the main surface 1a side of the second main surface 1b so that the source region 3 and the drain region 4 leave the channel region 5 therebetween.
Instead of being formed in the single crystal semiconductor layer 1, (a) the source region 3 and n as the second conductivity type similar to those described above from the first main surface 1a side are formed. The offset region 6 having the n-type as the second conductivity type, in which the impurity imparting the type is introduced at a relatively low concentration, leaves the channel region 5 similar to that described above between them.
The drain region 4 is formed to a depth reaching the second main surface 1b, and from the first main surface 1a side, the drain region 4 similar to that described above is provided in the offset region 6 on the side opposite to the channel region 5 side. The structure is the same as that of the conventional insulated gate field effect transistor shown in FIG. 13 except that the structure is formed so as to be connected to each other and reach the second main surface 1b.

The conventional insulated gate field effect transistor having such a configuration has the same configuration as that of the conventional insulated gate field effect transistor shown in FIG. 13 except for the above-mentioned matters. Although omitted, it is clear that the same action and effect as in the case of the conventional insulated gate field effect transistor shown in FIG. 13 can be obtained.

Further, in the case of the conventional insulated gate field effect transistor shown in FIG. 14, since the offset region 6 is interposed between the channel region 5 and the drain region 4, the source / back gate voltage is applied. The breakdown voltage between the working electrode 23 and the drain electrode 24 is made higher than that of the conventional insulated gate field effect transistor shown in FIG. 13 in which the offset region 6 is not interposed between the channel region 5 and the drain region 4. Therefore, the offset region 6 is interposed between the channel region 5 and the drain region 4 to limit the voltage of the power source connected through the load between the source / back gate voltage applying electrode 23 and the drain electrode 24. It can be relaxed as compared with the case of the conventional insulated gate field effect transistor shown in FIG.

[0015]

In the case of the conventional insulated gate field effect transistors shown in FIGS. 13 and 14, in any of them, as described above, the source / back gate voltage applying electrode 23 is Since the source region 3 and the channel region 5 are connected to each other, the back gate voltage can be applied to the channel region 5 at a value sufficiently close to the potential of the source region 3, and thus the function as an insulated gate field effect transistor can be obtained. Although it can be stably obtained, in this case, the connection of the source / back gate voltage applying electrode 23 to the channel region 5 is such that the above-mentioned source / back gate voltage applying electrode 23 is made of the above-mentioned material, Due to the fact that the channel region 5 has a relatively low impurity concentration of less than 1 × 10 ¹⁸ cm ⁻³ ,
Since the connection is made by the Schottky junction, a depletion layer extending from the side of the source / back gate voltage applying electrode 23 side is formed in the channel region 5.

Therefore, there is a drawback in that the so-called short channel effect may occur, such that the threshold voltage and the transconductance of the insulated gate field effect transistor can be obtained only at low values.

Therefore, the present invention does not have the above-mentioned drawbacks.
A new insulated gate field effect transistor is proposed.

[0018]

The insulated gate field effect transistor according to the first invention of the present application is the same as the case of the conventional insulated gate field effect transistor described above with reference to FIG. And a single crystal semiconductor layer having a first conductivity type and having a second conductivity type opposite to the first conductivity type in the single crystal semiconductor layer from the first main surface side. The second region so that the source region and the drain region having the conductivity type of
Is formed so as to reach the main surface of the single crystal semiconductor layer, a gate electrode is formed on the first main surface of the single crystal semiconductor layer so as to face the channel region through a gate insulating film, and Is formed so as to cover the gate electrode and the gate insulating film, and the surface of the first insulating film opposite to the single crystal semiconductor layer side is a flat surface. Is bonded to a support substrate on the flat surface side thereof, a second insulating film is formed on the second main surface of the single crystal semiconductor layer, and the source is formed on the second insulating film. A source / back gate voltage application electrode connected to the region and the channel region is formed.

However, the insulated gate field effect transistor according to the first invention of the present application is the insulated gate field effect transistor having the above structure,
(A) Second of the single crystal semiconductor layer in the channel region
An electrode attachment region having a first conductivity type in which an impurity imparting a first conductivity type is introduced at a higher concentration than that of the channel region is formed in the main surface side of (b) for the source. The connection of the electrode serving also as a back gate voltage to the source region is a connection to the source region by ohmic contact, and (c) the electrode serving as a source and back gate voltage applying electrode is in ohmic contact with the region with an electrode. By doing so, the connection of the source / back gate voltage applying electrode to the channel region is made via the electrode region.

Further, the insulated gate field effect transistor according to the second invention of the present application has the first and second main surfaces as in the case of the conventional insulated gate field effect transistor described above with reference to FIG. And a single crystal semiconductor layer having a first conductivity type, wherein: (i) a second crystal opposite to the first conductivity type from the first main surface side in the single crystal semiconductor layer; A source region having a second conductivity type in which an impurity imparting a conductivity type is introduced at a relatively high concentration and an impurity providing a second conductivity type in a relatively low concentration are introduced second
And an offset region having a conductivity type are formed to a depth reaching the second main surface so as to leave a channel region therebetween, and (ii) from the first main surface side to the first main surface side. A drain region having a second conductivity type into which an impurity imparting a second conductivity type is introduced at a relatively high concentration is connected to the offset region on the side opposite to the channel region side, and the second main surface is formed. Formed to a depth reaching
A gate electrode is formed on the first main surface of the single crystal semiconductor layer so as to face the channel region via a gate insulating film, and the first insulating film includes the gate electrode and the gate insulating film. Formed to cover the first
The surface of the insulating film opposite to the single crystal semiconductor layer side is a flat surface, and the first insulating film is bonded to the supporting substrate on the flat surface side, and the single crystal semiconductor A second insulating film is formed on the second main surface of the layer, and a source / back gate voltage applying electrode connected to the source region and the channel region is formed on the second insulating film. Has been formed.

However, the insulated gate field effect transistor according to the second invention of the present application is the insulated gate field effect transistor having such a structure as follows.
As in the case of the insulated gate field effect transistor according to the first invention of the present application, (a) an impurity imparting the first conductivity type is introduced into the channel region in the second main surface side of the single crystal semiconductor layer. An electrode-attached region having a first conductivity type introduced at a higher concentration than that of the channel region is formed, and (b) connection of the source / back gate voltage applying electrode to the source region is The electrode for ohmic contact is connected to the source region, and (c) the electrode for applying source / back gate voltage is in ohmic contact with the region for attaching electrode. Is connected to the above channel area,
It is connected through the electrode region.

In each of the above-mentioned first invention of the present application and the second invention of the present application, the single crystal semiconductor layer is a single crystal silicon layer, and the channel region is 1 x 1
The source region and the electrode attachment region have an impurity concentration of 5 × 10 ¹⁹ cm ⁻³ or more, and the source / back gate voltage applying electrode has an impurity concentration of less than 0 ¹⁸ cm ^−3. , Molybdenum, scandium, europium,
The metal selected from yttrium, titanium, hafnium, vanadium, chromium, lead, nickel, platinum, cobalt, tungsten, and aluminum, or a silicide or nitride thereof can be used.

[0023]

BEST MODE FOR CARRYING OUT THE INVENTION Next, referring to FIG.
An embodiment of an insulated gate field effect transistor according to the second invention will be described. In FIG. 1, parts corresponding to those in FIG. 13 are designated by the same reference numerals, and detailed description thereof will be omitted.

The insulated gate field effect transistor according to the first invention of the present application shown in FIG. 1 corresponds to the conventional insulated gate field effect transistor shown in FIG. 13 in which the second main portion of the single crystal semiconductor layer 1 of the channel region 5 is formed. In the surface 1b side,
Impurities that are connected to the source region 3 and give p-type conductivity as the first conductivity type are 5 × 10 ¹⁹ cm ⁻³ or more.
An electrode attachment region 51 having a p-type as the first conductivity type, which is introduced at a higher concentration than the channel region 5, is formed, and the source / back gate voltage application electrode 2 is also formed.
The connection of 3 to the source region 3 is as described in the conventional insulated gate field effect transistor shown in FIG.
For the reason described in the conventional insulated gate field effect transistor shown in FIG. 3, it is connected to the source region 3 by ohmic junction, but the source / back gate voltage applying electrode 2 is also used.
3 is the electrode-attached region 51, the source / back gate voltage applying electrode 23 is the material described in the conventional insulated gate field effect transistor shown in FIG. 13, and the electrode-attached region 51 has a high impurity concentration. Since it has an ohmic junction because it has, the connection of the source / back gate voltage applying electrode 23 to the channel region 5 is not shown in FIG.
The conventional insulated gate field effect transistor shown in FIG. 13 is replaced by the Schottky junction in the case of the conventional insulated gate field effect transistor shown in FIG. It has the same structure as that of the transistor.

The above is the configuration of the embodiment of the insulated gate field effect transistor according to the first invention of the present application.

The embodiment of the insulated gate field effect transistor according to the first invention of the present invention having such a structure is based on the manufacturing method of the conventional insulated gate field effect transistor shown in FIG. It can be manufactured by an embodiment of a manufacturing method described below with reference to FIG.

That is, on a single crystal semiconductor substrate 41 made of a single crystal silicon substrate having a p-type as a first conductivity type prepared in advance, an impurity or a second conductivity type for giving a first conductivity type is formed. Single crystal semiconductor layer 4 made of a single crystal silicon layer in which any given impurities are not intentionally introduced
2 is formed by an epitaxial growth method, and
In the single crystal semiconductor layer 42, there is p-type as the first conductivity type, which becomes the single crystal semiconductor layer 1 shown in FIG. 1 from the main surface 43 side opposite to the single crystal semiconductor substrate 41 side. A semiconductor region (well) 1'is formed (FIG. 2A).

Next, on the main surface 43 side of the single crystal semiconductor layer 42, the element isolation insulating film 2 described above with reference to FIG. 1 is viewed from the side opposite to the single crystal semiconductor substrate 41 side, and the semiconductor region (well) 1 is formed. It is formed by a selective oxidation method so as to surround ′ (FIG. 3B).

Next, the single crystal semiconductor substrate 41 of the semiconductor region (well) 1'that will become the main surface 1a described above with reference to FIG.
An insulating film to be the gate insulating film 8 shown in FIG. 1 is subsequently formed on the main surface 1a 'on the side opposite to the side, and then a polycrystalline silicon layer to be the gate electrode 7 shown in FIG. 1 is formed on the insulating film. Then, the insulating film and the polycrystalline silicon layer are etched to form the gate electrode 7 shown in FIG. 1 on the semiconductor region (well) 1'via the gate insulating film 6. When viewed from the side opposite to the single crystal semiconductor substrate 41 side, the structure is formed so as to divide the semiconductor region (well) 1'into two and to extend the gate electrode 7 on the element isolation insulating film 2 ( FIG. 3C).

Next, in the semiconductor region (well) 1 ', a second mask is formed with the gate electrode 7 from the main surface 1a' side as a mask.
By the process of introducing an impurity imparting n-type as the conductivity type, the source region 3 and the drain region 4 shown in FIG. 1 are formed at both positions sandwiching the gate electrode 7 as viewed from the side opposite to the single crystal semiconductor substrate 41 side. Areas 3'and 4 '
It is formed so as to leave a region 5'become the channel region 5 shown in FIG. 1 between the regions 3'and 6 '(FIG. 3D).

Next, on the single crystal semiconductor layer 42, as shown in FIG.
The insulating film to be the first insulating film 9 shown in FIG.
And 6 ', and then the surface of the insulating film opposite to the single crystal semiconductor layer 42 side is flattened by polishing to form the insulating film 9 having the flat surface 9a shown in FIG. Formed (FIG. 4E). Next, the insulating film 9 is adhered to the substrate 30 shown in FIG. 1 on its flat surface 9a side (FIG. 4F).

Next, from the single crystal semiconductor substrate 41 side to the element isolation insulating film 2, the single crystal semiconductor substrate 41,
By removing the single crystal semiconductor layer 42, the semiconductor region (well) 1 ', the regions 3', 4'and 5 ', the semiconductor region (well) 1', the regions 3 ', 4'and 5' First and second main surfaces 1a and 1b shown in FIG.
A single crystal semiconductor layer 1, a source region 3, a drain region 4, and a channel region 5 each having an oxide are formed (FIG. 5).
G).

Next, in the channel region 5 formed in the single crystal semiconductor layer 1, the second main surface 1 of the single crystal semiconductor layer 1 is formed.
From the side b, an electrode-attached region 51 in which an impurity imparting p-type as the first conductivity type is introduced at a high concentration of 5 × 10 ¹⁹ cm ⁻³ or more is implanted with, for example, impurity ions imparting p-type. By processing, it is formed so as to be connected to the source region 3 (FIG. 5H).

Next, the second main surface 1b of the single crystal semiconductor layer 1
The second insulating film 10 described above with reference to FIG. 1 is formed thereon, and then the second insulating film 10 is provided with the electrode attachment region 51 and the drain formed in the source region 3 and the channel region 5. Window 1 shown in FIG. 1 that exposes regions 4 to the outside
3 and 14 are formed (FIG. 6I).

Next, on the second insulating film 10, both the electrode attaching region 51 formed in the source region 3 and the channel region 5 through the window 13 are connected to each other by ohmic contact, as shown in FIG. The electrode 23 for source and back gate voltage application shown is formed, and the drain region 4 is formed through the window 14.
Drain electrode 2 connected to the electrode with an ohmic junction
4 (FIG. 6J).

Although not shown, the gate electrodes 7 are formed through the second insulating film 10 and the element isolation insulating film 2 after or before the windows 13 and 14 are formed in the second insulating film 10. After forming a window (not shown) exposed to the outside, and forming a source / back gate voltage applying electrode 23 and a drain electrode 24, before or after the second insulating film 10 and element isolation. A conductive layer for leading out the gate electrode is formed which is connected to the gate electrode 7 through the window through the insulating film 2.

The above is the method of manufacturing the insulated gate field effect transistor according to the first invention of the present application described above with reference to FIG. From the above, the configuration of the insulated gate field effect transistor according to the first invention of the present application shown in FIG. 1 has been clarified.

According to the insulated gate field effect transistor of the first invention of the present application having the above structure,
Except for the matters described above, since the structure is similar to that of the conventional insulated gate field effect transistor shown in FIG. 13, it is used as a source / source like the case of the conventional insulated gate field effect transistor shown in FIG. The back gate voltage applying electrode 23 is connected to the ground, and a load (not shown) is connected between the drain electrode 24 and the source / back gate voltage applying electrode 23, and a power source whose positive electrode side is the drain electrode 24 side ( (Not shown), and the gate electrode 7
A positive voltage based on the source / back gate voltage applying electrode 23 and zero lower than the voltage between the gate electrode leading conductive layer and the source / back gate voltage applying electrode 23 connected to each other. Alternatively, if a control voltage source (not shown) that can obtain a control voltage that takes a negative voltage as binary display “1” and “0” respectively is connected, the control voltage from the control voltage source can be displayed in binary. When "0" is taken, the n-channel is hardly formed in the channel region 5 from the gate insulating film 8 side, or even if it is formed, the n-channel is slightly formed, but the control voltage from the control voltage source is 2
When taking “1” in the value display, the n-channel extends from the gate insulating film 8 side to the channel region 5 between the source region 3 and the drain region 4, and the control voltage is “0” in the binary display.
When the control voltage takes a binary value of "1" or "0", it is called an ON state between the source region 3 and the drain region 4. Can be controlled to a state which is referred to as an off state or an off state, so that the current flowing through the load has a large value.
It is possible to control whether to supply by "1" of the value display or by "0" of the binary display having a sufficiently small value.
That is, the function as an insulated gate field effect transistor can be obtained.

The source / back gate voltage applying electrode 23 is connected to the source region 3 and the electrode attaching region 51 by ohmic contact, and the electrode attaching region 51 is located in the channel region 5. Therefore, since the source / back gate voltage applying electrode 23 is connected to the channel region 5 via the electrode attaching region 51,
The back gate voltage can be applied to the channel region 5 at a value sufficiently close to the potential of the source region 3 as in the case of the conventional insulated gate field effect transistor shown in FIG. The function as a transistor can be stably obtained.

Further, since the source / back gate voltage applying electrode 23 is in ohmic contact with the electrode attaching region 51 formed in the channel region 5, the source / back gate voltage applying electrode 23 of the source / back gate voltage applying electrode 23 is formed. The connection to the channel region 5 is not via the Schottky junction as in the case of the conventional insulated gate field effect transistor shown in FIG. 13, but via the electrode attachment region 51. In, the depletion layer extending from the source / back gate voltage applying electrode 23 side is not formed.

Therefore, the so-called short channel effect, such as the threshold voltage and the transconductance of the insulated gate field effect transistor which can be obtained only at a low value, is also shown in FIG.
It is possible to effectively avoid the possibility that it may occur as in the case of the conventional insulated gate field effect transistor shown in FIG.

[0042]

Second Embodiment Next, with reference to FIG.
An embodiment of an insulated gate field effect transistor according to the second invention will be described.

The insulated gate field effect transistor according to the second invention of the present application shown in FIG. 7 is shown by attaching the same reference numerals to the portions corresponding to those in FIG. 1, and detailed description thereof will be omitted.
As in the case of the conventional insulated gate field effect transistor shown in FIG. 4, in the single crystal semiconductor layer 1, the source region 3 and the drain region 4 leave the channel region 5 between them from the first major surface 1a side. Instead of being formed to a depth reaching the second main surface 1b, in the single crystal semiconductor layer 1,
(A) As the second conductivity type in which the source region 3 similar to that described above from the first main surface 1a side and the impurity imparting n-type as the second conductivity type are introduced at a relatively low concentration n
The offset region 6 having a mold is formed to a depth reaching the second main surface 1b so as to leave the channel region 5 similar to that described above between them, and the first main surface 1a side From the drain region 4 similar to that described above.
According to the first invention of the present application shown in FIG. 1, except that the offset region 6 is formed so as to be connected to the side opposite to the channel region 5 side and reach the second main surface 1b. It has a structure similar to that of the insulated gate field effect transistor.

The insulated gate field effect transistor according to the second invention of the present application shown in FIG. 6 corresponds to the manufacturing method of the insulated gate field effect transistor according to the first invention of the present application shown in FIG. It can be manufactured by the embodiment of the manufacturing method described below with reference to FIG.

8 to 12, parts corresponding to those in FIGS. 2 to 6 are designated by the same reference numerals, and detailed description thereof will be omitted. The method for producing the insulated gate field effect transistor according to the second invention of the present application shown in FIGS. 8 to 12 is the same as the method for producing the insulated gate field effect transistor according to the first invention of the present application shown in FIGS. Then, the single crystal semiconductor layer 42 is formed on the single crystal semiconductor substrate 41, and the single crystal semiconductor layer 42 is formed.
A semiconductor region (well) 1'is formed therein (FIG. 8A).

Next, as in the case of the method of manufacturing the insulated gate field effect transistor according to the first invention of the present application shown in FIGS. 2 to 6, an insulating film for element isolation is formed on the main surface 43 side of the single crystal semiconductor layer 42. 2 is formed (FIG. 9B).

Next, as in the case of the method for manufacturing the insulated gate field effect transistor according to the first invention of the present application shown in FIGS. 2 to 6, the gate is formed on the main surface 1a 'of the semiconductor region (well) 1'. A structure in which the electrode 7 is formed via the gate insulating film 6 is formed (FIG. 9C).

Next, in the semiconductor region (well) 1 ', a second mask with the gate electrode 7 from the main surface 1a' side as a mask is used.
By the introduction process of the impurity that gives the n-type as the conductivity type, the offset region shown in FIG. 7 is formed on one side of the two regions divided by the gate electrode 7 when viewed from the side opposite to the single crystal semiconductor substrate 41 side. Forming a region 6'to become 6,
Next, in the semiconductor region (well) 1'and the region 6 ', an n-type as a second conductivity type is provided with the gate electrode 7 from the main surface 1a' side of the semiconductor region (well) 1'as a mask. By the impurity introduction process, the regions 3'and 4'to be the source region 3 and the drain region 4 shown in FIG. 7 are formed at both positions sandwiching the gate electrode 7 as viewed from the side opposite to the single crystal semiconductor substrate 41 side. It is formed so as to leave a region 5'become the channel region 5 shown in FIG. 7 between the regions 3'and 6 '(FIG. 9D).

Next, according to the method of manufacturing the insulated gate field effect transistor according to the first invention of the present application shown in FIGS. 2 to 6, the insulating film having the flat surface 9a on the single crystal semiconductor layer 42. 9 (FIG. 10E).

Next, as in the case of the method of manufacturing the insulated gate field effect transistor according to the first invention of the present application shown in FIGS. 2 to 6, the insulating film 9 is provided on the flat surface 9a side of the support substrate 30. (FIG. 10F).

Next, according to the method of manufacturing the insulated gate field effect transistor according to the first invention of the present application shown in FIGS. 2 to 6, from the single crystal semiconductor substrate 41 side to the element isolation insulating film 2. Is removed to form the single crystal semiconductor layer 1, the source region 3, the drain region 4 and the channel region 5 from the semiconductor region (well) 1 ', the regions 3', 4'and 5 '(FIG. 11G).

Then, in the same manner as in the method of manufacturing the insulated gate field effect transistor according to the first invention of the present application shown in FIGS. 2 to 6, in the channel region 5 formed in the single crystal semiconductor layer 1, From the second main surface 1b side of the single crystal semiconductor layer 1, an electrode attachment region 51 into which an impurity imparting p-type conductivity is introduced at 5 × 10 ¹⁹ cm ⁻³ or more is formed so as to be connected to the source region 3 ( FIG. 11H).

Next, according to the method of manufacturing the insulated gate field effect transistor according to the first invention of the present application shown in FIGS. 2 to 6, on the second main surface 1b of the single crystal semiconductor layer 1,
A second insulating film 10 having windows 13 and 14 for exposing the electrode attachment region 51 formed in the source region 3 and the channel region 5 and the drain region 4 to the outside is formed (FIG. 11I).

Next, as in the case of the method of manufacturing the insulated gate field effect transistor according to the first invention of the present application shown in FIGS. 2 to 6, windows 13 and 14 are formed on the second insulating film 10.
And the electrode-attached region 51 formed in the source region 3 and the channel region 5, respectively, and the source / back gate voltage application electrode 23 connected to the drain region 4 by ohmic junction, respectively, and The drain electrode 24 is formed (FIG. 11J).

Although not shown, the second insulating film 10 and the element isolation insulating film 2 are formed in the same manner as in the method of manufacturing the insulated gate field effect transistor according to the first invention of the present application shown in FIGS. A conductive layer for leading the gate electrode is formed, which is connected to the gate electrode 7 through the window through which the gate electrode 7 is drawn.

The above is the manufacturing method of the insulated gate field effect transistor according to the second invention of the present application described above with reference to FIG. From the above, the configuration of the insulated gate field effect transistor according to the second invention of the present application shown in FIG. 7 has been clarified.

According to the embodiment of the insulated gate field effect transistor having the above-described second invention of the present application, the insulated gate according to the first invention of the present application shown in FIG. 1 is provided except for the matters described above. Since it has the same structure as that of the field effect transistor of the present invention, detailed description thereof will be omitted, but it is clear that the same action and effect as those of the insulated gate field effect transistor according to the first invention of the present application shown in FIG. 1 can be obtained. Is.

Further, in the case of the insulated gate field effect transistor according to the second invention of the present application shown in FIG. 7, the channel region 5 and the drain region 4 are similar to the case of the conventional insulated gate field effect transistor shown in FIG. Since the offset region 6 is interposed between them, the breakdown voltage between the source / back gate voltage applying electrode 23 and the drain electrode 24 is prevented by the offset region 6 being interposed between the channel region 5 and the drain region 4. This is higher than the case of the insulated gate field effect transistor according to the first invention of the present application shown in FIG. 1 which is not provided, so that a load is applied between the source / back gate voltage applying electrode 23 and the drain electrode 24. The offset region 6 is interposed between the channel region 5 and the drain region 4 to limit the voltage of the power source connected through the There is not, compared to the case of an insulated gate field effect transistor according to the present 1st invention shown in FIG. 1, it may be alleviated.

In the above description, only a few embodiments are described for each of the insulated gate field effect transistors according to the first invention and the second invention of the present application. For example, in the channel region 5. In the figure, the electrode attachment region 51 formed in FIG. 2 is formed in the channel region 5 with a part of the side opposite to the source region 3 side being left. It can be formed without leaving the source region 3 side,
In some cases, it may be formed so as to extend into the source region 3 and the drain region 4 or the offset region 6, and other various modifications and alterations can be made without departing from the spirit of the present invention. Ah

[0060]

According to the second aspect of the single crystal semiconductor layer in the channel region,
A region with an electrode having a higher impurity concentration than the channel region is formed in the main surface side of the source, and the source / back gate voltage applying electrode is connected to the source region through an ohmic junction, thereby Since the connection of the application / back gate voltage applying electrode to the channel region is not via the Schottky junction but via the electrode attaching region, the channel region is used for the source / back gate voltage applying It is possible to effectively avoid the possibility that the depletion layer extending from the electrode is not formed and thus the short channel effect is produced.

[Brief description of drawings]

FIG. 1 is a schematic cross-sectional view showing an embodiment of an insulated gate field effect transistor according to the first invention of the present application.

FIG. 2 is a schematic cross-sectional view in sequential steps, which is used for explaining a manufacturing method of the embodiment of the insulated gate field effect transistor according to the first invention of the present application shown in FIG.

3 is a schematic cross-sectional view in a sequential process subsequent to the sequential process shown in FIG. 2 for explaining the manufacturing method of the embodiment of the insulated gate field effect transistor according to the first invention of the present application shown in FIG. Is.

FIG. 4 is a schematic cross-sectional view in a sequential process that follows the sequential process shown in FIG. 3 for explaining the manufacturing method of the embodiment of the insulated gate field effect transistor according to the first invention of the present application shown in FIG. Is.

5 is a schematic cross-sectional view in a sequential process subsequent to the sequential process shown in FIG. 4 for explaining the manufacturing method of the embodiment of the insulated gate field effect transistor according to the first invention of the present application shown in FIG. Is.

6 is a schematic cross-sectional view in a sequential process that follows the sequential process shown in FIG. 5 for explaining the manufacturing method of the embodiment of the insulated gate field effect transistor according to the first invention of the present application shown in FIG. Is.

FIG. 7 is a schematic cross-sectional view showing an embodiment of an insulated gate field effect transistor according to the second invention of the present application.

8A and 8B are schematic cross-sectional views in sequential steps, which are used for explaining a method for manufacturing the insulated gate field effect transistor according to the second aspect of the invention shown in FIG.

9 is a view for explaining a method of manufacturing the insulated gate field effect transistor according to the second invention of the present application shown in FIG.
FIG. 6 is a schematic cross-sectional view in a sequential process that follows the sequential process shown in FIG.

FIG. 10 is a schematic cross-sectional view in a sequential step that follows the sequential step shown in FIG. 9 for explaining the method for manufacturing the insulated gate field effect transistor according to the second aspect of the present invention shown in FIG. 7.

FIG. 11 is a schematic cross-sectional view in a sequential step that follows the sequential step shown in FIG. 10 for explaining the method for manufacturing the insulated gate field effect transistor according to the second aspect of the present invention shown in FIG. 7.

FIG. 12 is a schematic cross-sectional view in a sequential step that follows the sequential step shown in FIG. 11 for explaining the method for manufacturing the insulated gate field effect transistor according to the second aspect of the present invention shown in FIG. 7.

FIG. 13 is a schematic cross-sectional view showing one of conventional insulated gate field effect transistors.

FIG. 14 is a schematic cross-sectional view showing another one of the conventional insulated gate field effect transistors.

[Description of Reference Signs] 1 single crystal semiconductor layer 1'semiconductor region (well) 1a, 1b main surface of single crystal semiconductor layer 2 isolation insulating film 3 source region 4 drain region 5 channel region 6 offset region 7 gate electrode 8 Gate insulating film 9, 10 Insulating film 9a Flat surface 13, 14 of insulating film 9 Window 23 Source and back gate voltage applying electrode 24 Drain electrode 30 Support substrate 31 Conductive layer 41 Single crystal semiconductor substrate 42 Single crystal semiconductor layer Area for 51 electrodes

─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Yoshihiro Arimoto 4-1-1 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Within Fujitsu Limited (72) Inventor Akio Ito 4-chome, Ueda-anaka, Nakahara-ku, Kawasaki, Kanagawa No. 1-1 No. 1 within Fujitsu Limited (56) Reference JP-A-9-74202 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 29/786 H01L 21/336

Claims (3)

(57) [Claims] 1. A single crystal semiconductor layer having first and second main surfaces and having a first conductivity type is provided, wherein a single crystal semiconductor layer is formed in the single crystal semiconductor layer from the first main surface side. 1
A source region and a drain region having a second conductivity type opposite to the second conductivity type are formed to a depth reaching the second main surface so as to leave a channel region therebetween. A gate electrode is formed on the first main surface so as to face the channel region via a gate insulating film, and a first insulating film is formed to cover the gate electrode and the gate insulating film. A surface of the first insulating film opposite to the single crystal semiconductor layer side is a flat surface, and the first insulating film is bonded to a support substrate on the flat surface side. A second insulating film is formed on the second main surface of the single crystal semiconductor layer, and the source / back gate voltage connected to the source region and the channel region is formed on the second insulating film. Insulation gate with application electrode In the type field effect transistor, an impurity imparting the first conductivity type is introduced into the channel region in the second main surface side of the single crystal semiconductor layer at a higher concentration than in the channel region. An electrode-attached region having a conductivity type is formed, and the source / back gate voltage application electrode is connected to the source region by ohmic junction to the source region. The applying electrode is ohmic-joined to the electrode-attached region, so that the connection of the source / back gate voltage-applying electrode to the channel region is a connection via the electrode region. Insulated gate field effect transistor. 2. A single crystal semiconductor layer having first and second main surfaces and having a first conductivity type, wherein a single crystal semiconductor layer is formed in the single crystal semiconductor layer from the first main surface side. The source region having the second conductivity type and the impurity imparting the second conductivity type are introduced at a relatively low concentration in which the impurity imparting the second conductivity type opposite to the first conductivity type is introduced at a relatively high concentration. The offset region having the second conductivity type being introduced so as to leave a channel region therebetween.
A drain region having a second conductivity type, which is formed to a depth reaching the main surface of the second conductivity type and in which an impurity imparting the second conductivity type is introduced at a relatively high concentration from the first main surface side. Is formed so as to be connected to the offset region on a side opposite to the channel region side and reach a depth reaching the second main surface, and a gate electrode is formed on the first main surface of the single crystal semiconductor layer. The first insulating film is formed to face the channel region with an insulating film interposed therebetween, and the first insulating film is formed to cover the gate electrode and the gate insulating film.
The surface of the first insulating film opposite to the single crystal semiconductor layer side is a flat surface, and the first insulating film is bonded to the support substrate on the flat surface side, A second insulating film is formed on the second main surface of the single crystal semiconductor layer,
In the insulated gate field effect transistor, wherein an electrode for source and back gate voltage application connected to the source region and the channel region is formed on the second insulating film, the single crystal of the channel region In the second main surface side of the semiconductor layer, an impurity imparting the first conductivity type is introduced at a higher concentration than that of the channel region.
A region with an electrode having a conductivity type is formed, and the connection of the source / back gate voltage applying electrode to the source region is a connection by ohmic contact to the source region. Since the voltage application electrode is in ohmic contact with the electrode attachment region, the source / back gate voltage application electrode is connected to the channel region through the electrode attachment region. An insulated gate field effect transistor characterized by: 3. The insulated gate field effect transistor according to claim 1 or 2, wherein the single crystal semiconductor layer is a single crystal silicon layer, and the channel region is
The impurity concentration is less than 1 × 10 ¹⁸ cm ⁻³ , the source region and the electrode attachment region have an impurity concentration of 5 × 10 ¹⁹ cm ⁻³ or more, and also for the source and the back gate voltage application. The electrodes are molybdenum, scandium, europium, yttrium, titanium, hafnium, vanadium,
An insulated gate field effect transistor characterized by comprising a metal selected from chromium, lead, nickel, platinum, cobalt, tungsten, and aluminum, or a silicide or nitride thereof.