JP3370903B2 - Photomask group for manufacturing semiconductor device and method of manufacturing semiconductor device using the same - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which a large-capacity memory such as DRAM and a logic product such as a microprocessor or ASIC are integrated on a semiconductor substrate, a photomask for manufacturing the semiconductor device, and a photomask thereof. The present invention relates to a method for manufacturing a semiconductor device.

[0002]

2. Description of the Related Art In recent years, in semiconductor devices, general-purpose DRAM, general-purpose synchronous DRAM, microprocessor and AS
A system including an IC or the like is integrated on a single chip. In the following, a general-purpose DRAM or a general-purpose synchronous DRAM will be referred to as a DRAM. The microprocessor and ASIC are called logic. Integrating a system composed of DRAM, logic, etc. on a single chip is called mixed mounting. By embedding the DRAM and the logic in a single chip, the data transfer rate between the DRAM and the logic is improved and the power consumption is reduced.

A conventional mixed semiconductor device and a method of manufacturing the same will be described with reference to FIGS.
FIG. 20 shows a schematic layout of a conventional mixed semiconductor device. The mixed semiconductor device 1'is
It has a DRAM block 2'and a logic block 3'arranged around the DRAM block 2 ', other than the DRAM. FIG. 21 shows an outline of a photomask used for exposure. This photomask is made of quartz glass 1
A chrome-based material is vapor-deposited on the light-shielding portion in accordance with various data. The data section 107 is an area in which data of the semiconductor device is arranged. Frame data
The section 106 ' is an area in which frame data that blocks light around the area corresponding to the logic block 3'is arranged. The first alignment pattern 109 is used for alignment between the photomask and the exposure device.
The second alignment pattern 110 is used for alignment between photomasks. However, as many photomasks as the number of mask processes are required according to the layout data of the semiconductor device 1 '.

Frame data section 106 ' , first alignment pattern 109, second alignment pattern 1
The 10 and the quartz glass 100 are not directly related to the function of the semiconductor device 1 ′, and their size, shape, and arrangement position are defined according to the specifications of the exposure apparatus used. Further, since the reduced projection exposure is performed, the size of the data portion 107 is formed to be five times the size of the semiconductor device 1 ′, and the reduced projection exposure is performed to ⅕ at the time of exposure. Further, FIG. 21 shows a case where data for two chips is arranged on the photomask, but the number of chips arranged on the photomask is determined according to the performance of the exposure apparatus and the chip size.

FIG. 22 shows an outline of a process flow in a manufacturing process of a mixed semiconductor device. This process flow includes a transistor forming step, a capacitance forming step, and a wiring forming step. DRAM The capacitance forming process of each step is a step carried out for the high integration of the memory cell region,, called a stacked
Is a unique process.

FIG. 23 and FIG. 24 show process cross-sectional views at typical portions of a DRAM block and a logic block, taking the first layer wiring forming process as an example. In this process sectional view, the semiconductor substrate 201, the diffusion layer 202, and the gate electrode 2 are shown.
03, polycide bit line 204, capacitance electrode pair 20
5, 206, the interlayer film 207, the contact hole 208,
A metal 209 deposited over the entire main surface of the semiconductor substrate and a resist 210 applied over the entire main surface of the semiconductor substrate are included. The shaded area of the photomask 304 for the wiring forming process indicates a light shielding area. As shown in FIG. 23, the exposure apparatus uses the light 300 having a predetermined wavelength to expose the photomask 3
The resist 210 is exposed using 04. After exposure by the exposure device, resist development, metal etching, and resist removal are performed to form metal wiring 211, as shown in FIG.

[0007]

Generally, in order to form a fine pattern, it is necessary to focus the exposure apparatus on a register coated on a semiconductor substrate when the exposure apparatus performs exposure. However, in the wiring forming process shown in FIG. 23, there is a large step of height h (FIG. 23) in the memory cell region of the DRAM block and other regions, and DR
It was impossible to focus the exposure on both the AM block and the logic block at the same time. For this reason, the wiring rule of the metal wiring (metal wiring pitch L in FIG. 24) has to be looser than the miniaturization ability defined by the performance of the exposure apparatus or the like. Therefore, it has been a big problem that the degree of integration of the logic block which uses a lot of metal wiring cannot be increased.

Further, variations and defects in the photomask pattern are directly reflected in the pattern of the semiconductor device. For this reason, a very high precision photomask is required for a large-capacity DRAM that has been miniaturized. In addition, there is also a step in which a special photomask such as a phase shift mask is required for miniaturization. Generally, such photomasks are very expensive. In the mixed semiconductor device, the specifications of the DRAM block are limited, but the specifications of the logic block differ depending on the application and customer.
Mixed semiconductor devices are products that produce a large number of various products in small quantities. For this reason, in a mixed semiconductor device, it is necessary to prepare an expensive photomask for each product for all processes including the electrostatic capacitance forming process, resulting in a significant increase in cost.

Furthermore, since DRAM block is large, the data constituting the layout data of the semiconductor equipment is enormous. Therefore, the time required to convert the layout data into the format data for the photomask manufacturing apparatus and the time required to manufacture the photomask become long,
There was a problem that the development period took a long time.

It is an object of the present invention to provide a semiconductor device and a method for manufacturing the same, which increase the degree of integration of the mixed semiconductor devices and which do not increase the development cost.

[0011]

The photomask group of the present invention includes memory cells
Has writing to said memory cell and said memory cell
Memory block for reading from the
Control the memory block, which is arranged with a space
Logic block, the memory block, and
A signal line connected to the Zick block;
A photomask set for the body device fabrication, a second photomask for the first photo mask for forming the memory blocks, shields the placement region before Symbol memory blocks forming said logic block When, comprising a front Symbol third photomask without shielding the arrangement region of the light shielding by the logic block arrangement region of the memory block.
By preparing the photomask group as described above, it is possible to highly integrate the semiconductor device and to manufacture the semiconductor device without increasing the development cost.

The method of manufacturing a semiconductor device according to the present invention comprises the steps of applying a resist on the main surface of a semiconductor substrate and then exposing the resist using the first photomask, and using the second photomask. The resist is developed after two steps including exposing the resist to light. In the memory block and the logic block, exposure can be performed with the optimum exposure focus.

Another invention of a method of manufacturing a semiconductor device comprises a step of applying a resist on a main surface of a semiconductor substrate and then exposing the resist using the first photomask, and a step of exposing the third photomask. The resist is developed after two steps including a step of exposing the resist using the resist. In the memory block and the logic block, exposure can be performed with the optimum exposure focus.

Still another invention of a method of manufacturing a semiconductor device comprises: exposing the resist using the first photomask; and exposing the resist using the second photomask. The exposure is performed at the optimum exposure focus for the photomask used in the process. In the memory block and the logic block, the resist is exposed with the optimum exposure focus, so that the semiconductor device can be highly integrated.

Still another invention of a method of manufacturing a semiconductor device comprises: exposing the resist using the first photomask; and exposing the resist using the third photomask. The exposure is performed at the optimum exposure focus for the photomask used in the process. In the memory block and the logic block, the resist is exposed with the optimum exposure focus, so that the semiconductor device can be highly integrated.

In still another invention of the method of manufacturing a semiconductor device, the memory block and the logic block are formed by different pattern forming rules, and the step of exposing the resist using the first photomask and the second step. In the step of exposing the resist using the photomask of (1), the photomask used in each step is exposed with an optimum exposure focus. In the memory block and the logic block, the resist is exposed with the optimum exposure focus, so that the semiconductor device can be highly integrated.

In another invention of the photomask group, at least one of the regions forming the signal line of the first photomask and the second photomask has the first width within a predetermined width of the signal line. Of the photomask and the second photomask, which has a width wider than the sum of the mask alignment accuracy. By configuring the photomask as described above,
A signal line having a desired width can be formed.

In still another invention of the photomask group, a boundary line of a region of the first photomask other than the memory block is shaded and a boundary line of a region of the second photomask is shaded in the memory block. And are not the same.
By configuring the photomask as described above, a short circuit between signal lines can be prevented.

[0020]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. << Embodiment 1 >> A semiconductor device and its manufacturing apparatus in Embodiment 1 of the present invention will be described with reference to FIGS. <Structure> FIG. 1 shows a schematic layout of a semiconductor device according to the first embodiment. Mixed semiconductor device 1
Is a DRAM block 2, a logic block 3, a D
A separation band 4 having a predetermined width that separates the RAM block 2 and the logic block 3 and a metal wiring 5 that connects the DRAM block 2 and the logic block 3 are provided. The chip size of the semiconductor device 1 is Lx in the X direction and Ly in the Y direction. The DRAM block 2 is composed of a memory cell array of a predetermined capacity, a decoder, a sense amplifier and its control circuit.

FIG. 2 schematically shows a terminal specification diagram of the DRAM block 2. The DRAM block 2 includes a power source, a ground, an address signal, an input signal, an output signal (hereinafter, the input signal and the output signal are collectively referred to as an I / O signal), a DR.
The configuration is controlled by the AM control signal. These signals are input from the logic block 3 via the metal wiring 5 and output via the metal wiring 5. 128 for example
Bit output configuration 16Mbit DRAM, DRAM
Block 2 has 17 terminals for address signals and 128 terminals.
About 150 terminals including terminals for I / O signals of a book are provided. In this case, 150 metal wirings 5 are provided. The process of manufacturing this semiconductor device is similar to the conventional process shown in FIG. DRAM block 2
Is a structure formed by a transistor forming step, a capacitance forming step, and a wiring forming step. The logic block 3 has a configuration formed by a transistor forming process and a wiring forming process.

<Photomask> As the photomask, there are a photomask for patterning the logic block 3 and a photomask for patterning the DRAM block 2. The details of these photomasks will be described below. . FIG. 3 shows an outline of a photomask (hereinafter referred to as a logic mask) for forming the pattern of the logic block 3. This logic mask has data of two chips arranged on a quartz glass 100 of a predetermined size. Has been done. The DRAM block unit 101 is
This is an area in which data for shielding the area corresponding to the DRAM block 3, the separation band 4 and the metal wiring 5 is arranged. The logic block unit 102 is an area in which data for logic blocks is arranged. Frame data section 106
Is an area in which frame data for shielding the area corresponding to the periphery of the logic block 2 is arranged. The first alignment pattern 103 is used for aligning the logic mask with the exposure apparatus. The second alignment pattern 104 is used for alignment between logic masks.

Further, the DRAM block section 101 will be described. The area inside the broken line 101a is the area corresponding to the DRAM block 3, and the area outside the broken line 101a is the area corresponding to the separation band 4 and the metal wiring 5.
The third alignment pattern 105 is used to align the logic mask with the DRAM block. The broken line 101a is shown for the sake of explanation, and does not mean that a dotted line pattern exists in the logic mask. The same applies to FIGS. 5 and 19. The frame data section 106, the first alignment pattern 103, and the second alignment pattern 104 are arranged according to the same arrangement rule as the conventional example (FIG. 21). The number of logic masks is as many as the number of mask steps in the transistor forming step and the wiring forming step.

FIG. 4 shows an outline of a photomask (hereinafter referred to as a DRAM mask) for patterning the DRAM block 2. In this DRAM mask, data for one chip is arranged on quartz glass 100 of a predetermined size. The DRAM block unit 107 is a DRAM
This is an area in which data for blocks is arranged. In the DRAM mask used in the metal process, the separation band portion 108 is an area where wiring data for connecting the DRAM block and the logic block is arranged. However, the separation band portion 108 is a DRA used in other than the metal process.
In M mask, depending on the process and device specifications,
Data to be shielded or transmitted is arranged. The frame data portion 106a is an area in which frame data for shielding the area corresponding to the periphery of the separation band 4 is arranged. The first alignment pattern 103a is used for aligning the DRAM mask with the exposure apparatus. The second alignment pattern 104a is used for alignment between DRAM masks. The third alignment pattern 105a corresponds to the third alignment pattern 105 of the logic mask, and is used for mask alignment of the DRAM mask with the logic block. The frame data portion 106a, the first alignment pattern 103a, and the second alignment pattern 104a are arranged according to the same arrangement rule as in the conventional example (FIG. 21). The number of DRAM masks is the same as the number of mask steps in the transistor forming step, the wiring forming step, and the capacitance forming step.

FIG. 5 shows the logic block unit 102a.
A photo mask (hereinafter referred to as a logic auxiliary mask) in which data for a logic block is not arranged is shown. The configuration other than the logic block unit 102a is
It is similar to the logic mask. The logic auxiliary mask is
It is used to remove the deposited layer in the logic block region among the deposited layers deposited in each step in the capacitance forming step. The logic auxiliary mask can be shared by one logic auxiliary mask in each capacitance forming process.

<Manufacturing Method> A method of manufacturing a semiconductor device using the photomasks of FIGS. 3 to 5 will be described below. [Transistor forming step and wiring forming step] The transistor forming step and the wiring forming step will be described. FIG. 6 shows a manufacturing process for a transistor forming process and a wiring forming process. A logic mask and a DRAM mask are used in this manufacturing process. A resist is applied to the entire main surface of the semiconductor substrate (step S061). Alignment of the logic mask and exposure equipment is the first step of the logic mask.
This is performed by the same method as the conventional method using the alignment pattern 103 of. The alignment of the logic block is the second alignment pattern 10 of the logic mask.
4 is used. If necessary, the alignment of the logic block is corrected using the third alignment pattern 105 of the logic mask. The resist applied on the entire main surface of the semiconductor substrate is exposed at a pitch of Lx in the X direction and (2 × Ly) in the Y direction using a logic mask (step S062).

The alignment between the DRAM mask and the exposure device is performed by the first alignment pattern 10 of the DRAM mask.
3a is used in the same manner as the conventional method. DRA
Alignment of M blocks is performed using the second alignment pattern 104a of the DRAM mask. If necessary, the alignment of the DRAM block is corrected using the third alignment pattern 105a of the DRAM mask. The resist applied on the entire main surface of the semiconductor substrate is exposed using a DRAM mask at a chip size pitch of the semiconductor device, that is, a pitch of Lx in the X direction and Ly in the Y direction (step S063). Only the alignment of the DRAM block in the first mask process,
This is performed on the basis of the information on the relative positional relationship of the DRAM block 2 with respect to the logic block 3 which is known at the design stage of the semiconductor device 1. Resist development (step S064), etching (step S065), and resist removal (step S)
066) is performed to form a resist pattern.

Regarding the above-mentioned transistor forming step and wiring forming step, the wiring forming step of the first layer will be taken as an example to mainly explain the exposure performed using the logic mask and the DRAM mask. 7, 8 and 9 show process cross-sectional views of the wiring process of the first layer at typical portions of the DRAM block and the logic block. In this process sectional view, the semiconductor substrate 201, the diffusion layer 202, the gate electrode 203, the polycide bit line 204, and the capacitance electrode pair 205, 20.
6, the interlayer film 207, the contact hole 208, the metal 209 entirely deposited on the main surface of the semiconductor substrate, the resist 210 applied on the entire main surface of the semiconductor substrate, and the metal wiring 21.
1 is included. Logic mask 30 for metal process
1 and the shaded portion of the DRAM mask 302 indicate a light shielding region.

As shown in FIG. 7, the exposure apparatus exposes the resist 210 with the light 300 having a predetermined wavelength using the logic mask 301. Here, since the logic block is formed only in a region having a low level difference between the transistor and the wiring, the exposure focus of the exposure apparatus is set to the logic block having a low level difference. Therefore, it is possible to form a finer wiring pattern (metal wiring pitch L1 in FIG. 7) than the conventional one. Note that the DRAM block is not exposed. As shown in FIG. 8, the exposure apparatus exposes the resist 210 with the light 300 having a predetermined wavelength using the DRAM mask 302. In the DRAM block 2, a region having a high level difference forming an electrostatic capacity and a region having a low level difference forming a transistor such as a sense amplifier and wiring are mixed. Therefore, DRA
Wiring pattern of M block (metal wiring pitch L in FIG. 8)
2) is the same wiring pattern as the conventional one. The logic block 3 is not exposed because it is outside the exposure area of the DRAM mask. After that, resist development, metal etching, and resist removal are performed to form metal wirings 211 as shown in FIG.

[Capacitance Forming Step] The capacitance forming step will be described. FIG. 10 shows a manufacturing process for the capacitance forming process. A logic auxiliary mask and a DRAM mask are used in this manufacturing process. A resist is applied to the entire main surface of the semiconductor substrate (step S10).
1). The alignment between the logic mask and the exposure apparatus is performed by using the first alignment pattern 103 of the logic mask by the same method as the conventional method. Alignment of the logic block is performed using the second alignment pattern 104 of the logic auxiliary mask. If necessary, the alignment of the logic block is corrected by using the third alignment pattern 105 of the logic auxiliary mask. The resist applied on the entire main surface of the semiconductor substrate is exposed at a pitch of Lx in the X direction and (2 × Ly) in the Y direction using a logic auxiliary mask (step S102).

The alignment between the DRAM mask and the exposure apparatus is performed by the first alignment pattern 10 of the DRAM mask.
3a is used in the same manner as the conventional method. DRA
Alignment of M blocks is performed using the second alignment pattern 104a of the DRAM mask. If necessary, the alignment of logic blocks is corrected using the third alignment pattern 105a of the DRAM mask. The resist applied on the entire main surface of the semiconductor substrate is exposed using a DRAM mask at a chip size pitch of the semiconductor device, that is, a pitch of Lx in the X direction and Ly in the Y direction (step S103). Resist development (step S104), etching (step S105), and resist removal (step S106) are performed to form a resist pattern.

With respect to the above-mentioned capacitance forming process, the formation of the polycide bit line will be taken as an example, and the exposure performed by using the logic auxiliary mask and the DRAM mask will be mainly described. 11, 12 and 13 show process cross-sectional views of the formation of the polycide bit line at typical locations of the DRAM block and the logic block. In this process sectional view, the semiconductor substrate 201, the diffusion layer 202, and the gate electrode 20 are shown.
3. Polycide 20 entirely deposited on the main surface of the semiconductor substrate
4a, a resist 21 applied over the entire main surface of the semiconductor substrate
0 and polycide bit lines 204 are included. The shaded areas of the logic auxiliary mask 303 and the DRAM mask 302a indicate light-shielding areas. As shown in FIG. 11, the exposure apparatus exposes the resist 210 with the light 300 having a predetermined wavelength using the logic auxiliary mask 303.
However, the DRAM block 2 is not exposed. 12
As shown in, the exposure apparatus is a DRA for polycide process.
The resist 210 is exposed to light 300 having a predetermined wavelength using the M mask 14. However, the logic block is D
It is not exposed because it is outside the exposure area of the RAM mask.
Thereafter, resist development, polycide etching, and resist removal are performed to form polycide bit lines 204 as shown in FIG.

[Wiring Method] A wiring method of the metal wiring 5 connecting the DRAM block 2 and the logic block 3 will be described with reference to FIGS. 14 to 17. FIG. 14 shows a DRAM
The respective shapes in the vicinity of the boundary area of the mask and the logic mask are shown. The DRAM mask has linear wiring patterns Da1 and Db1 having a constant width. The logic mask has linear wiring patterns La1 and Lb1 having a constant width.

The shape of the wiring formed by using the DRAM mask and the logic mask shown in FIG. 14 will be described below. DRAM for the alignment position of the logic mask
If the alignment position of the mask is not displaced, the wirings a and b
Is formed as a linear wiring having a desired width ((a) of FIG. 15). However, logic mask and DRA
The following problems occur depending on the positional relationship of the M mask. When the alignment position of the DRAM mask deviates from the alignment position of the logic mask by the distance X in the right direction in FIG. 14, the wirings a and b cannot secure a desired width in the boundary region ((of FIG. 15). b)). The alignment position of the DRAM mask with respect to the alignment position of the logic mask is
When the distance Y is shifted upward in FIG. 14, a region which is not exposed is generated in the boundary region in the logic mask process and the DRAM mask process, and the wirings a and b are short-circuited (FIG. 15C). DRA for logic mask alignment position
When the alignment position of the M mask is displaced downwardly by the distance Y in FIG. 14, the M mask is exposed twice in the logic mask process and the DRAM mask process in the vicinity of the boundary region other than the wiring part on the logic block side. Therefore, the wirings a and b cannot secure a predetermined width near the boundary area ((d) of FIG. 15). As described above, when the DRAM mask and the logic mask shown in FIG. 14 are used, the desired wiring cannot be formed with the current mask alignment accuracy. In addition,
When the accuracy of mask alignment is improved, D shown in FIG.
It is possible to form a desired wiring by using a RAM mask and a logic mask.

The shapes of the DRAM mask and the logic mask for solving the above problems will be described with reference to FIGS. The DRAM mask has a length (Y1 + Y
The area 2) is provided with wiring patterns Da2 and Db2 having a portion having a width (2 × X1) wider than a desired wiring width and a portion having a desired wiring width. Light-shielding area of DRAM mask (that is, frame data portion 106 of DRAM mask)
The distance a) is set back by a distance Y2 with respect to the boundary line. Similar to the case of FIG. 14, the logic mask has linear wiring patterns La2 and Lb2 having a constant width.

DRA for the alignment position of the logic mask
When the alignment positions of the M masks are not displaced, the wirings a and b are formed as wirings each having a desired wiring width ((a) of FIG. 17). When the alignment position of the DRAM mask deviates from the alignment position of the logic mask by a distance X (X1 or less) to the right in FIG.
Can secure a desired wiring width even in the boundary region ((b) of FIG. 17). When the alignment position of the DRAM mask deviates from the alignment position of the logic mask in the upward direction in FIG. 16 by a distance Y (Y2 or less), the wirings a and b may be short-circuited as shown in FIG. No (FIG. 17 (c)). When the alignment position of the DRAM mask deviates from the alignment position of the logic mask by the distance Y (Y1 or less) in the downward direction in FIG. 16, there is no region exposed twice in the logic mask process and the DRAM mask process, and the wiring a And b can secure a desired wiring width ((d) of FIG. 17). Therefore, in the semiconductor device, the logic mask and the DRAM mask, if the widths of X1, Y2 and the separation band are set to δ or more and Y1 is set to (δ + the minimum line width of the wiring) or more, the logic mask and the DRAM of FIG.
The problem of using a mask can be solved.
Note that δ indicates a relative mask misalignment of the DRAM mask with respect to the logic mask.

The alignment of the DRAM block 2 is D
Performed at only DRAM block 2 with the second alignment pattern 104 a of the RAM mask. For this reason,
The deviation of the mask alignment between the layers of the DRAM block 2 is very small. Usually, the misalignment of mask alignment is
It is 0.1 μm to 0.2 μm or less. The alignment of the logic block 3 is performed only by the logic block 3 using the second alignment pattern 104 of the logic mask 3. Therefore, the mask misalignment between the layers of the logic block 3 is very small. Normal,
The mask misalignment is 0.1 μm to 0.2 μm or less. The alignment of the DRAM block 2 with the logic block 3 is performed in the first step.
This is performed based on the information on the relative positional relationship of the DRAM block 2 with respect to. In this case, the mask alignment shift is
Depending on the mechanical accuracy of the exposure apparatus, the mask misalignment between layers is larger than that. Usually, the mask alignment deviation due to the mechanical accuracy of the exposure apparatus is about 1 μm.

DRAM block 2 and logic block 3
Are connected to each other by metal wiring 5, and in the other regions, a separation band 4 is provided and the DRAM block 2 and the logic block 3 are connected.
Are separated. Therefore, regarding the mutual relationship between the DRAM block 2 and the logic block 3, it is sufficient to consider only the connection of the metal wiring 5. If the length of one side of the DRAM block 2 is 5 mm, 150 metal wirings 5 may be arranged at a pitch of about 30 μm. Since the mask misalignment is about 1 μm or less, FIG.
The values of X1, Y1 and Y2 in the DRAM mask of
The size of the semiconductor device 1 can be set to a value with a sufficient margin without increasing the size.

As described above, by preparing the photomask group of the DRAM mask, the logic mask, and the logic auxiliary mask, the DRAM block 2 and the logic block 3 can be exposed under the optimum exposure conditions to be formed. Therefore, the degree of integration of the semiconductor device can be increased. Further, by forming a DRAM mask and a logic mask in the shape as shown in FIG. 16, the metal wiring 5 having a predetermined width can be formed. Further, it is possible to prevent a short circuit of each metal wiring 5.

Example 2 A semiconductor device according to Example 2 of the present invention will be described with reference to FIGS. 18 to 19.
FIG. 18 shows the outline of the layout of the semiconductor device in the second embodiment. The embedded semiconductor device 1a has a D
RAM block 2a, logic block 3a, DR
It has a separation band 4a having a predetermined width for separating the AM block 2a and the logic block 3a, and a metal wiring 5a connecting the DRAM block 2a and the logic block 3a. Here, the logic content of the logic block 3a is different from that of the semiconductor device 1 according to the first embodiment. Therefore, the semiconductor device 1 in the first embodiment and the semiconductor device 1a in the second embodiment have different sizes.

A photomask used for exposure of the semiconductor device 1a shown in FIG. 18 will be described. FIG. 19 shows an outline of a logic mask for forming the pattern of the logic block 3a. In this logic mask, data for one chip is arranged on the quartz glass 100 of a predetermined size. The logic mask is omitted because the description of the logic mask in FIG. 3 can be applied except that data for one chip is arranged. The logic auxiliary mask is shown in FIG.
In the logic mask 9 of FIG.
2 is a photomask in which data for logic blocks is not arranged. Photomasks required for manufacturing the semiconductor device 1a are a logic mask and a single logic auxiliary mask as many as the number of mask steps in the transistor forming step and the wiring forming step. The DRAM mask is
The one used for manufacturing the semiconductor device 1 can be used. If the information on the relative positional relationship of the DRAM block to the logic block is changed in mask alignment of the DRAM block, the semiconductor device 1a can be manufactured by the manufacturing method described in the first embodiment. As described above, the DRAM mask and the logic mask of the mask process other than the transistor forming process and the wiring forming process can be shared, so that the development cost and the manufacturing cost can be reduced.

The semiconductor device according to the first and second embodiments is provided with a separation band separating the logic block and the DRAM block. Therefore, the influence of noise generated in the logic block on the DRAM block can be reduced. Similarly, the influence of noise generated in the DRAM block on the logic block can be reduced. If a separation band is not provided between the logic block and the DRAM block, the DRAM block has a higher step than the logic block. Therefore, exposure must be performed in consideration of this step at the boundary between the DRAM block and the DRAM block. However, by providing the separation band, the DRAM block and the logic block can be exposed to the resist under the optimum exposure conditions without considering the step. By providing the separation band, the alignment of the logic block and the DRAM block only needs to consider the connection of the metal wiring, which facilitates the alignment of the logic block and the DRAM block. Further, the region of this separation band can also be used as an arrangement region of the alignment pattern.

In the above embodiment, DRAM masks and logic masks were prepared for all mask processes. However, for example, the DRAM mask and the logic mask may be prepared only for some masking steps such as the capacitance forming step or the wiring forming step. In the above embodiment, one semiconductor device has one DRA.
Although M blocks are arranged, two or more DRAM blocks may be arranged in the semiconductor device.
In the above embodiment, the step of performing the exposure using the DRAM mask is performed after the exposure performed using the logic mask. However, the step of performing the exposure using the logic mask is performed after the exposure performed using the DRAM mask. Good. In the above-described embodiment, the area wider than the wiring width is provided on the DRAM mask side in order to form the wiring. However, the area larger than the wiring width may be provided in the logic mask. Alternatively, the DRAM mask and the logic mask may be provided with a region wider than the wiring width.

In the above embodiment, the second alignment pattern of the DRAM mask is arranged in the region corresponding to the separation band. However, the second alignment pattern of the DRAM mask may be arranged in the region corresponding to the DRAM block so that the width of the separation band is not limited by the second alignment pattern. In the above embodiment, the separation band is arranged on the DRAM block side, but the separation band may be arranged on the logic block side.
It may be arranged on the RAM block side and the logic block side. Further, for example, a pattern for process monitor may be arranged in the area of the separation band. The above embodiment is a semiconductor device in which a stack DRAM and a logic are mounted together. However, it may be a semiconductor device mounted together with a trench type DRAM, and may be a flash type EEPRO.
It may be a semiconductor device mounted together with M, an ultraviolet erasable EPROM, a ferroelectric memory and the like.

[0045]

As described above, according to the present invention, the DRAM
Mask, logic mask, logic auxiliary mask 3
By using different types of photomasks, each of the DRAM block and the logic block can be exposed under optimum exposure conditions. Therefore, the DRAM block and the logic block can be highly integrated. Further, even when the DRAM block and the logic block designed by different design rules are mixedly mounted, the exposure condition for forming the pattern can be optimized, and the semiconductor device having a high degree of integration and mounted can be manufactured. Further, according to the present invention, the DRAM mask can be shared, and the photomask and the logic auxiliary mask (1
It suffices to fabricate only one) for each semiconductor device. For this reason, significant cost reduction is possible.

[Brief description of drawings]

FIG. 1 is a schematic diagram showing a layout of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a terminal specification diagram of the DRAM block of FIG.

FIG. 3 is a diagram showing a logic mask according to the first embodiment of the present invention.

FIG. 4 is a diagram showing a DRAM mask according to the first embodiment of the present invention.

FIG. 5 is a diagram showing a logic auxiliary mask according to the first embodiment of the present invention.

FIG. 6 is a diagram showing a transistor forming process and a wiring forming process in Embodiment 1 of the present invention.

FIG. 7 is a cross-sectional view showing an outline of a wiring forming process in Example 1 of the present invention.

FIG. 8 is a sectional view showing an outline of a wiring forming process in Example 1 of the present invention.

FIG. 9 is a sectional view showing an outline of a wiring forming process in Embodiment 1 of the present invention.

FIG. 10 is a diagram showing a capacitance forming step in Example 1 of the present invention.

FIG. 11 is a sectional view showing an outline of a capacitance forming step in Example 1 of the present invention.

FIG. 12 is a cross-sectional view showing an outline of a capacitance forming step in Embodiment 1 of the present invention.

FIG. 13 is a cross-sectional view showing the outline of a capacitance forming step in Embodiment 1 of the present invention.

FIG. 14 is a wiring pattern D according to the first embodiment of the present invention.
FIG. 3 is a schematic diagram showing an example of a RAM mask and a logic mask.

FIG. 15 is a diagram showing wirings formed by the DRAM mask and logic mask of FIG.

FIG. 16: D for forming a wiring in Example 1 of the present invention
FIG. 6 is a schematic diagram showing another example of a RAM mask and a logic mask.

17 is a diagram showing wirings formed by the DRAM mask and the logic mask of FIG.

FIG. 18 is a schematic diagram showing a layout of a semiconductor device according to a second embodiment of the invention.

FIG. 19 is a diagram showing a logic mask according to the second embodiment of the present invention.

FIG. 20 is a schematic diagram showing a layout of a conventional semiconductor device.

FIG. 21 is a diagram showing a photomask of a conventional semiconductor device.

FIG. 22 is a view showing the manufacturing process of the semiconductor device.

FIG. 23 is a sectional view showing an outline of a metal wiring process of a conventional example.

FIG. 24 is a sectional view showing an outline of a metal wiring process of a conventional example.

[Explanation of symbols]

1, 1a, 1 'semiconductor device 2, 2a, 2' DRAM block 3, 3a, 3 'logic blocks 4, 4 a partial Hanaretai 5,5 a main barrel wiring 100 quartz glass 101 and 107 DRAM block unit 102,102a Logic block part 103, 103a First alignment pattern 104, 104a Second alignment pattern 105, 105a Third alignment pattern 106, 106a Frame data part 108 Separation band part 201 Semiconductor substrate 202 Diffusion layer 203 Gate electrode 204 Polycide bit Lines 205 and 206 Capacitance electrode 207 Interlayer film 208 Contact hole 209 Metal 210 Resist 211 Metal wiring 301 Logic mask 302, 302a DRAM mask 303 Logic auxiliary mask 304 Photomask 300 Light

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁷ identification code FI H01L 27/10 461 H01L 27/10 621C 27/108 (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 21 / 8242 H01L 21/027 H01L 21/82 H01L 21/822 H01L 27/04 H01L 27/10

Claims (8)

(57) [Claims] 1. A memory cell having a memory cell and writing to the memory cell.
Memory for imprinting and reading from the memory cell
The block and the memory block with a space therebetween.
A logic block for controlling the memory block,
Connected to the memory block and the logic block
And signal lines and to a photomask set for semiconductor device fabrication comprising the formation of the first photomask to form the memory block, a shielded arrangement region before Symbol memory block said logic block second and photomask, before Symbol third photomask group semiconductor device manufacturing you comprising: a photomask, a the placement area is shielded without shielding the arrangement region of the logic block of the memory block for. 2. A method of manufacturing a semiconductor device using the photomask group according to claim 1 , wherein a resist is applied to the main surface of a semiconductor substrate, and then the resist is applied using the first photomask. The step of exposing
A method of manufacturing a semiconductor device, comprising: developing the resist after performing two steps including exposing the resist using the second photomask. 3. A method of manufacturing a semiconductor device using the photomask group according to claim 1 , wherein a resist is applied to the main surface of a semiconductor substrate, and then the resist is applied using the first photomask. The step of exposing
A method of manufacturing a semiconductor device, comprising: developing the resist after performing two steps including a step of exposing the resist using the third photomask. 4. A process of exposing the resist using a process and the second photomask to expose the resist using the first photomask, optimal for a photomask used in each step The method for manufacturing a semiconductor device according to claim 2 , wherein the exposure is performed at a different exposure focus. 5. The process of exposing the resist using a step and the third photomask to expose the resist using the first photomask, optimal for a photomask used in each step The method of manufacturing a semiconductor device according to claim 3 , wherein the exposure is performed at a different exposure focus. Wherein said memory block and said logic block is composed of different patterning rule, exposing the resist using a process and the second photomask to expose the resist using the first photomask The method of manufacturing a semiconductor device according to claim 2 , wherein the photomask used in each step is exposed with an optimum exposure focus in the step. 7. The first photomask and the second photomask, wherein at least one of regions of the first photomask and the second photomask forming the signal line has a predetermined width of the signal line. The photomask group according to claim 1 , wherein the photomask group has a portion wider than the width obtained by adding the mask alignment accuracy of the photomask of (1) . 8. A border region that blocks other than the memory blocks of said first photomask, and the perimeter of the area for shielding the memory block of the second photomask, but not identical, that The group of photomasks according to claim 7 .