JP3372192B2 - Bus interface test method and recording medium storing the processing program - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test technique for a bus interface unit of each device connected to a system bus in an information processing system, and more particularly, to efficiently solve problems of a bus driver element and a bus receiver element of the bus interface unit. The present invention relates to a bus interface test method suitable for good detection and a recording medium recording a processing program therefor.

[0002]

2. Description of the Related Art When a device constituting an information processing system that needs to operate for a long period of time fails, the device is disconnected from the system by a program, and then a maintenance person replaces it with a spare device. In this case, in order to reduce the replacement time and the replacement work load, a technique called hot line mounting is used in which the device is replaced while the power is on. In a system that enables such live line mounting, a CPU (Central Processing Uni
(t; central processing unit) In addition to the normal system bus that connects peripheral devices, a maintenance information transfer signal called the maintenance bus that enables communication between the device disconnected from online and the CPU Lines are provided.

The hot line mounting in the system using the maintenance bus is performed in the following procedure. (I) The device in which the failure has occurred is separated from the system (program processing). (Ii) Pull out the failed device from the system (maintenance staff work). (Iii) Replace the removed device with a spare device (maintenance staff work). At this time, the attached device (spare device) is turned on, and self-diagnosis of the device is automatically performed (internal processing of the spare device). The self-diagnosis of the spare device is performed in a state where the system bus and the spare device are electrically separated from each other, that is, in an electrically isolated state, so as not to affect other devices in the current operation.

(Iv) The result of this self-diagnosis is notified from the spare device to the host CPU via the maintenance bus. (V) If the diagnosis result is normal, the CPU that has received this notification releases the electrical isolation state via the maintenance bus and tests the interface with the system bus (program processing). (Vi) If the result of this bus interface test is normal, it is judged that the spare device can be used for operation, and it is installed in the system (program processing).

The test of the interface with the system bus in (v) will be further described with reference to the drawings. FIG. 2 is a block diagram showing an example of the configuration of an information processing system for hot-line mounting. In the information processing system of this example, the CPU 1 and the device A (described as “peripheral device A” in the figure) 10 are connected by a system bus 3 and a maintenance bus 2. The system bus 3 is provided with a signal line for parity check. Various other devices are connected to the system bus 3, one of which will be described below on behalf of the device A. Also, CPU
1 is also included as one of the other devices and has a similar configuration.

The system bus 3 is mainly composed of the CPU 1 and the device A.
Used for information transfer to and from the maintenance bus 2
Is mainly used for the purpose of communication between the CPU 1 and the device A10 which is separated from the system (online program). The device A10 includes a system bus interface unit 4 including a bus driver and a bus receiver, a system bus control unit 8 that controls communication via the system bus 3 via the system bus interface unit 4, and a maintenance bus 2 via It is composed of a maintenance bus control unit 5 for controlling communication and a main circuit unit 9 for realizing main functions of the device A10.

The system bus control unit 8 has a register 6 and a parity check unit 7 inside. Further, the maintenance bus control unit 5 has a function of setting electrical isolation for the bus driver and the bus receiver in the system bus interface unit 4. The parity check unit 7 uses the data for parity check sent from the signal line for parity check in the system bus 3 to check the parity error of the data written in the register 6. The conventional bus interface test at the time of hot-line mounting in the system having such a configuration will be described below with reference to FIG.

FIG. 6 is a sequence diagram showing a procedure example of a conventional bus interface test. In the case of a failure or update of the version number, it is necessary to install the device A in a hot line. When this hot line mounting is performed, the power of the device A is turned on, the main circuit is activated, and self-diagnosis is automatically started. This self-diagnosis process is usually performed not only on the main circuit itself but also on the maintenance bus control unit and the system bus control unit. When the power is turned on, the maintenance bus control unit is set to the isolation (iSOL)
By the control, the connection between the system bus and the device A is electrically disconnected, that is, brought into a high impedance state so that the device A itself does not disturb the CPU and other devices via the system bus.

When the self-diagnosis processing is completed, the apparatus A sends a notification indicating that the hot-line is attached to the CPU side through the maintenance bus together with the result. CPU receives this notification
Checks the diagnosis result and, if not normal, outputs a message to maintenance personnel. If the result is normal, it is judged that there is no internal failure or abnormality, and C
The PU instructs the device A via the maintenance bus to cancel the electrical isolation of the system bus.

At this stage, the system may be immediately incorporated into the system for operation, but in order to complete the test, the system bus interface section 4 of the device A in FIG. 2, that is, the bus driver element, the bus receiver, is used. An interface test may be performed to confirm that the device has no failure. Traditionally, this interface test
The arbitrary pattern is written in the register 6 in the system bus control unit 8, the pattern is read out immediately after this writing, and the pattern is checked.

However, in such a conventional interface test technique, the system bus interface unit 4 of FIG. 2 is used.
When the "0" stack fault or the "1" stack fault of the bus driver or the bus receiver of a certain signal line in the above coincides with the pattern of the data to be written in the register, the parity on the system bus 3 by the parity check unit 7 is checked. There is a possibility that it may be overlooked without being detected by the check or the data collation after reading, and may be erroneously determined to be normal. Such an example will be described with reference to FIG.

FIG. 7 is an explanatory view showing a defect example in the conventional bus interface test technique. For example, when the receiver element 4a corresponding to the i-th bit of data has a "0" stack failure and the value of the i-th bit of the pattern of the write data 11 happens to be "0",
The parity bit generated by the parity check unit 7 is also
The received parity bit matches (here, both are “1”), and the failure is overlooked. As a result, there is a possibility that the failure of the hot-wired device A is latently incorporated into the system, resulting in an unexpected system abnormality thereafter.

[0013]

The problem to be solved is that the prior art cannot sufficiently confirm the failure of the bus driver and the bus receiver of the bus interface section. An object of the present invention is to provide a bus interface test method and a recording medium having a processing program therefor, which can solve the problems of the conventional techniques and improve the failure detection accuracy of the interface test.

[0014]

In order to achieve the above object, in the bus interface test method of the present invention, "write (write)" and "read (read)" used in the conventional bus interface test are performed, for example. Switching is performed by switching between two writing patterns in which bits at the same position are reversed, such as all "1" and all "0".
A parity check is performed for each pattern when writing and reading. This makes it possible to detect a 1-bit stack fault in the driver element and the receiver element of the bus interface unit. If the signal line to be tested is an even number, the pattern is also composed of an even number of bits. In this case, the value added for parity check for the two write patterns is the same, and the driver element of the parity signal line is the same. And 1-bit stack failure of the receiver element may be missed, so "write" / "read" using the third pattern with the opposite parity value
Do. Furthermore, by comparing the pattern at the time of writing and the pattern at the time of reading in each pattern, a defect other than the parity error can be detected. It should be noted that such a processing program is recorded in a recording medium such as an optical disk or a floppy disk (FD), and is loaded and executed in the main memory during the test.

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings. FIG. 1 is a flow chart showing an embodiment of processing according to the present invention of a bus interface test method of the present invention, and FIG. 2 is a block showing a configuration example of an information processing system to which the bus interface test method of the present invention is applied. It is a figure. The information processing system shown in FIG. 2 is the one exemplified in the above description of the conventional technique.
And a device A (indicated as “peripheral device A” in the figure) 10 are connected via a maintenance bus 2 and a system bus 3, and the device A 10 includes a system bus interface unit 4 connected to the system bus 3. A maintenance bus control unit 5 connected to the maintenance bus 2, a system bus control unit 8 including a register 6 and a parity check unit 7, and a main circuit 9 for controlling the overall operation of the device A10. .

On the system bus 3, an OD for driving an optical disc (described as "OD" in the figure) 20 storing a processing program for the bus interface test of the present invention.
The drive unit 21 is connected, and the program from the optical disc 20 is loaded into the CPU 1 and executed. Further, the system bus 3 is provided with a signal line for parity check, and in the parity check unit 7 of the device A10, the data for parity check sent by the signal line for parity check in the system bus 3 is sent. Is used to check the parity error of the data written in the register 6. In this example, by using this parity error check, the test of the system bus interface unit 4 after performing the above-described self-diagnosis processing at the time of hot-line mounting of the information processing system can be performed with high reliability. it can.

Before explaining the interface test according to the present invention, regarding the bus signal lines of the information processing system,
This will be described with reference to FIGS. 3 and 4. FIG. 3 is an explanatory diagram showing a configuration example of a signal line of a bus of the information processing system in FIG. Here, "Toron standard system bus TOXB
US Ver. 1.00.00.00 "(October 1991, published by the TRON Association) as an example.

Although there are a total of 89 signal lines in this example,
Of these, stack failures in the bus interface section corresponding to the following 72 signal lines are to be tested. (A) "CAD00-63" of "No. 9": A bidirectional information transfer bus of 64-bit width in which control information, address information and data information are transferred in a time division manner. (B) "CADP0-7" of "No. 10": CAD00
It is a parity signal for each −63 bytes (8 bits).
Represents odd parity. The basic operation of this bus will be described with reference to FIG.

FIG. 4 is an explanatory diagram showing an operation example of the bus signal line in FIG. This example shows the case of a mode (8-byte mode) in which 8 bytes of the information transfer bus are fully used. As a function of this bus, as described in the above publication, it also has a 4-byte mode in which half of the 8 bytes of the information transfer bus is used, but the operation is similar, and is explained here. Is omitted. This figure shows an operation example in which the device i transfers data to the device j via the bus. Note that the bus handler (BH) shown here is a circuit having a function of arbitrating bus requests, and is provided in a device connected to the bus or as an independent device, and is the same as the present invention. Are not directly related, but are described here for explaining the operation of the bus.

The operation will be described below according to the numbers (1) to (14) indicating the change timing of each signal line. (1) The device i drives the bus use request signal (BRQL-i) in order to transfer information to the device j, and B
A bus acquisition request is issued to H (bus handler). (2) When the BH can accept the bus use request signal,
The bus right is given to the device i by driving the bus use permission signal (BGRM-i) for the device i. (3) The device i that has acquired the bus use right stops driving the bus use request signal in response to the bus use permission signal.

(4) At the same time, the device i receives the bus use permission signal, validates the information transfer bus, and sends information to the bus. At the time of the first information transfer, the BS * signal (bus cycle start signal, * symbol indicates negative logic) of the transfer control signal is driven. (5) At the same time as BS *, the BLK * signal (block signal) is driven to notify the other devices of the start of block transfer.
The BLK * signal is driven on the bus during the information transfer period. However, the drive is stopped one bus cycle before the end of the transfer, and the BH is informed that the bus will be released after one bus cycle. (6) The BH, which has detected the driving stop of the BLK * signal of the transfer control signal, stops driving the bus use permission signal after one clock.

(7) After sending the order command (Co),
After two cycles, the status valid signal (STVLD * signal) is driven, and in this cycle, the transfer destination device, device j, reports the order command reception state to the transfer source device i. (8) In the transfer after the command, the transfer destination device j checks the success or failure of the data transfer with respect to the received information for each transfer of the information transfer bus, and collects the results together with the status code on the status bus. It is returned to the transfer source device i as (4 bits). This return is performed at the timing when the status valid signal is driven, two cycles after the final data transfer.

With the above, one bus operation is completed. The TOXBUS used in the description of this embodiment employs a split transfer type technology in which the bus right is acquired / released each time information is transferred. Therefore, answer information or data can be returned from the transfer destination device j. When necessary, the transfer destination device j itself newly acquires the right to use the bus, and the transfer source device i
Answer information and data will be returned to. This operation is shown in (9) to (14) in the figure, but since it is not directly related to the present invention, the description of this part will be omitted.

In the operation of the bus described above, 64
Command information C, address information A, and actual data D are transferred via a bit (8 bytes) information transfer bus. Using this transfer operation, the test data pattern is written into and read from the register 6 of the device A in FIG. 2 as shown in FIG. FIG. 5 is a sequence diagram showing an example of an information transfer operation according to the present invention in the information processing system in FIG.

As shown in FIG. 5, when the CPU receives the bus use permission from the BH corresponding to the bus request, the CPU writes the test data into the register of the device A. Here, of the information to be transferred, the command information C includes the transfer source device number, the transfer destination device number, and the transfer mode (4
Since the byte mode (4B) / 8 byte mode (8B) and the like are held, the information pattern cannot be arbitrarily changed. Further, the address information A also designates the data storage means of the transfer destination device, that is, the address of the register or the like, and it is difficult to set an arbitrary pattern.

As described above, of the information transferred through the bus, it is the data D that can be changed in an arbitrary pattern. In this example, by changing the pattern of the data D, the failure detection accuracy of the interface test can be improved. Improve. That is, the command information Co, the address information A and the 8-byte data (D
0 or D1) is sent and written to the register. Device A
Stores data D0 (D1) at address A, and then stores B
After sending the bus request to H and receiving the bus use permission from BH, the answer command CAW is returned to the CPU.

When the CPU receives this answer command CAW, after the sequence of bus request and bus use permission,
The read command of the data D0 (D1) of the register of the device A is sent to the device A via BH. In response to this read command, the device A sends the data D0 (D1) to the CPU together with the answer command CAW. The same process is repeated by changing the data pattern. Hereinafter, an example of the interface test by changing the pattern of the data D0 (D1) will be described with reference to FIG.

In the example in FIG. 1, TOXBUS is 8
It is assumed that the register operates in the byte mode, the register in the system bus control unit of the device A has a 64-bit width, and the parity check signal line (parity line) has 1 byte (8 bits). That is, the bus interface test is performed on the signal line having an even bit width. Therefore, in the bus interface test of the present example, each process of writing (steps 101 and 102) and reading (steps 103 and 104) and collating (steps 105 and 106) is repeated (for example, using the following three patterns). Step 10
0, 200, 201, 300, 301) to perform information transfer bus (64 lines) or parity lines (8 lines)
The 0 stack fault or the 1 stack fault occurring in one of the total 72 is detected. The order of the patterns used for the checking process does not have to be the order shown here and may be arbitrary.

(I) Pattern 1 (= D1): A pattern in which 64 bits are all "1" and is used in the processing of step 100. In this case, if normal, the information transfer bus (8
Bytes) The number of bits "1" for each byte (8 bits) of CAD00-63 is "8", and all the 8 bits of CADP0-7 on the parity line have a pattern of "1" by the odd parity method. Become. That is, the total of the number of bits "1" for each byte (8 bits) on the information transfer bus and the number of bits for each bit on the parity line is an odd number (9). However, if a 1-bit 0 stack fault occurs in the information transfer bus CAD00-63 or the parity lines CADP0-7, the bit "1" on the information transfer bus + parity line becomes an even number, and a parity error occurs, Abnormality is detected. That is, according to this pattern 1, the information transfer bus CAD00-63 or the parity line CADP0-
It is possible to detect without missing the 1-bit 0-stuck fault in 7.

(II) Pattern 2 (= D0): A pattern in which 64 bits are all "0", which is used in the processing of step 200. In this case, if normal, the information transfer bus (8
The number of bits "1" for each 1 byte (8 bits) of CAD00-63 is "0", and all 8 bits of CADP0-7 on the parity line have a pattern of "1" by the odd parity method. Become. That is, the sum of the number of bits "1" for each byte (8 bits) on the information transfer bus and the bit for each bit on the parity line is an odd number (one). However, the information transfer bus CAD00-63 has a 1-bit 1-stack fault, and the parity line CADP0-
If a 1-bit 0 stack failure occurs in 7, the bit "1" on the information transfer bus + parity line becomes an even number,
A parity error occurs and an anomaly is detected. That is,
According to this pattern 2, the information transfer buses CAD00-63
Can be detected without missing the 1-bit 1-stack fault in 1 or the 1-bit 0-stack fault in the parity lines CADP0-7.

By these pattern 1 and pattern 2,
1 bit of 0 in the information transfer bus CAD00-63
Both the stack failure and the one-stack failure have been checked, but it is 1 in the parity lines CADP0-7.
Only the 0 stack failure of the bit is checked, and the 1 stack failure is still unknown, and the check according to the following pattern 3 is necessary.

(III) Pattern 3: 64 bits are "H"
(Hexadecimal code) 5454 ... 54 ”and is used in the process of step 300. This pattern is
The binary code is "01010100/01010100
/ ... ", and the number of bits" 1 "for each byte is" 3 ", which is an odd number, and all signals (CADP0-7) on the parity line are" 0 "during normal operation by the odd parity method. . However, 1 of parity lines CADP0-7
If one stack fault occurs in a bit, the number of bits “1” on the information transfer bus + parity line becomes “3” +
Since “1” = “4” is an even number, a parity error occurs and an abnormality is detected. That is, according to this pattern 3, a 1-bit 1-stack fault in the parity lines CADP0-7 can be detected without missing.

Each pattern used here is simple and is used to reduce mistakes when creating a program for a bus interface test.
The patterns used in the present invention are not limited to the above three patterns. That is, the information transfer bus (64
The number of bits "1" becomes an even number due to the occurrence of a 1-bit stack fault on the (+ line) + parity lines (8 lines) (here, TOXBUS is an even number for odd parity processing). However, it may be an odd number in the case of a bus of even parity processing), and any one can be used as long as it can detect a 1-bit stack fault without omission. For example, instead of "H (hexadecimal code) 5454 ... 54" in pattern 3, "H (hexadecimal code) 57" in which the number of bits "1" for each byte is an odd number
57 ... 57 "and" H (hexadecimal code) 1313 ...
Even if "13" is used, the parity line CADP0-7 is set to 1
It is possible to detect anomalies due to a one-stack failure of bits.

Next, each step 10 using each pattern
Steps 101 to 1 performed in processing 0, 200, 300
The processing of 06 will be described. The process of step 101 is the writing of the designated pattern to the register (8 bytes) in the device A. When a parity error is detected in this process (step 102), the process ends with “test NG” and no error occurs. In that case, the process of the next step 103 is performed. still,
The parity error in this case is due to the failure of the bus receiver element of a certain bit in the bus interface unit of the device A.

The process of step 103 is the same as step 101.
The data written in the process is read from the register. If a parity error is detected in this process (step 104), the test ends in NG, and if there is no error, the process in the next step 105 is performed. . The parity error in this case is due to the failure of the bus driver element of a certain bit in the bus interface unit of the device A. The process of step 105 is a process of collating the pattern of the data written in the process of step 101 with the pattern of the data read in step 103, and if they do not match (in this case, another cause unrelated to the parity error). (Step 104), the check process for this pattern ends with NG, and if they match, the check process ends normally.

As described above with reference to FIGS. 1 to 5, in the bus interface test method of this embodiment, the data pattern is changed in three ways (all "1", all "0", "5454". 54 (hexadecimal code) "), the parity check function of the system bus is used to repeat the test based on the parity check result of each pattern and the collation result of the write pattern and the read pattern. As a result, the stack value (0 or 1) of the stack fault of the bus driver or the bus receiver element in the interface portion with the system bus of the device A
And a pattern of data transferred on the system bus happen to coincide with each other, it is possible to reliably detect a 1-bit stack failure that may have been missed by the conventional bus interface test technique.

The present invention is not limited to the embodiments described with reference to FIGS. 1 to 5, and various modifications can be made without departing from the scope of the invention. For example, in the present embodiment, three types of data patterns are used, but this is because the test is performed on even-numbered signal lines, and in the case of the test on odd-numbered signal lines, the bit patterns are reversed (same). It is sufficient to use two data patterns whose position bit values are opposite). That is, in two data patterns in which the data pattern has an odd number of digits and the bit values are mutually inverted, the parity values (“1” and “0”) added for the parity check are always reversed.

For example, if the data pattern is "01101 (5 digits)" with odd parity, the parity value is "0".
Therefore, the parity value becomes “1” in the data pattern “10010” in which the bit value is inverted (reverse). Also, with even parity, the data pattern is “101101
1 (7 digits) ", the parity value is" 1 ", and the bit value is inverted (reverse) data pattern" 010 ".
The parity value of "0100" is "0". As a result, if the data pattern has an odd number of digits, it is possible to check both the 1-bit 0-stack fault and the 1-bit fault in the information transfer bus CAD by using only two patterns having mutually inverted bit values. Parity line C
Both 1-bit 0-stack and 1-stack faults in ADP can be checked.

In this embodiment, the TOXBUS operates in the 8-byte mode, and the register in the system bus control unit of the device A has a 64-bit width. However, in the case of the 4-byte mode, the device in the device A has the same structure. Even when the register has a 32-bit width, the same processing can achieve the purpose. In the case of the 4-byte mode, in FIG. 5, the command information Co and the address information A are not at the same time,
When the command information Co and the address information A are transferred serially in this order, and the register has a 4-byte width, the data D
Only 0 is transferred.

Further, the present invention is not limited to the TRON standard system bus TOXBUS, but can be applied to any bus as long as it has a parity check function, and the same effect can be expected. Further, in this example, the configuration example in which the CPU and the device A are connected to the system bus has been described, but the same applies to devices connected via a bus other than the system bus in the same system. Can be applied to. In this example, CP
The configuration example in which the U and the device A are connected to the system bus has been described. However, the CPU and the device A do not need to be directly connected by a bus line, and may be connected via a bus expansion device or the like. , Can be applied as well.

In this example, the application in the case of hot-line installation is explained as an example. However, when the bus interface part of a certain device is suspicious, the maintenance staff performs diagnosis and if the maintenance staff is OK. The technique of the present invention can also be applied to the case where the maintenance command is input and executed. Further, in this example, a 1-bit stack failure is detected, but since write data and read data in each data pattern are also collated, a plurality of stack failures are also detected to some extent. be able to. Further, in the present example, the processing program relating to the bus interface test method is recorded on the optical disc, but a recording medium suitable for the capacity such as an FD or a magnetic tape can be used.

[0042]

According to the present invention, a failure of a bus driver element or a bus receiver element of a bus interface unit, that is, a 1-bit stack failure can be detected with certainty, and the failure detection accuracy of an interface test can be improved. It is possible to improve the reliability of the information processing system including the bus interface unit.

[Brief description of drawings]

FIG. 1 is a flowchart showing an embodiment of a process according to the present invention of a bus interface test method according to the present invention.

FIG. 2 is a block diagram showing a configuration example of an information processing system to which the bus interface test method of the present invention is applied.

3 is an explanatory diagram showing a configuration example of a signal line of a bus of the information processing system in FIG.

FIG. 4 is an explanatory diagram showing an operation example of a bus signal line in FIG.

5 is a sequence diagram showing an example of an information transfer operation according to the present invention in the information processing system in FIG.

FIG. 6 is a sequence diagram showing a procedure example of a conventional bus interface test.

FIG. 7 is an explanatory diagram showing a defect example in the conventional bus interface test technique.

[Explanation of symbols]

1: CPU, 2: maintenance bus, 3: system bus, 4: system bus interface unit, 4a: receiver element,
5: maintenance bus control unit, 6: register, 7: parity check unit, 8: system bus control unit, 9: main circuit, 10:
Device A, 11: write data, 20: optical disc, 2
1: OD drive device.

─────────────────────────────────────────────────── ─── Continuation of the front page (73) Patent holder 000000295 1-7-12 Toranomon, Minato-ku, Tokyo Oki Electric Industry Co., Ltd. (72) Etsue Masuda Etsuo Masuda 3-19-2 Nishishinjuku, Shinjuku-ku, Tokyo Date Main Telegraph and Telephone Corporation (72) Inventor Koichi Shimizu 3-19-2 Nishishinjuku, Shinjuku-ku, Tokyo Japan Telegraph and Telephone Corporation (72) Inventor Takao Murakami 4-chome Kamiodachu, Nakahara-ku, Kawasaki-shi, Kanagawa No. 1 in Fujitsu Limited (72) Inventor Hiroshi Nishii 216 Totsuka-cho, Totsuka-ku, Yokohama-shi, Kanagawa Hitachi, Ltd. Information & Communication Division (72) Inventor Yuichi Hirano 5-7-1, Shiba, Minato-ku, Tokyo Inside NEC Corporation (72) Inventor Tamotsu Tahara 1-7-12 Toranomon, Minato-ku, Tokyo Inside Oki Electric Industry Co., Ltd. (56) Reference JP-A-5-158843 (J , A) JP flat 5-12133 (JP, A) JP flat 8-179013 (JP, A) JP flat 5-342117 (JP, A) (58 ) investigated the field (Int.Cl. ^7, DB Name) G06F 11/22-11/26

Claims (5)

(57) [Claims] 1. An information transfer bus and a parity check signal.
Connected to a bus consisting Line, a bus interface method for testing a bus interface that equipment having a parity check function, the server of the first data in any odd digits of a bit pattern
Write to the storage means of the above device through the interface
The first step and the first data written in the storage means in the first step.
A second step of performing a parity check on the data by the parity check function and a parity check function on the second step .
If the parity check result is a parity error, above
If the bus receiver element of the bus interface is defective
By the third step of detecting and the parity check function in the second step.
If the parity check result is a parity error,
The first data written in the storage means is transferred to the bus controller.
The fourth step of reading through the interface and the first data read in the fourth step .
Check the parity with the above parity check function.
According to the fifth step to be performed and the parity check function described above in the fifth step
If the parity check result is a parity error, above
If the bus driver element of the bus interface is defective
The sixth step of detecting and the parity check function of the fifth step
If the parity check result is a parity error,
Second data having a bit pattern opposite to that of the first data
Second data writing and writing <br/> write non seventh step in the storage means via the bus interface, in the storage means in step said 7
An eighth step of performing a parity check with the parity check function relative to data, due to the parity check function in step said 8
If the parity check result is a parity error, above
The ninth step to detect that the bus receiver element is defective
And the first in the parity check function.
Parity check using the data and the second data
Based on the results of
A bus interface test method, comprising detecting a 1-bit stack fault of the bus driver element and the bus receiver element connected to each of the T-check signal lines . 2. An information transfer bus and a parity check signal.
Connected to a bus consisting Line, a bus interface method for testing a bus interface that equipment having a parity check function, the server of the first data in any of the even digits of a bit pattern
Write to the storage means of the above device through the interface
The first step and the first data written in the storage means in the first step.
Parity check preset in the above device
A second step of performing a parity check by the function, according to the parity check function in the second step
If the parity check result is a parity error, above
If the bus receiver element of the bus interface is defective
By the third step of detecting and the parity check function in the second step.
If the parity check result is a parity error,
The first data written in the storage means is transferred to the bus controller.
The fourth step of reading through the interface and the first data read in the fourth step .
Check the parity with the above parity check function.
According to the fifth step to be performed and the parity check function described above in the fifth step
If the parity check result is a parity error, above
If the bus driver element of the bus interface is defective
The sixth step of detecting and the parity check function of the fifth step
If the parity check result is a parity error,
Second data having a bit pattern opposite to that of the first data
Second data writing and writing <br/> write non seventh step in the storage means via the bus interface, in the storage means in step said 7
An eighth step of performing a parity check with the parity check function relative to data, due to the parity check function in step said 8
If the parity check result is a parity error, above
The ninth step to detect that the bus receiver element is defective
And the parity check function in the eighth step above.
If the parity check result is a parity error,
The storage unit stores the third data having a bit pattern in which the parity value added for the parity check is opposite to that of the first and second data via the bus interface.
A write non-tenth step written to, the third data written in the memory means at said 10 step
An eleventh step of performing a parity check with the parity check function for, in the parity check function in step said 11
If the parity check result is a parity error,
The above-mentioned bus receiver connected to the parity check signal line.
The twelfth step of detecting that the server device has a failure, and the parity check function in the eleventh step.
The parity check result must be a parity error.
For example, the third data written in the storage means is stored in the buffer.
Thirteenth step of reading through the interface
And the third data read in the 13th step.
Then, the parity check function is used to check the parity.
And a parity check function in the fourteenth step.
If the parity check result is a parity error,
The above bus driver connected to the parity check signal line.
And a fifteenth step of detecting that the aver element is defective.
The first to the third in the parity check function
Based on the result of the parity check using the data of
Information transfer bus and signal line for parity check
A bus interface test method for detecting a 1-bit stack fault of the bus driver element and the bus receiver element connected to each of the above. 3. The bus interface test method according to claim 1 or 2, wherein the bit pattern of the first data is either all "1" or all "0". Bus interface test method characterized by the following. 4. The bus interface test method according to claim 1, wherein the parity is read every time each data is read from the storage means.
If there are no errors, the bus interface test wherein the line <br/> Nau pattern matching and data read from the written data and said storage means to the storage means. 5. A recording medium in which each processing program in the bus interface test method according to claim 1 is recorded.