JP3373641B2 - Test sequence generator - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test sequence generator for a system designed in a hardware design language.

[0002]

2. Description of the Related Art In hardware design of a conventional logic system, logic synthesis has become popular as a solution to the problem of the increase in design man-hours accompanying the progress of semiconductor technology. By using logic synthesis, a gate-level logic circuit corresponding to the RTL description (hardware design description by register transfer level) is automatically synthesized.

As a test sequence for verifying this RTL description, a pattern for verifying whether a register, a bus, or an arithmetic unit operates under a clock or a control signal to obtain a correct result in a determined cycle is used. . It consists of an input test pattern applied to the input port, an expected value pattern at the output port, a test pattern applied to the register for verifying the inside of the circuit, and an expected value pattern at the register.

As described above, the designer manually creates an RTL input test pattern that is an input. Regarding the expected value pattern, the designer conducted an RTL simulation using a test sequence, checked whether the obtained result was in accordance with the specifications, and if the result was correct, the result was used as the expected value pattern.

On the other hand, in order to create a verification test sequence for an RTL description generated by a high-level synthesis device from a behavior description having a higher degree of abstraction, the designer first had to understand the synthesized RTL description. . For example, the timing of the test pattern applied to all input ports and the timing information of the operation result appearing at the output port are
It was necessary to read from the RTL description. The RTL description of a 1-megagate LSI has tens of thousands of lines and hundreds of ports, and it takes a lot of time for the designer to check the timing of each port.

Since various data types such as a floating point type and a bit type exist in the port including an integer type, when the data type of the port in the behavior description and the data type of the register transfer description are different, It was necessary to convert the value of the test pattern in consideration of the above. Moreover, if different data types are used for each port, the work involved in type conversion is very complicated and takes a lot of time. As described above, the designer creates the input test sequence while manually acquiring the scheduling information of the input or output of the RTL description and converting the pattern value.

Further, the RTL description of a large-scale logical system has tens of thousands to hundreds of thousands of lines, and the test sequence of this description is equivalent to or more than that line, and it is a difficult work to manually create. there were.

On the other hand, in order to improve the efficiency of design, a circuit already designed for another purpose may be reused as a component of another large-scale system. These opportunities increase as the system under design grows. In such a case, even if the operation of the reused circuit is guaranteed to be correct by itself, it is necessary to incorporate the circuit to check the integrity of the system and verify the operation of the entire system. .

In order to verify the entire large-scale system by simulation, it is more efficient to perform it at the behavioral level, which is a higher description level with a higher level of abstraction than RTL. Since the degree of abstraction is high, detailed simulation cannot be performed, but the simulation itself can be performed at high speed. However, when it is desired to verify the operation inside the circuit in more detail, the RTL simulation is more suitable. From this, in order to verify a large-scale system including some of the above-mentioned designed circuit modules, the newly created circuit module requires detailed verification, so that the RTL is used to design the designed circuit module. Since it is mainly necessary to describe the part related to the interface with other modules, there is a strong demand for describing it at the behavior level and simulating the whole while adjusting the timing between modules at both levels.

[0010]

However, since many of the designed circuits are designed by RTL, it is necessary to rewrite the designed circuit from the RTL description to the behavioral description in order to use the verification method as described above. There is. At this time, it is necessary to verify whether the rewritten behavior description is correct as the specification of the original RTL description. In this verification, a behavior-level test series that is equivalent to the RTL test series used when verifying the designed circuit of the RTL description is created, and the simulation result of the RTL description and the behavior description are simulated by the behavior test series. It will be possible if they can be compared.

However, to create a behavioral test sequence for simulating a behavioral description equivalent to the RTL test sequence for simulating the RTL description as described above, it is necessary to create the behavioral test sequence as described below. There is a problem that a behavior test sequence equivalent to the RTL test sequence cannot be easily created because the levels have different degrees of abstraction with respect to time and data.

Regarding data, for example, in RTL, an integer may be handled as a data type, but in many cases, bit strings and multivalued logic are mainly used. On the other hand, at the behavior level, in addition to the above data types, abstract data such as literals and structures may be handled.

Regarding the time, the RTL has a concept of a state synchronized with a clock. Therefore, when creating a test sequence along a time series, a test vector is designated for each state or for each clock cycle unit time. Will be done. Further, since the circuit operation in each state is determined, the time when the input value is changed must be determined accordingly.

On the other hand, at the behavior level, RT
There is no concept of a state synchronized with a lock like L, and the order relation of individual operations is considered as a temporal concept, so rather than specifying an input vector for each unit time,
Input vectors that may change in the output variables of the behavior description are specified sequentially.

As described above, since the RTL and the behavior level have different degrees of abstraction regarding data and time, the RTL is different.
It was difficult to verify the behavior description by creating an equivalent behavior level test series from the test series of.

It is also conceivable that a behavior test sequence is created independently of the RTL test sequence, and a behavior description simulation is carried out using the behavior test sequence for verification. As a result, the correctness of the behavioral description can be verified. However, in this method, if there is an error in the interpretation stage of the work of interpreting the operation specification of the circuit from the RTL description and creating the behavior description, the error is not detected and the behavior description is equivalent to the original RTL description. There was a problem that things were not guaranteed.

As described above, even if the circuit described in RTL is rewritten in the behavioral description, it is difficult to verify that it is equivalent. Therefore, even if the circuit module described in RTL is rewritten in the behavior description and that part is simulated at the behavior level to improve the efficiency of verification of the entire system, the rewritten behavior description is equivalent to the original RTL description. However, there is a problem in that the reliability of the verification result deteriorates, the behavior description is often required to be corrected during system verification, and the efficiency of the entire design cannot be improved in the end.

An object of the first aspect of the present invention is that a test sequence for verifying a behavior description already exists and RT is used.
When the L description is manually designed, by automatically generating the RTL verification test series and the expected value series, R
Because it is difficult for the designer to understand the function of the circuit from the high-level synthesized RTL description when shortening the design verification time of the TL description and creating the test sequence of the RTL description generated by high-level synthesis. Drastically reduce the time required to create a test sequence for verification of RTL description, and
Misunderstanding the function of the TL circuit, creating a test series,
Modify the necessary test series according to the change in the RTL description,
The purpose is to automate the creation of the test sequence of the RTL description in order to prevent the mixture of defects that would occur due to manual operation.

Further, there is a problem that applying the simulation of the entire system in which the behavior description and the RTL description are mixed does not lead to improvement in design efficiency.
When the behavior description is created from the TL description, any means can be used as long as it is a means for verifying whether the behavior description is equivalent to the RTL description. Generally, simulation is effective for verifying the description, but it is necessary to use an equivalent test series. However, it is difficult to create an equivalent behavior series from the RTL test series because of the difference in abstraction level between the two levels.

Therefore, according to the second aspect of the present invention, R
The purpose is to realize a function of generating a behavioral test series equivalent to the TL test series. As a result, the simulation result of the RTL description by the RTL test series and the simulation result of the behavior description by the behavior test series can be compared, and it is possible to verify whether the behavior description and the RTL description are equivalent. Is also solved.

[0021]

According to a first aspect of the present invention, a test sequence generation device uses a behavioral level specification description of a logic system and a register transfer level description corresponding to the specification description. In each step of the control steps corresponding to the state transition of the register transfer level, the specification description and the register transfer level are associated by associating the signal name and the port of the register transfer level description and the behavior level specification description. Correspondence correspondence between the specification description and the register transfer level description obtained by the correspondence creation unit based on the test sequence data for verifying the specification description. And a test sequence generation unit that automatically generates test sequence data at the register transfer level based on the relationship.

According to a second aspect of the present invention, there is provided a test sequence generation device, which comprises an RTL analysis unit for analyzing state transition information of an RTL description, and RTL analysis unit based on the state transition information generated by the RTL analysis unit. A test sequence (test pattern) processing unit that processes a test sequence (RTL test pattern) to the required number of steps, and facilities and variables existing in the RTL description and the behavior description, respectively, based on the correspondence information of the RTL-behavior description, It comprises a test expression form changing unit that associates these data types and changes the form of the test sequence to generate a behavior-level test sequence.

[0023]

According to the first aspect of the present invention, the correspondence creation unit for the behavior level specification description and the register transfer level description includes the behavior level description data, the RTL description data, the RTL facility and the behavior. From the information corresponding to the described signal name, the data type of the RTL facility or behavior signal, the application or observation time of the test pattern made for the RTL facility,
RTL test sequence information including the value of the facility pattern added to the RTL description is generated. The test generation unit that generates the RTL verification test sequence captures the behavior level input test sequence and the expected value sequence data, and uses the test sequence information generated by the correspondence generation unit to input the RTL description input test sequence. And generate an expected value series.

According to a second aspect of the invention, first the RTL
The analysis unit analyzes the state transition information of the RTL description,
The information about the number of states of description, the condition of state transition, the input port referenced in each state, and the output port to which a value is set is generated. Based on this information, the test pattern processing unit investigates in which state of the RTL description each step of the RTL test series is, extracts a valid value in the RTL test series, and merges the steps of the test pattern. And delete it to generate a test series with the same number of steps as the behavioral test series. The test expression form changing unit associates the facility, the variable, and the data type between the RTL description and the behavior description based on the information of the behavior description, and similarly in the test pattern generated by the test sequence processing unit, the facility is also changed. When the RTL facility is described by a plurality of behavior variables, the column of the RTL facility of the test series is divided into the column of variables, and the data of the facility RTL data is stored. Change the value to a more abstract representation in the behavioral hell. Also, in the test expression form changing unit, when the number of test columns is changed by associating the facility with a plurality of variables, it is checked whether or not the test pattern processing unit can newly merge the steps of the test series. Make changes if possible.

[0025]

[Embodiment] Generally, when the target logical system becomes large in scale and the corresponding RTL description becomes tens of thousands to hundreds of thousands, it is extremely difficult to manually create a test pattern for testing it. Become. In that case, if a test pattern for RTL description can be automatically generated from the abstracted test pattern at the behavior level, it becomes extremely easy to create a test pattern for RTL description of a large-scale logic system. An apparatus therefor is shown below as a first embodiment of the present invention.

The first embodiment will be described in the following order. First
A configuration diagram of the test sequence generation device of the present invention will be described below. Second, the behavior level test series will be described.
Thirdly, the test sequence of the generated RTL will be described. Fourth, the correspondence between the behavioral level specification description and the register transfer level description The command given to the creation unit, the data created by the creation unit, and the processing flow of the creation unit will be described.
Fifth, the processing flow of the test sequence generation device will be described. Finally, the processing flow of test sequence generation using a simple motif circuit will be described in detail.

FIG. 1 is a block diagram showing the configuration of an embodiment of the test sequence generation device of the present invention.

The behavior-level specification description data 1 and the register transfer level (RTL) description data 2 are intermediate circuit data after compiling the hardware design description of each level. The data of the operator itself that represents the operation and function of the circuit and the connection information between the operators are stored. These descriptions are designed manually by a designer or by using a synthesizer.

The behavior level specification description and RTL description correspondence creation unit 3 includes a command consisting of correspondence information between the facility of the RTL description and the signal name of the behavior description.
From behavior-level description data and RTL description data to test pattern application steps (cycles) performed for facilities and signal data types and RTL facilities, observation steps for observing operation results, and RTL description. Generate information on the pattern value of the applied facility.

The storage unit 4 for storing the data of the test series for verifying the behavior-level description is composed of a test-specific description for describing the input test series and the expected value series, a hardware design description for describing the test series, and the like. It stores intermediate data of the input test series and the expected value test series after being compiled or after the pattern description given by the command of the behavioral level simulation apparatus is converted by the translation apparatus.

The test sequence generation unit 5 for inputting the RTL description and for generating the expected value test sequence generates a test sequence from the storage unit 4 for storing the input test sequence and the expected value sequence for verifying the behavioral description and the behavior level specification. Description and RT
A control step in which a test pattern is applied to an input port of the RTL description generated by the correspondence creating unit 3 with the L description;
The frame data of the test pattern is created using the information of the control step in which the internal operation of the TL description is executed and the result is observed, and the test series is converted based on the frame to generate the RTL test series. .

The RTL description input and expected value test series data 46 are the RTL test series and expected value data generated by the test series generation unit.

FIG. 2 is a diagram for explaining behavior-level test series data 4 and RTL test series data 6.

First, the behavior level test pattern will be described. When a test pattern is applied, a circuit including behavioral level description performs data operation according to the procedure in the description and outputs the result from the output port without delay. The concept of time is not introduced only in the operation and order of operations. Therefore, the test sequence also does not have the concept of time, and if it is input to the behavioral circuit model, outputs can be obtained at the same time.

FIG. 2A is a diagram for explaining data related to a behavior level test series. In reality, there are many test sequences, but in this embodiment, 3 for the sake of simplicity.
Shows two test series. This table has a test sequence number for identifying a test sequence, an input port name for applying or observing a pattern, an internal variable name, and an output port name. Input / expected value determination information is stored as an attribute of a port or a variable. IN indicates an input pattern, and EXP indicates an expected value pattern. The numbers in the row of the test sequence numbers are the values of the test patterns. In this embodiment, the data types are all displayed as integers for simplicity (the pattern values depend on the data type of the port, for example, Real number, integer,
Bits, bit strings, etc., are stored according to their type). An expected value is stored in the output port column of the internal variable, which is generally created from the result of the behavior level simulation. It is not necessary to observe the values of all internal variables, and one row in the table of FIG. 2 (a) to be observed when the behavior description is converted to the RTL description and remains as a register is 1
It is a test pattern per operation and an expected value pattern.

Next, the RTL test sequence will be briefly described. The RTL circuit, which is a sequential circuit, returns to the initial state and repeats the operation when the data fetched from the outside is finished while transitioning from the initial state to the next state. In this embodiment, this state transition is called a control step, and each step is indicated by a state identifier. The test series includes an input test series necessary for calculation in each state and an expected value series of outputs observed in each state.

FIG. 2B is a diagram for explaining the test series data of the register transfer leveling. FIG. 2B shows a part of a large number of test sequences. This embodiment will be described using a test sequence for verifying the operation in three states.
a and b are input ports, r1 and r3 are registers, and z1 is an output port. In this embodiment, the data type of the input, register and output port is integer, but it may be bit or bit string. For the sake of simplicity, an integer example will be described here. The input and expected value discrimination information is the same as the behavior level test sequence. The test sequence 1 shows the pattern of state 1, and the value "1" is input to the input port a and the input port b
The value '2' is applied to. In the state 2 of the test sequence 2, “-” is written in the inputs a and b, which means that any value may be used as long as the data types are the same. (It is called a don't care pattern). The expected value of the register r1 is "3". In the state 3 pattern of the test sequence 3, the expected value of the output port z1 is “5”.

With reference to FIG. 3 to FIG. 5, a description will be given of a correspondence generation unit for the behavior level specification description and the RTL description. First, the command, the information generated by the physical constitution preparation cloth, and the processing flow of the preparation unit will be described.

FIG. 3A is a view for explaining a command input description relating to a behavior level specification description and an RTL description correspondence creating section. The command gives the correspondence information between the RTL facility and the variable of the behavior description.
"RTL IN "is a keyword for declaring the input port name of the RTL description, and a, b, c1 are the input port names.
"RTL "REG" is a keyword for declaring an RTL description register, and r1 and r3 are register names.
L “OUT” is a keyword that declares the output port name of the RTL description, and z1 is the output port name. I
“N” is the input port name of the behavior description and is “BL VA
"R" is a variable, "BL "OUT" is a keyword for declaring the output port name, and the characters after the keyword are the respective names. "EQUAL" associates the RTL port name or register name with the behavior description port name or variable name. Command for "(a: a)"
Indicates that the RTL input port “a” (first a) corresponds to the behavior description “a” (second a).
"(Z1: z1, z2)" is the RTL output port "z
1 ”corresponds to“ z1 ”and“ z2 ”of the behavior description. That is, the output port“ z1 ”of the RTL time-divides the values of“ z1 ”and“ z2 ”of the behavior description. Is output.

Although FIG. 3B exists in the RTL description,
It shows the command to input the information of the port that does not exist in the behavior description. The keyword has the same meaning as in FIG. 3A, "IN" indicates a port or register to which the input pattern is applied, and "EXP" indicates a port or register to observe the expected value pattern. ":
= 'P' ”means the application of positive pulse,“: = ”
L ′ ”indicates a 1-bit expected value 0, and: =“ LHL ”indicates a 3-bit expected value 010 related to the register r4. Further, an expression is described after“: = ”to indicate the value of the input pattern. It can be selected depending on the condition, or the pattern value of the current control step can be calculated by using the value of the pattern one control step before (a detailed example will be described later).

Although the command has been described above as an example, the correspondence creation unit of the behavioral level specification description and the RTL description of the present invention is not limited by the command, and the information given by using the command is not limited to other information. It may be given by means such as a table-type input means or an attribute description of a hardware description language.

FIG. 4A is a diagram for explaining the correspondence information generated by the correspondence creation unit for the behavior level specification description and the RTL description. The data of this figure is created by (1) taking in and analyzing the data of the command, the behavior description and the RTL description as in this embodiment, or (2) inputting from outside the device of the present invention by the designer. It is given by the device or (3) obtained from the reference information created by the high-level synthesis device.

Ports of RTL description, registers, names of signals, and their data types (INTEGER in the example)
And apply test sequences to these facilities,
The control step information whose output is observed is stored. State 1 is a state number indicating the first state. R
In the TL description, different patterns may be applied or observed in different states for the same port, and in this case, there are a plurality of control steps for the same port. In the figure, the port z1 of the RTL description corresponds to the ports z1 and z2 of the behavior description, and further, the names of the ports of the behavior description corresponding to the ports of the RTL description and their data types are stored. .
The data types include bits, bit strings, integers, real numbers, and record types having these as elements.

In FIG. 4B, the data type relating to a port or register which is present in the RTL description but not in the behavioral description, the pattern application or control step to be observed, and the application fetched from the above command. Alternatively, it shows the observation discrimination information and the pattern value. In this embodiment, an example of the clock signal clk, the system reset signal rst, and the scan-out signal so is shown. c
The lk signal is 1 bit, and the positive pulse (P) of the input pattern “010” is applied to each step of the states 1 to 3. Further, when the calculation formula of the pattern value is given, the area for storing the pattern value of this figure stores not the pattern value itself but the information indicating the relation with the calculation formula.

FIG. 5 and FIG. 6 are views for explaining the processing flow relating to the correspondence generation unit for the behavior level specification description and the RTL description. This preparation section will follow the steps below.
1 (a), (b) behavioral level specification description and RT
Information corresponding to the L description is created. The start and end of processing are indicated by the terminals 101 in FIG. 5 and 111 in FIG. Step 10
2-110 shows a process. RTL input, register, output facility name, input / expected value discrimination information, command consisting of pattern value, behavior level input,
Commands for declaring variables and output port names and command information (Figs. 3 (a) and 3 (b)) in which RTL port names and register names are associated with ports and variable names in behavior description A port, a register name, a corresponding behavior level port name, and a variable pattern value are set (step 102), RTL description data is fetched (step 103), and behavior description data is fetched (step 104). The data type and bit width of the port and the register fetched from the command are extracted and set using the RTL data fetched in 103. (Step 105) Similarly, the behavior description data fetched in Step 104 is set. And use it to extract the data type of the port or variable imported from the command. Tsu to door (step 106) .RT
Using the data described in L, a state number for identifying the order of the states is created, and the facility name read / written in each state is obtained (step 107). For example, create internal data as shown in the table below. In the state 1, the revolt occurs in the facilities a and b, and the state 2
Then, writing occurs in the facility r3.

[0046]

[Table 1] It is checked whether reading and writing occur in different control steps (step 108). If YES, obtain the order in which the ports and variables in the behavior description corresponding to the facility imported from the command appear in the behavior description, and compare this with the state number at which the facility is read and written,
Correspondences between facilities in each control step and ports and variables in behavioral description. In the above example, since the pattern is output to the state 2 and the state 3 for the output port z1, the order in which the ports z1 and z2 of the behavior description corresponding to the port name z1 of the RTL appear in the behavior description is extracted, and the former Compare them with the order of the control steps and take a correspondence between them. Then, z1 of state 2 corresponds to z1 which appears first in the behavior description, and z1 of state 3 corresponds to z2 of the behavior description (step 109). In the case of NO, the control step of the input port, the register and the output port is set using the information created in step 107 (step 110). The data of FIG. 4A is generated through the above steps. Figure 4
The data input and output of (b), the facility name and data type of the register, and the control step are created in the above process flow, and the input and expected value determination information and the pattern value are the values input from the command. Set.

The test sequence generation unit is composed of a test sequence frame information generation unit and a test sequence conversion unit. A processing flow relating to the first series of frame information generation of the test sequence will be described with reference to FIGS. 7 to 9. Here, only the processing flow will be described, and a detailed description using the motif will be described later.

Reference numeral 201 in FIG. 7 and 218 in FIG. 8 indicate the start and end of processing at the terminals. Steps 202 to 217 indicate processing. The input port name, the internal variable name, the output port name and the discrimination information of input or expected value are fetched from the behavior-level test series data (step 202). Correspondence between specification description at behavior level and RTL description Input and output port of RTL description, control step information of register, and input of behavior description corresponding to control step of each port or register of RTL description created by the creating unit 3. , Output port name, internal variable name are imported. The port name and input newly added to the RTL description and the expected value discrimination information are fetched (step 203). The control step information in the RTL description is analyzed to find the number of states, and the number of states required for execution is taken as the number of pattern fields. Also, the related information of each field and the state number is created (step 204).

From the correspondence information on the ports of the behavior description and the RTL description fetched in step 203, the number existing as the input port of the behavior description and also as the input port of the RTL is set as the number of input test sequence columns, and each column is Information corresponding to the port name in the RTL description is created (step 205). The number of ports in the RTL description may be smaller than the number of ports in the behavior description (1 port is used by multiplexing), but in this case, there is no problem in creating a column of RTL ports. On the contrary, since a port which does not exist in the behavior description may be added to the RTL description, it is first checked whether the added input port and the value of the pattern are known (step 206). In the case of YES, the column number of the added port is added to the above column number, and the column and the RTL port name are associated (step 20).
7). If NO, the process proceeds to step 208. Step two
By using the correspondence information between the register of the RTL description and the internal variable of the behavior description, which is taken in 03, information on whether the internal variable of the behavior description is applied or observed is taken out to check whether it is an applied pattern (step 208). If YES, recalculate the number of columns in the input pattern
Corresponds to the register name in the TL description (step 20)
9). If NO, set the number of columns in the expected value pattern,
Correspondence between the column and the register name of the RTL description is obtained (step 210).

It is checked whether or not there is a register added to the RTL description (step 211). If yes, go to step 211; if no, go to step 21.
Go to 5. Information on application or observation of the additional register of the RTL description taken in at step 203 is taken out to check whether it is an application pattern (step 212). If YES, the number of columns in the input pattern is recalculated, and the columns are associated with the register names in the RTL description (step 21).
3). If NO, set the number of columns in the expected value pattern,
Correspondence between the column and the register name of the RTL description is obtained (step 214). Similar to the input port, it exists as an output port of the behavior description from the correspondence information of the RTL description and the port of the behavior description captured in step 203,
Moreover, the number that also exists as the output port of the RTL is added to the calculated expected value column number to create the correspondence information between the column and the output port of the RTL description (step 215).

For the output port which does not exist in the behavior description but exists only in the RTL description, it is checked whether or not there is a name or applied / expected value discrimination information and the expected value pattern is known (step 216). In the case of YES, the number of additional output ports is added to the number of expected value columns, and correspondence information between columns and output port names in the RTL description is created (step 217). N
If O, go to step 218. The frame information of the test pattern is created by the above processing.

Next, a test sequence generation process will be described. Reference numerals 301 and 306 in FIG. 10 indicate the start and end of processing at terminals. Reference numerals 302 to 305 denote processes. The port information is fetched from the frame information of the RTL test pattern, the correspondence information between the behavior level specification description and the RTL description, and the behavior level test sequence (step 302).

However, this generation process is not necessary when the correspondence information between the behavior-level specification description and the RTL description and the generation of the test pattern frame information are performed subsequently. One behavior-level test series is extracted from the behavior-level test series data (step 30).
3). Using the frame information, the input pattern value and the expected value pattern value are substituted into the column of the corresponding field (step 304). Capture all patterns and R
It is determined whether a TL test pattern has been generated (step 305). If YES, the process ends. If NO, the process returns to step 303, and steps 303 to 305 are repeated.

Next, the embodiments of the present invention will be described in detail by taking the description in the hardware design language illustrated in FIGS. 11 and 12 as an example. First, three motif circuits will be described. These are circuits described in VHDL (IEEE standard hardware design language). E in VHDL
Although it is necessary to describe the external interface of the circuit with a keyword called "unity", it is omitted in this embodiment because it is not important.

FIG. 11A shows a circuit which is composed only of data calculation. The input ports are a, b, c1 and c2 and the data type is an integer, and the output ports are z1 and z2 and the data type is an integer. In the description below, the main body of the circuit is described, and statements from process to end process are sequentially processed. r
1, r2 and r3 are internal variables and “: =” is a substitution. Further, “<=” is a substitution when the left side is a signal. “+” Is addition, and “−” of “r2: = − r1;” is sign inversion. Of process after () sensitivity list referred to as the signal written in, when an event to at least one occurs, Begi in the statement process
n or less circuits are executed in order, and end pro is used until the next event occurs in the signal of the sensitivity list.
Wait at cess. Substitutions into r1, r2 and r3 are executed without delay, but substitutions into z1 and z2 require a very small time called delta delay. However, delta time is ignored here. In other words, the behavioral level circuit consisting of this description, if a value is given to the input port,
It can be regarded as a circuit that is sequentially processed and the value is instantly calculated and output to the output port.

FIG. 11B shows an example of the RTL description generated by the high-order synthesis apparatus after the designer has manually or modified the RTL description, or the circuit manually designed by the designer. The sequential sentences below the process sentence are separated by three wait until sentences. The wait until clk = '1' waits for further execution in the wait statement until the 1-bit clock new number clk changes from '0' to '1'. When clk rises, the signal assignment statement is executed until the next wait statement. Up to the first wait statement, state 0 is the initial state (state name 0 does not exist, so state number 0
, The assignment to r1 is state 1, and r3 and z
The output to 1 is state 2 and z1 below is state 3
Is. However, the state 0 up to the uppermost wait statement is an initial state, and is a state taken only once after the operation starts. Since the signals r1 and r3 are referenced in a state different from the assigned state, they operate like registers.

FIG. 11 (c) is a circuit for selecting the execution of the operation and the result according to the condition, and the input ports are a, b, c0,
, The data type is integer, the output port is z, and the data type is integer. if (a <b) is a conditional statement that selects a variable assignment statement of not more than then and a variable assignment statement of less than else as a result of the comparison of the values of a and b. The'- 'in the variable assignment statement under else is subtraction.

FIG. 11D shows an RTL circuit described through a design process similar to that shown in FIG.
Signal assignment statements are separated by t and until statements. Up to the first wait statement is the initial state (state 0), a + b and ab are selected and executed under the condition a <b, and the value is assigned to the register r1. Further, the result of the condition a <b is also held in the register r2 (state 1). State 2
Then, the output to z is further selected by the value of r2 latched in the state 1, and when r2 is false, it is added to c0 to r1 and output to z.

FIG. 12A shows a circuit which has a loop description and which adds a coefficient of "1" stored in a of a bit string. The input port is a and the data type is a 4-bit bit string, and the output port is z and the data type is an integer. for--
The-statement is a loop statement in which the variable assignment statements up to end loop are repeated four times. tmp (0) and '
1'is the logical product of the value of index 0 of the array tmp and the bit '1'. That is, tmp
When lsb (minimum bit) of 1 is 1, cnt is added by 1. shr is a function that shifts the value of tmp to the right,
Here, one bit of the second argument is shifted.

FIG. 12B shows an RTL circuit for FIG. 12A which has undergone the same design process as FIG. 11B.
This is a five-state circuit in which signal assignment statements are separated by four wait until statements. The first wait statement is the initial state (state 0) and the signal cnt is initialized. In the next state (state 1), the value of the 0th bit of the input port a and the bit "1" are ANDed, and if true, 1 is added to cnt. In the following states, the value of the index of different a and the bit "1" are ANDed, and the element of a counts the number of values "1".

The test sequence generation algorithm will be described by taking the motif description shown in FIGS. 11 and 12 as an example. It is assumed that the behavioral description in FIG. 11A is converted into the RTL description in FIG. 38B by high-level synthesis or manually. Figure 11
A behavior-level test sequence for verifying the behavior description in (a) will be described with reference to FIG. Input ports a, b, c1 and c2 have integers 1, 2, 8, 1 (8
2 and 1 are not shown in FIG. 2A),
The expected values of the internal variables r1 and r2 are 3 and -3, respectively, and the expected values of the output ports z1 and z2 are 5 and 4, respectively.
Next, the correspondence information between the behavior-level specification description and the RTL description will be described with reference to FIG. Behavioral test patterns are applied to the input ports a, b, and c1 of the RTL description as state 1, state 1, and state 2 respectively.
To the output port z1 of the RTL description, the result of the behavior description z1 is obtained in the state 3.
Z2 results are obtained. However, the value of z2 is not output in the first state, and the value is output only in the fourth state. Similarly, the expected values of the variables r1 and r3 of the behavior description are obtained in the registers r1 and r3 in the states 2 and 3, respectively. For simplicity, the data type of the port register is the same as the data type of the corresponding port or variable in the behavior description. For the newly created port clk in the RTL description, the pattern information of the command input from the outside is stored. The data is shown in Figure 4.
It becomes like the line of clk in (b). A 1-bit input pattern (pattern of positive pulse 010) is applied in states 1, 2 and 3.

According to the processing procedure of FIGS. 7 to 9, FIG.
Creation of frame information regarding the test sequence of the RTL description in (b) will be described.

The port name, the internal variable name, the input and the expected value discrimination information are fetched from the behavior level test series data 4 into the memory of the test series generating section 5.

[0064]

[Table 2] Next, the behavior-level specification description and RTL in FIG.
The information corresponding to the description is taken into the memory of the test sequence generator.

Next, frame information of the RTL test series is created. Since the maximum number of states in the RTL description is represented by the last state number (state 3) of the output ports, the number of states counted from the initial state is counted. The maximum number of states 3 is the number of fields (number of rows) in the test sequence. Create a relationship between fields and state numbers. Field 1-> State 1 Field 2-> State 2 Field 3-> State 3 The number of input ports in the RTL description is 4, and this is the number of columns in the input pattern. Create a correspondence between the Koran number and the port. Also, the port and the variable name of the behavior description corresponding to the RTL facility are taken out, the information taken in the memory is used to determine the information whether the pattern is an input or an expected value, and the information is registered in the frame information. The port clk newly created in the RTL description is registered in the frame.

A pattern column is also created for a register described in RTL. Check whether the pattern is applied or observed. Behavior description variable r1 corresponding to register r1
From the discrimination information of, the expected value pattern is obtained.

The output port of the RTL description is similarly registered in the frame. The frame generated in this way is as shown in FIG.

In this embodiment, the data type of the port is described as an integer, but the behavior level specification description and the RT
The number of columns of the pattern is ensured according to the data type to create a frame by using the information of the data type correspondence between the RTL port and the behavior level port of the correspondence information with the L description.

Purification of a test sequence using frame information will be described according to the processing procedure of FIG. FIG. 10 shows frame information, behavior-level specification description, and R.
Although it is described that the correspondence information with the TL description, the port name at the behavior level, and the capture are included, it is not necessary to capture these information if they already exist in the memory. Behavior level test pattern "1, 2, 8, 1, 3, -3,-
-, 5, 4 "(see FIG. 2A for this value). The behavioral test pattern is set in the control step by using the correspondence information between the behavior level specification description and the RTL description. For port a, the behavior a pattern “1” is set in state 1 (see FIG. 4A and FIG. 2B). Set the pattern “1” of b. If the data type of the port of the behavior description is different from that of the RTL description generated in the same way for other ports and registers, for example, the port of the behavior description is an integer and the port of the RTL description is If the port is a bit string, it is converted into a bit representation pattern of the bit width of the port and set.

Although the bidirectional port described in the RTL is not described in this embodiment, the application and the output of the test are observed with respect to the same port, and this embodiment is expanded assuming that the applied state and the output state are different. This can be done easily.

Even when a conditional statement exists as in the motif description of FIG. 11C, the test sequence and the expected value sequence of the RTL description are generated by using the processing flows of FIGS. 9 and 10 of this embodiment. it can. FIG. 14A is a test sequence for verifying the motif of FIG. 11C, and FIG. 14B is an RTL test sequence generated using this embodiment. For the test and expected value series of input and output facilities,
It is automatically generated using the above processing flow.

However, in the RTL description of FIG. 11D, the register r1 has a different meaning from the variable r1 of the behavior description. Register r2 that does not exist in the behavior description
Since there is a part different from that of FIG.
The processing relating to this point will be described. The value of the test series is a>
In the case of b, the expected value of the variable r1 of FIG. 11C cannot be used as the expected value of the register r1 of FIG. 11D, or the register r2 is a newly generated facility, so the pattern information is Absent. Therefore, FIG. 14 (c)
As described above, the input pattern of the positive pulse'P 'is input to clk, and for the register r1, the value of the input pattern a + b is set as the expected value when the condition a <b is true, and a-b is set when it is false. The calculated value of is the expected value. Similarly, the expected value of the register r2 is "H" when the condition a <b is true, and "L" when it is false. The formulas for calculating the values of these patterns are used when the test sequence generation unit generates the patterns of FIG. 37, that is, after the values of the behavior-level test patterns are captured, and the expected values are calculated (FIG. 10).
(Not shown in) but set. As described above, the expected value pattern can be generated by externally setting via the command in the correspondence creating unit for the behavior level specification description and the RTL description.

As for the motif description in FIG. 12 (a),
By performing the same processing as in the case of FIG. 11A, the test series and the expected value series of the RTL description can be generated. FIG. 15 (a) shows FIG.
9 (a) is a verification test series of behavior description. Four
When "0101" is applied to the bit input port a,
It is expected that the variable cnt and the output port z will be 2. The circuit of the register transfer description in FIG. 12B operates in four states. Also, cnt becomes a register. Since the expected value of the variable described in the behavior cannot be used as the expected value of the register cnt in the states 1 to 3, if it is desired to observe the value of cnt in these states, it is necessary to manually give it. FIG. 42 (c) shows a command that gives the expected value of cnt. "RTL REG ”is a command that declares the name of the register as described above.
EXP is an expected value, and the expression below ": =" is an expression for calculating the expected value. cnt + CASE --- is c of the previous state
The expected value of cnt in each state can be calculated by adding the number of 1s in the 4-bit value of a obtained by the CASE formula to the value of nt. In this way, the expected value pattern can be generated by externally setting the behavior level specification description and the RTL description in the correspondence creating section via a command.

As described above, since the test pattern and the expected value pattern to be applied not only to the input and output ports but also to the register can be generated, the device of the present invention is very effective in generating the test sequence for verification. is there.
Therefore, it is possible to generate a test sequence and an expected value sequence using this test sequence generation device, perform an RTL simulation using these sequences, and verify whether the corrected RTL description is equal to the behavior specification.

On the other hand, although a circuit module that has already been verified is often incorporated in another large-scale logic system, the problem in testing this logic system is not the internal operation of the circuit module, but the problem. This is the part of the interface with other modules. Therefore,
It is efficient in terms of handling to perform a simulation at a behavioral level with a higher degree of abstraction. In this case, it is necessary to rewrite the RTL description of the circuit module into the behavior description, and it is also necessary to create a behavior-level test pattern for verifying whether or not the rewriting is correct. Next, an apparatus for generating a behavior level test pattern from a test pattern in the RTL description will be described as a second embodiment of the present invention.

FIG. 16 shows a block diagram of the second embodiment of the present invention. In this embodiment, the RTL test pattern storage unit 11, R
It comprises a TL description storage unit 12, a test pattern processing unit 13, and a test expression form changing unit 15.

In the following example, the unit time of the RTL test sequence is a clock cycle for controlling the state transition, and the RTL test sequence starts from the initial state. In the following example, the VHDL model is used as the language for describing the RTL. To describe the state machine, use a process statement that represents sequential processing, and use a signal that represents a clock as c.
It is designated as lk, and the state transition synchronized with the clock is represented by the statement of wait on clk.

In the present embodiment, for simplicity, it is assumed that when a behavior description equivalent to this is created from the RTL description, input / output is associated one-to-one and the name is not changed. Even if a rule for creating such a behavior description is not specified, the correspondence relationship between the names of the behavior description and the RTL description can be realized by providing the correspondence information.

Consider an example in which the behavior description shown in FIG. 18 is created from the RTL description shown in FIG. It is assumed that the test series of FIG. 19 is given as the RTL test series. The configuration of the RTL analysis unit is shown in FIG. The RTL analysis unit includes a flow graph creation unit (14-1), a state identification unit (14-2), and an internal table creation unit (14-3). In the RTL description in which the state transition is explicitly described, the flow graph creation unit (1
No processing is performed in 4-1) and the state identifying section (14-2). The internal table creation unit (14-3) creates an internal table necessary for the test pattern processing unit, such as a state transition table, an input / output valid state table, a state merge impossible information table. Instead of the state transition table, another data structure representing a state machine such as a state transition graph can be used.

In the RTL description of this example, since the state transitions are composed of sequential processing statements that are not explicitly described, the process of creating a flow graph is required. Flow graph creation unit (14-
The processing flow of 1) is shown in FIG. Explaining along an example, the flow graph creation unit (14-1) uses the RTL of FIG.
Nodes are created for the signal substitution statements ,,, in the description (step 1). Next, it is assumed that one sentence is taken out in the processing step, but the sentence is taken out first, and then the sentence is taken out as a signal assignment statement executed subsequently to the statement in the processing step (step 3). Here, the flow graph creation unit F1 adds a branch e = (v1, v2) from the node vl corresponding to the sentence to the node v2 corresponding to the sentence (step 4). Since the statement is executed unconditionally after the statement except for the wait condition, the condition label Lc (e) is not set in the branch e in the processing step. However, since the wait statement exists between the two statements, the wait flag label Lw (e) is set to ON in the branch e in step G6. Since there is no signal assignment statement to be executed after the statement other than the statement, the process proceeds to step 8 after step 7. By applying the processing steps 2 to 8 to all the signal assignment statements in this way, the flow graph shown in FIG. 22 is generated. In this example, since all the statements are executed unconditionally except for the wait condition, no condition label is attached to the branch of the graph in FIG. Also, wait on cl in the middle of the sentence represented by the end points of the branch
If there is a k statement, the wait flag label of that branch is set. In FIG. 22, the branches e12 and e34 correspond to this. These branches will represent state transitions.

The state identifying unit 14-2 divides the graph by the branch in which the wait flag label is set. In FIG. 22, the state is divided into the branches e12 and e34, and (v1), (v2, v3), (v4, It can be divided into three subgraphs called v5). This divided subgraph is set to one state. Since the state of the description of FIG. 17 is not written explicitly, the state name is assigned by the state identification unit 14-2.
Automatically determines st0, st1, st2.

The internal table creating section 14-3 creates a state transition table based on the divided graph. In the graph of FIG. 22,
Since the condition labels of the branches e12 and e34 to be divided are not set, the state transition table shown in FIG. 23 has no state transition condition.

Next, the internal creating section 14-3 creates an input / output valid state table based on the flow graph. The input port a is referenced by the node v1 in FIG. 22, and the node v1 is in the state st0.
Belong to. As a result, st0 is registered in the "referenced / set state" column of a of the input / output valid state table. By performing this processing for all the inputs and outputs, the input / output valid state table shown in FIG. 24 is generated in this example.

Finally, if there are a plurality of states to be referenced / set in the column of each input / output port of the input / output valid state table, the internal table creating unit 14-3 cannot merge those states. As a result, a state merge impossible information table is created. In the input / output valid state table of FIG. 24, since all the input / output ports are referenced / set in only one state, there is no state that cannot be merged with each state, and the state merge as shown in FIG. Generate the impossible information table.

FIG. 26 shows the configuration of the test sequence processing section 13. The test sequence processing unit is a test sequence state correspondence creating unit 1 that associates each step of the RTL test sequence with a state.
3-1 and a test sequence compression unit 13-2 that merges successive steps of the test sequence.

FIG. 27 shows a processing flow of the test sequence status correspondence creating section 13-1. This process will be described with reference to the state transition table of FIG. 23 and the RTL test sequence of FIG. 19 according to the process flow of FIG. The variable (STT) representing the current state is set to the initial state st0 by the processing step A1, and step
Is set to 1. By the processing step A2, the RTL of FIG.
The first step in the test sequence is associated with the state st0. Since one step is not the final step, the process proceeds to processing step A4. Here, the next state of st0 and its transition condition are extracted from the state transition table of FIG. 23, but st0 is unconditional.
Since the transition to st1, the STT can be newly set to st1 without comparing the transition condition with the test sequence. The processing sequence A5 advances one step in the test sequence, and the same processing is repeated thereafter. When the processing flow of FIG. 27 is finished, a test sequence associated with each step state as shown in FIG. 28 is obtained.

Next, FIG. 29 shows a processing flow of the test sequence compressor 53-2. Describing along the processing flow, in processing steps B1 to B5, step = 1, step2 =
2, ST1 = st0, ST2 = st1. Since st0 and st1 can be merged according to the state merge impossible information table of FIG. 25, the process proceeds to step B7, and the first step and the second step of the test sequence of FIG. 28 are merged. At this time, from FIG. 24, the value of the first step corresponding to st0 for the input ports a and b and the value of the second step corresponding to st1 for the input port c are merged into the value of the test sequence. Since the input port d is not referenced by either st0 or st1, either value may be taken. Next, in processing step B9, st1 is added to ST1 to set ST1 = st0, st1,
This time, the processing is performed for the merged first step and third step. By processing steps B4 and B5, step2 =
3, ST2 = st2. According to FIG. 29, st2 is st0, st1
Since both can be merged, the merged first step and third step are merged. The value of the input port d is set to the value of the third step, which is st2. Since the test sequence is now the last line, the process ends. As a result, a test sequence as shown in FIG. 30 is generated.

Finally, the test expression form changing unit 55 associates the variable name of the test sequence with the data type. In this embodiment, when the behavior description is created from the RTL description,
I / O is performed under the rule that there is a one-to-one correspondence and the name is not changed. Therefore, by comparing the input / output definition parts of the behavior description and the RTL description, the data type of the RTL description and the behavior description are compared. Create a data type correspondence table. Next, based on this correspondence table, the data expression form of the test pattern generated by the test sequence processing unit is changed. In the present embodiment, neither the RTL description of FIG. 17 nor the behavior description of FIG. 3 is changed to an integer data type, so the test series of FIG. 30 becomes the final behavior test series.

As another example, consider an example in which the behavior description shown in FIG. 32 is created from the RTL description shown in FIG. It is assumed that the test sequence of FIG. 33 is given as the RTL test sequence. From the RTL description of FIG. 31, the RTL analysis unit (4)
Create a flow graph like 4. The difference from the previous example is that the sentence that can be executed next to sentence (4) in FIG. 31 is the sentence (4) itself and the sentence (8) depending on the condition. , It becomes a graph with branching. The state transition table is also a table having transition conditions as shown in FIG.
The input / output valid state table of FIG. 36 and the state merging impossible information table of FIG. 37 can be generated in the same manner as the previous example.

Then, according to the processing of the test sequence state correspondence creating unit of FIG. 27, it is determined which state each step of the RTL test sequence is in from the state transition table of FIG. 33 and the input value of the RTL test sequence of FIG. (FIG. 38). Unlike the previous example, since there is a condition in the state transition, processing step A4
Then, the input value (a
FIG. 33 shows the next state of st0 for which the transition condition is = 0, b = 0).
Search more and extract. It can be seen from FIG. 33 that the next state under this condition is sa0, and st0 at the step in FIG.
It can be seen that it is. Such processing is repeated, and FIG.
A test sequence like 8 is obtained.

Next, according to the processing of the test sequence compressing section of FIG. 28, the steps of continuation of the test sequence of FIG. 38 are merged. In this example as well, there is no state that cannot be merged as in the previous example, but if the same states appear consecutively, they cannot be combined, so the test sequence is as shown in FIG.

Finally, the test expression form changing unit changes the data type and generates the behavior test sequence.
If there is no change in the data type, the behavior test sequence shown in FIG. 39 is obtained.

[0093]

According to the first aspect of the present invention, since the RTL test series and the expected value series whose specifications have changed can be automatically generated, the time required for manually creating the test series is significantly reduced. it can. In addition, there is an effect that bugs do not enter because no human intervention is required. Furthermore, since the test according to the specification change of the RTL description and the correction of the expected value series can be performed in a short time by using the device of the present invention, there is an effect that the design verification time of the RTL description is significantly shortened.

According to the second aspect of the present invention, the behavior test sequence can be created from the RTL test sequence, and when the behavior description which is the specification is created from the RT description, is the behavior description correct as the specification? The work of verifying by simulation can be performed efficiently. Then, it becomes possible to use the behavior description created from the RTL description, and when verifying a large-scale system including some pre-designed circuit modules, those pre-designed circuit descriptions designed by RTL can be used. It is possible to improve the efficiency of verification of the entire system by rewriting the behavior description and performing simulation at a faster behavior level for those parts. This also leads to improvement of design efficiency by reusing resources, which is very useful when actually designing a large-scale system.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a test sequence generation device according to a first embodiment of the present invention.

FIG. 2 is a conceptual diagram of data in a test series storage unit.

FIG. 3 is an explanatory diagram of commands fetched by a behavior level specification description and RTL description correspondence creation unit.

FIG. 4 is a data conceptual diagram of correspondence information between behavior-level specification description and RTL description.

FIG. 5 is a diagram showing the first half of the processing flow of the correspondence creating unit for the behavior level specification description and the RTL description.

FIG. 6 is a diagram for explaining the latter half of the flowchart of FIG.

FIG. 7 is a diagram showing the first part of the frame information generation processing flow of the test sequence generation unit.

FIG. 8 is a diagram showing an intermediate portion of the flowchart of FIG.

9 is a diagram showing the final part of the flowchart of FIG. 7. FIG.

FIG. 10 is a diagram illustrating generation of a test sequence by a test sequence generation unit.

FIG. 11 is a diagram illustrating behavior description and RTL description.

FIG. 12 is a diagram illustrating behavior description and RTL description.

FIG. 13 is a diagram illustrating frame information of an RTL pattern.

14 is a behavior description of FIG. 11 (c) and FIG.
The figure explaining the test sequence of the RTL description of (d).

FIG. 15 is a behavioral description of FIG.
The figure explaining the test series of the RTL description of (b).

FIG. 16 is a diagram showing a configuration of a system according to a second embodiment of the present invention.

FIG. 17 is a diagram showing an example of RTL description.

FIG. 18 is a diagram showing an example of behavior description.

FIG. 19 is a diagram showing an example of an RTL test sequence.

FIG. 20 is a diagram showing an outline of a processing flow of an RTL analysis unit.

FIG. 21 is a diagram showing a processing flow of a flow graph creation unit of the RTL analysis unit.

FIG. 22 is a diagram showing an example of a flow graph.

FIG. 23 is a diagram showing a state transition table.

FIG. 24 is a diagram showing an input / output valid state table.

FIG. 25 is a diagram showing a state merge impossible information table.

FIG. 26 is a diagram showing an outline of a processing flow of a test series processing unit.

FIG. 27 is a diagram showing a processing flow of a test sequence state correspondence creating unit of the test sequence processing unit.

FIG. 28 is a diagram showing an RTL test sequence in which states are associated with steps.

FIG. 29 is a diagram showing a processing flow of a test sequence compression unit of the test sequence processing unit.

FIG. 30 is a diagram showing a behavior test series.

FIG. 31 is a diagram showing an example of RTL description.

FIG. 32 is a diagram showing an example of behavior description.

FIG. 33 is a diagram showing an example of an RTL test sequence.

FIG. 34 is a diagram showing an example of a flow graph.

FIG. 35 is a diagram showing a state transition table.

FIG. 36 is a diagram showing an input / output valid state table.

FIG. 37 is a diagram showing a state merge impossible information table.

FIG. 38 is a diagram showing an RTL test sequence in which states are associated with steps.

FIG. 39 is a diagram showing a behavior test series.

[Explanation of symbols]

1 Behavior level specification description 2 Register transfer level description 3 Correspondence section between behavior level specification description and register transfer level description 4 Behavior level test series data 5 Test series generation section 6 Register transfer level test series data 11 RTL Test pattern storage unit 12 RTL description storage unit 13 Test pattern processing unit 14 RTL analysis unit 15 Test expression form changing unit 16 RTL-behavior correspondence information 17 Behavior test pattern

Front Page Continuation (56) References Gerd Krueger, A Tol for Hierarchical Test Generation, IEEE Transactions on Computer-Aided Design, USA, April 1991, vol. 10 no. 4, p519-524 (58) Fields investigated (Int.Cl. ⁷ , DB name) G06F 17/50

Claims (2)

(57) [Claims] 1. A state transition of a register transfer level is identified from a behavior level specification description of a logic system and a register transfer level description corresponding to the specification description .
In each control step,
Signals for transmission level description and behavior level specification description
By performing the name and correspondence of ports, based on the correspondence creation unit, the test sequence data to verify the specification description to take correspondence between the specification description and the register transfer level description, the corresponding creation Obtained by the department,
Correspondence between specification description and register transfer level description
And a test sequence generation unit for automatically generating test sequence data at a register transfer level based on the above . 2. Analyzing information of state transition of RTL description
RTL analysis unit and state transition generated by the RTL analysis unit
Number of steps that require RTL test sequence based on information
RTL-behavior description
The RTL description and behavior description based on the correspondence information described above.
Facilities and variables that exist and their data types
The behavior of the test series by changing the form of the test series.
Test expressions that automatically generate via-level test sequences
A test sequence generation device including a state change unit.