JP3376138B2 - Method and apparatus for estimating node voltage of network - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method and apparatus for estimating a node voltage of a network, and more particularly to a method and an apparatus for estimating a node voltage of a network including an electron source at high speed.

[0002]

2. Description of the Related Art There are a number of linear circuit networks, and among them, two types, known as a thermionic depletion type and a cold cathode electron source, are known as display devices composed of electron-emitting devices. Cold cathode electron sources include field emission type, metal / insulating layer / metal type and surface conduction type electron emission devices. Particularly, the surface conduction electron-emitting device has an advantage that a large number of devices can be arrayed over a large area because of its simple structure and easy manufacture. Therefore, various applications that can make full use of this feature are being studied. Examples thereof include a charged beam source and a display device. In particular, an image forming apparatus, which is a display apparatus in which a large number of surface conduction electron-emitting devices are arranged and a phosphor that emits visible light by the electrons emitted from the electron sources, is a large-screen device. However, it is a self-luminous display device that can be manufactured relatively easily and has excellent display quality.

[0003]

An example of this self-luminous display device is shown in FIG. Referring to FIG. 6, this display device has a surface in which a n _{x number} of row-direction (or x-direction) wirings and n _y column-direction (or y-direction) wirings are provided in a vacuum container. The display device has a structure including an electron source substrate 1 in which conduction electron-emitting devices are arranged, and a face plate 86 having a phosphor that emits visible light when irradiated with an electron beam, in a position facing the electron source substrate 1.

Driving of a display device using the surface conduction electron-emitting device having the above structure will be described below. When driving and scanning the surface conduction electron-emitting device row by row, that is,
Consider a case where d _x1 of the wirings in the row direction is selected and driven. At this time, a voltage drop occurs due to the wiring resistance of the row and column direction wiring itself.

On the other hand, due to the drive voltage applied to the column direction wirings d _y1 to d _yn , the current flows through the row direction wiring d _x1 . Therefore, particularly when the voltage drop in the row-direction wiring is not negligible, it appears as the luminance distribution of light emission. Therefore, in the display device (collection of cold cathode electron sources) as described above, it is important to quantitatively analyze the influence of the wiring resistance.

Conventionally, a circuit analysis method and a node analysis method are known as methods for systematically analyzing a linear network using Kirchhoff's law. The circuit analysis method is a circuit equation obtained by applying the Kirchhoff's voltage law to each circuit with the circuit current J as an unknown: ZJ = E Z: Impedance matrix E: It is a solution to power. In this method, it may be troublesome to take an independent circuit, and it is considered unsuitable for analysis of a complicated circuit.

On the other hand, in the nodal analysis method, the nodal potential V is an unknown number, and the nodal equation obtained by applying Kirchhoff's current conservation law to each node: YV = I Y: Admittance matrix I: Connected to the node It is for solving the electric current from the current source. If a voltage source is connected to the node, convert it into an equivalent current source. Since this method can make the node potential an unknown number, the method of taking the unknown number is unique and has an advantage that it can be easily applied to a complicated circuit.

However, when a large-scale circuit is analyzed by the nodal analysis method, when trying to solve the nodal equations as simultaneous linear equations, the number of unknowns becomes large, and a great amount of calculation time is required to obtain the nodal potentials. There was a point. The present invention has been made in view of the above conventional example,
It is an object of the present invention to provide a circuit network analysis method and apparatus capable of obtaining a node potential of a circuit including electrical elements and wirings at high speed with a physically clear and simple procedure.

[0009]

In order to achieve the above object, a method and apparatus for estimating a nodal voltage of a circuit according to the present invention have the following configuration. That is, one terminal of the resistive elements arranged in a matrix is connected to the row wiring, the other terminal of the resistive element is connected to the column wiring, and a predetermined wiring is provided between the row wiring and the column wiring. A nodal voltage estimation method for estimating a nodal voltage at one terminal of the resistive element and a nodal voltage at the other terminal of the resistive element in a configuration for applying a voltage, wherein the row-direction wiring and the row-direction wiring are provided. Each terminal of the resistive element to be connected for each wiring of 1 is a group, and each terminal of the resistive element to be connected to each wiring of the column direction wiring and the column direction wiring is one group. In this case, an initial value setting step of setting a predetermined initial value for each terminal voltage of each group, a simultaneous analysis system of nodal analysis regarding the node voltage of each terminal of the nth group of each group, and the initial value setting step. so A first updating step of calculating and updating the node voltage of each terminal of the n-th group based on the initial value of the node voltage of each terminal of the groups other than the n-th group determined; Nth
A nodal analysis of the nodal voltage of each terminal of the group Based on the simultaneous equations and the nodal voltage of each terminal of the groups other than the nth group updated in the first updating step, the nodal voltage of each terminal of the nth group is calculated. A second updating step for updating the node voltage, and that the node voltage of each terminal updated in the first updating step and the second updating step has converged based on the comparison with the node voltage before updating. And a determining step.

According to another aspect of the present invention, one terminal of the resistive elements arranged in a matrix is connected to a row wiring, and the other terminal of the resistive element is connected to a column wiring. In a configuration for applying a predetermined voltage between directional wirings, a nodal voltage estimation device for estimating nodal voltage at one terminal of the resistive element and nodal voltage at the other terminal of the resistive element, Each terminal of the resistive element connected to each of the row wiring and each of the row wiring is defined as one group, and the resistive element connected to each of the column wiring and the column wiring. When each of the terminals is grouped into one group, initial value setting means for setting a predetermined initial value to each terminal voltage of each group, and nodal analysis on the node voltage of each terminal of the n-th group of each group Coalition And first updating means for calculating and updating the node voltage of each terminal of the n-th group based on the initial value of the node voltage of each terminal of the groups other than the n-th group set by the initial value setting means. , The n-th group based on the nodal simultaneous equations regarding the node voltages of the terminals of the n-th group of the groups and the node voltages of the terminals of the groups other than the n-th group updated by the first updating means. Second, which calculates and updates the node voltage of each terminal of the group
And the determination means for determining that the node voltage of each terminal updated by the first updating means and the second updating means has converged based on the comparison with the node voltage before updating. Prepare

[0011]

In the above structure, one terminal of the resistive element arranged in a matrix is connected to the row wiring, the other terminal of the resistive element is connected to the column wiring, and the row wiring and the column wiring are connected. In a configuration for applying a predetermined voltage between the two, a nodal voltage estimation method for estimating nodal voltage at one terminal of the resistive element and nodal voltage at the other terminal of the resistive element, wherein Each terminal of the resistive element connected to each wiring of the wiring and the row directional wiring is defined as one group, and each of the resistive elements connected to each wiring of the column directional wiring and the column directional wiring When the terminals are grouped into one group, a predetermined initial value is set for each terminal voltage of each group, and a set of simultaneous equations for nodal analysis regarding the node voltage of each terminal of the nth group of each group is set. First Based on the initial value of the node voltage of each terminal of the groups other than the group, the node voltage of each terminal of the nth group is calculated and updated, and the node related to the node voltage of each terminal of the nth group of each group Based on the analysis simultaneous equations and the node voltage of each terminal of the groups other than the nth group updated in the updating step, the node voltage of each terminal of the nth group is calculated and updated, and the updated terminal voltage of each terminal is calculated. It is determined that the node voltage has converged based on the comparison with the node voltage before updating.

According to another invention, one terminal of a resistive element arranged in a matrix is connected to a row wiring, the other terminal of the resistive element is connected to a column wiring, and the row wiring and the column are connected. In a configuration for applying a predetermined voltage between directional wirings, a nodal voltage estimation device for estimating nodal voltage at one terminal of the resistive element and nodal voltage at the other terminal of the resistive element, Each terminal of the resistive element connected to each of the row wiring and each of the row wiring is defined as one group, and the resistive element connected to each of the column wiring and the column wiring. When each of the terminals is grouped into one group, the initial value setting means sets a predetermined initial value to each terminal voltage of each group, and the first updating means sets the nth group of each group. Regarding the node voltage of each terminal Based on the node analysis simultaneous equations and the initial value of the node voltage of each terminal of the groups other than the nth group set by the initial value setting means, the node voltage of each terminal of the nth group is calculated and updated, 2 update means,
The n-th group based on the simultaneous equations of nodal analysis regarding the node voltage of each terminal of the n-th group of the groups and the node voltage of each terminal of the groups other than the n-th group updated by the first updating means. The node voltage of each terminal is calculated and updated, and the determination unit determines that the node voltage of each terminal updated by the first updating unit and the second updating unit has converged. Determined based on comparison with.

[0013]

First Embodiment First, a brief description will be given of the configuration of a linear circuit analysis apparatus including an electron source according to one embodiment of the present invention, followed by a detailed description. A linear circuit network analyzing apparatus according to an embodiment of the present invention includes a terminal voltage measuring device that measures a terminal voltage of a linear circuit including elements and wirings, an input module that inputs terminal voltage data and circuit constant data, and a circuit. Display constants, nodal potentials and nodal currents, memory for nodal potential calculation programs, central processing unit for calculation processing, output module to output nodal potential calculation data, and nodal potential calculation data It has a nodal potential indicator.

The point of the processing by the nodal potential calculation program is a step of collecting nodal equations for each wiring to form one block, and repeatedly calculating the nodal potential for each block. In this process,
First, the node voltage in the block corresponding to each wiring is analytically obtained under the condition that the variable values of other blocks are fixed, and until the obtained variable values of each block converge to satisfy all the equations. , The potential of each node is obtained by repeating the above process repeatedly. Here, the initial value of each variable is, for example, a voltage value equal to the terminal voltage from the relationship between the wiring resistance and the surface conduction electron-emitting device resistance described later.

By this procedure, the linear circuit network analyzer including the electron source according to one embodiment of the present invention can obtain the node potential with high accuracy and at high speed. In addition, according to this method, it has been confirmed experimentally that the convergence of the solution is good. Hereinafter, the configuration of an analyzing apparatus for a linear circuit network including an electron source according to an embodiment of the present invention will be described in detail.

FIG. 1 shows the configuration of a linear network analysis apparatus including an electron source according to an embodiment of the present invention. Here, the terminal voltage measuring device 101 measures the terminal voltage of a linear circuit including an electron source element and wiring. Also, the input module 102
Inputs terminal voltage data and circuit constant data. Here, the circuit constant data includes expected values of the wiring resistance and the surface conduction electron-emitting device resistance.

The RAM 103 stores the circuit constant data input from the input module 102, the initial values of the node potential and the node current, the values during their calculation, and the like. ROM1
Reference numeral 04 stores a program that describes a processing procedure of analysis processing of a linear circuit network including the electron source of this embodiment. This program is read, interpreted and executed by the central processing unit 105.

The output module 106, based on the calculation result or the node potential data in the middle of the calculation, outputs the node potential indicator 107.
Is driven by analog or digital to display the nodal potential display 10
Display on 7. The nodal potential indicator is, for example, a display device such as a display device or a printer device. The terminal voltage of the circuit under test 110 driven by the circuit driving device 111 is taken into the terminal voltage measuring device 101 through the analog interface 108, AD-converted, and data together with the circuit constant data (circuit admittance) 112 through the digital interface 109. Input to the input module 102.

The node potential obtained by the processing described below is sent to the node potential display 107 through the data output module 106 and displayed as numerical data or a graph. The data input module 102 is an input device including a file device such as a floppy disk device and / or a keyboard.

The memory for storing the analysis program of this embodiment may be a RAM. Next, the processing of the analysis program of this embodiment will be described for an equivalent circuit of the electron source matrix circuit as shown in FIG. Where Rd (i,
j): (i = 1,2, j = 1,2) indicates the element resistance of the electron source, and for the sake of convenience of the reader, the case where four electron sources are arranged in a matrix is described for convenience. To do.

The size of this matrix is not limited to 2 × 2, and may be much larger. Referring to FIG. 2, Rx (i, j): (i = 1, 2, j = 1, 2)
And Ry (i, j) :( i = 1,2, j = 1,2) are the wiring resistances in the horizontal and vertical directions, respectively, and Rd (i, j): (i = 1,2, j
= 1, 2), the following relations exist for the order of resistance values. Rx (i, j) << Rd (i, j) Ry (i, j) << Rd (i, j) where (i = 1, 2, j = 1, 2) Since the voltage divided into j) and Ry (i, j) is much smaller than the voltage divided into Rd (i, j), it is assumed that the voltage is equal to or close to the terminal voltage value.

Now, the node x (1, j) is connected to the voltage source E (j) and the node y is
(i, 1) are respectively connected to the voltage source F (i), and the potentials of the nodes x (i, j) and y (i, j) are respectively U (i, j) and
If V (i, j), then the nodal equation is

[0023]

[Equation 4] And U (i, j), V (i, j): (i = 1, 2, j = 1, 2) is an 8-element simultaneous linear equation with unknowns.

Next, each line of the above simultaneous equations is modified as shown below, and is also grouped into blocks in which two lines are combined for each wiring. <First block: Wiring connected to E (1)>

[0025]

[Equation 5] <Second block: wiring connected to E (2)>

[0026]

[Equation 6] <Third block: Wiring connected to E (3)>

[0027]

[Equation 7] <4th block: Wiring connected to E (4)>

[0028]

[Equation 8] Then, for each of these blocks, the variables (node voltages U, V) appearing on the left side are analytically obtained by fixing the variable values of the other blocks. Since the equations for each block are binary simultaneous equations, they can be solved analytically easily and at high speed.

FIG. 3 shows a processing flowchart for obtaining the node voltages U and V. In step S1, a selection variable m for selecting each block is initialized to 1. The initial values of the node voltages U and V are, for example, as described above, the terminal voltages E (j): (j = 1, 2), F (i):
The voltage value is set equal to (i = 1, 2).

In step S2, each node voltage of the m-th block is determined by fixing the node voltages of the other blocks and analytically solving the equation of the corresponding m-th block. In addition, it goes without saying that various direct methods and iterative methods can be applied to this solution.

In step S3, it is checked whether the selection variable m is 2, and if it is not 2, the process proceeds to step S4, m is incremented by 1, and the process returns to step S2. On the contrary, if it is 2, the process proceeds to step S5. In step S5, it is checked whether the calculated node voltage values have converged.
The determination of convergence is made, for example, by checking whether the time differential values of all the node voltage values are within a predetermined error value. Here, if it is determined that it has not converged, the process returns to step S1 and the same processing is repeated until it converges. If it converges, it will progress to step S6 and each converged node voltage value will be displayed on the node potential display 107 via the output module 106.

As described above, the analyzer for the linear circuit network including the electron source of this embodiment can obtain the node potential with high accuracy and high speed. Also, according to this method,
It has been confirmed by experiments that the solution converges well. still,
In this embodiment, an example of obtaining each node potential in the matrix circuit including the surface conduction electron-emitting device having a size of 2 × 2 is shown, but this is not limited to this size.
It goes without saying that the present invention can be easily applied to a matrix circuit including a surface conduction electron-emitting device having a size of nxn. (Embodiment 2) In the embodiment 2, a method of obtaining each node voltage when the size of the matrix circuit including the surface conduction electron-emitting device is expanded to the size of nxm will be described.

In the matrix circuit including the surface conduction electron-emitting device as shown in FIG. 4, a processing example for obtaining each node voltage will be described below. Referring to FIG. 4, Rd (i, j): (i = 1,
2, ..., n _x ; j = 1,2, ..., _ny ) is the element resistance, and Rx (i,
j), Ry (i, j): (i = 1,2, ..., n _x ; j = 1,2, ..., n
_y ) is the wiring resistance, and the relationship between them is as follows. Rx (i, j) << Rd (i, j) Ry (i, j) << Rd (i, j) Further, the node X (1, j) (j = 1,2, ..., _ny ) is Voltage source E (j): (j = 1,2, ..., _ny ) at node Y (i,
1): (i = 1,2, ..., n _x ) is the voltage source F (i) :( i =
1, 2, ..., N _x ), respectively. Node X
Assuming that the potentials of (i, j) and Y (i, j) are U (i, j) and V (i, j), respectively, the node equation for the wiring in the x direction is

[0034]

[Equation 9] Also, the nodal equation for wiring in the y direction is

[0035]

[Equation 10] Becomes

These equations are simultaneous linear equations of n _x × n _y elements, but when n _x and n _y become large, when they are calculated based on the conventional analytical solution method, the direct method or the iterative method,
There is a problem that the calculation time becomes long. Therefore, in the linear circuit network analyzer including the electron source according to the second embodiment of the present invention, first, the above equations are summarized for each block regarding each wiring in the x-direction and the y-direction, and the following equation is obtained. To transform. <First Block Group: Wiring Connected to E (j) (j = 1, ..., ny)>

[0037]

[Equation 11] <Second Block Group: Wiring Connected to F (i) (i = 1, ..., Nx)>

[0038]

[Equation 12] Then, for each of these blocks, the variables (node voltages U, V) appearing on the left side are analytically obtained by fixing the variable values of the other blocks. Here, the equation for each block corresponding to the wiring of the x and y directions, since it is n _x and n _y origin tridiagonal form simultaneous equations, n _x, when n _y increases, n _x × n It is possible to solve much faster than the case of solving _y- ary simultaneous linear equations.

As described in the first embodiment, the process of obtaining the node voltages U and V for each block is repeated to obtain the finally converged node voltages U and V. Figure 5
Shows a processing flowchart for obtaining the node voltages U and V. In step S51, a selection variable j for selecting the j-th block connected to the voltage source E (j) is initialized to 1.

The initial values of the node voltages U and V are, for example, as described above, the terminal voltages E (j) :( j = 1,
n _y ), F (i): (i = 1, n _x ). In step S52, each node voltage of the block connected to E (j) is determined by fixing each node voltage of the other blocks and analytically solving the corresponding equation of the m-th block.

Needless to say, various direct methods and iterative methods can be applied to this solution. In step S53, it is checked whether the selected variable j is n _y , and n _y
If not, the process proceeds to step S4, j is incremented by 1, and the process returns to step S52. On the contrary, if n _y , the process proceeds to step S55.

In step S55, a selection variable i for selecting the i-th block connected to the voltage source F (i) is initialized to 1. In step S56, each node voltage of the block connected to F (i) is determined by fixing each node voltage of the other block and analytically solving the above equation of the corresponding i-th block.

Needless to say, various direct methods and iterative methods can be applied to this solution. In step S57, it is checked whether the selection variable i is n _x , and n _x
If not, the process proceeds to step S58, i is incremented by 1, and the process returns to step S56. On the contrary, if n _x , the process proceeds to step S59.

In step S59, it is checked whether the calculated node voltage values have converged. The determination of convergence is made, for example, by checking whether the time differential values of all the node voltage values are within a predetermined error value. Here, if it is determined that it has not converged, the process returns to step S51, and the same processing is repeated until it converges.
If it converges, it will progress to step S60 and each converged node voltage value will be displayed on the node potential display 107 via the output module 106.

As described above, the analyzer for the linear network including the electron source of this embodiment can obtain the node potential with high accuracy and at high speed. Also, according to this method,
It has been confirmed by experiments that the solution converges well. According to the analyzing apparatus of the present embodiment described above, n _x = 300,
Approximately 2 for the normal solution for n _Y = 100
I was able to obtain a solution that was 00 times faster.

The present invention may be applied to a system composed of a plurality of devices or an apparatus composed of a single device. Further, it goes without saying that the present invention can be applied to the case where it is achieved by supplying a program to a system or an apparatus. As described above, according to the analyzing apparatus of the present embodiment, the node potential of the circuit including the element and the wiring can be obtained at high speed with a physically clear and simple processing step.

[0047]

As described above, according to the present invention, the node potential of a circuit including electrical elements and wiring can be obtained at high speed with a physically clear and simple procedure.

[Brief description of drawings]

FIG. 1 is a diagram showing an outline of a node voltage estimation device according to a first embodiment of the present invention.

FIG. 2 is an abstracted diagram of a node voltage estimation target circuit according to the first embodiment of the present invention.

FIG. 3 is a flowchart showing a nodal voltage estimation processing procedure according to the first embodiment of the present invention.

FIG. 4 is an abstracted view of a node voltage estimation target circuit according to a second embodiment of the present invention.

FIG. 5 is a flowchart showing a nodal voltage estimation processing procedure according to the second embodiment of the present invention.

FIG. 6 is a diagram showing an example of a network including surface conduction electron-emitting devices.

[Explanation of symbols]

101 terminal voltage measuring instrument 102 input module 103 RAM 104 ROM 105 Central processing unit 106 Output module 107 node potential indicator 108 analog interface 109 digital interface 110 circuit under test 111 circuit drive

Continuation of the front page (56) References JP-A-3-204958 (JP, A) Tsudaka, Resistence between row and column terminals in a uniform resistor matrix, IEEE Proceedings, United Kingdom, August 1985, vol. 132, Part G, no. 4, p165-166 Atsushi Kajino et al., Speed performance of analog neuro circuit, IEICE research report, Japan, Institute of Electronics, Information and Communication Engineers, April 22, 1994, Vol. 94, Vol. No. 15, p25-30 (58) Fields investigated (Int.Cl. ⁷ , DB name) G06F 17/50 662

Claims (12)

(57) [Claims] 1. One terminal of a resistive element arranged in a matrix is connected to a row wiring, and the other terminal of the resistive element is connected to a column wiring, and between the row wiring and the column wiring. In a configuration for applying a predetermined voltage, a nodal voltage estimation method for estimating a nodal voltage at one terminal of the resistive element and a nodal voltage at the other terminal of the resistive element, the row-direction wiring and the Let each terminal of the resistive element connected to each wiring of the row-direction wiring be one group,
An initial value setting step of setting a predetermined initial value to each terminal voltage of each group when each terminal of the resistive element connected to each wiring of the column direction wiring and each of the column direction wiring is set as one group And based on the initial value of the node voltage of each terminal of the groups other than the n-th group set in the initial value setting step, A first updating step of calculating and updating the node voltage of each terminal of the n-th group; a simultaneous nodal analysis equation concerning the node voltage of each terminal of the n-th group of each group; and the first updating step. The second updating step of calculating and updating the node voltage of each terminal of the n-th group based on the node voltage of each terminal of the groups other than the n-th group updated in step 1, A nodal voltage estimation method comprising: a judgment step of judging that the nodal voltage of each terminal updated in the second updating step has converged based on a comparison with the nodal voltage before updating. 2. In the first updating step and the second updating step, n is a range from 1 to the total number T of the row-direction wirings and the column-direction wirings, and the node voltage of each terminal is updated in order. The nodal voltage estimation method according to claim 1, wherein the nodal voltage estimation method is repeated. 3. The node according to claim 1, wherein the calculation of the node voltage of each terminal of the n-th group in the first updating step and the second updating step is performed analytically. Voltage estimation method. 4. The nodal analysis simultaneous equations are provided with a resistance value between terminals of the nearest resistive element connected to the row-direction wiring and the column-direction wiring as a constant. Nodal voltage estimation method described in. 5. The nodal voltage estimation method according to claim 1, wherein the resistive element is a surface conduction electron-emitting device. 6. The nodal voltage estimation method according to claim 1, wherein the resistance of the resistive element is extremely larger than the resistance of each of the row-direction wiring and the column-direction wiring. 7. One of the terminals of the resistive element arranged in a matrix is connected to a row wiring, and the other terminal of the resistive element is connected to a column direction wiring, and between the row direction wiring and the column direction wiring. In a configuration for applying a predetermined voltage, a nodal voltage estimation device for estimating nodal voltage at one terminal of the resistive element and nodal voltage at the other terminal of the resistive element, wherein the row-direction wiring and the Let each terminal of the resistive element connected to each wiring of the row-direction wiring be one group,
An initial value setting means for setting a predetermined initial value to each terminal voltage of each group when each terminal of the resistive element connected to each of the column wiring and each of the column wiring is set as one group And based on the initial value of the nodal voltage of each terminal of the groups other than the nth group set by the initial value setting means, First updating means for calculating and updating the node voltage of each terminal of the n-th group, simultaneous node analysis simultaneous equations regarding the node voltage of each terminal of the n-th group in each group, and the first updating means Second updating means for calculating and updating the node voltage of each terminal of the n-th group based on the node voltage of each terminal of the groups other than the n-th group updated in 1. A nodal voltage estimation device comprising: a judging unit that judges that the node voltage of each terminal updated by the second updating unit has converged based on a comparison with the node voltage before updating. 8. The first updating means and the second updating means sequentially update the node voltage of each terminal in the range of n from 1 to the total number T of the row-direction wirings and the column-direction wirings. The node voltage estimation device according to claim 7 , wherein the node voltage estimation device is repeatedly executed. 9. The node according to claim 7 , wherein the calculation of the node voltage of each terminal of the n-th group in the first updating unit and the second updating unit is performed analytically. Voltage estimation device. Wherein said nodal analysis simultaneous equations claims, characterized in that it comprises the resistance between terminals of the resistive element nearest connected to the row-directional wiring and the column direction wirings as constant 7 Nodal voltage estimation device described in. 11. The nodal voltage estimating apparatus according to claim 7 , wherein the resistive element is a surface conduction electron-emitting device. 12. The node voltage estimating apparatus according to claim 7 , wherein the resistance of the resistive element is extremely larger than the resistance of each of the row-direction wiring and the column-direction wiring.