JP3378647B2 - Logic comparison circuit of semiconductor test equipment - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logical comparison circuit for performing a logical comparison between an output from a device under test and an expected value in a semiconductor test apparatus. 2. Description of the Related Art FIG. 5 shows a block diagram and a timing chart showing a conventional configuration. Device under test DU
When comparing the voltage level specified as the output data Dout · 17 from T · 1, that is, the comparison voltage VO · 6 with the expected value 9, and classifying the delay time of the output data Dout · 17,
In the prior art, it was described as follows.
Data obtained by level comparison of Dout 17 from DUT 1 with the comparison voltage VO 6 is output from the timing generator 4, and the timing comparator 3 compares the timing with the comparison timing STROBE 5 synchronized with the operation clock 10. . Here, the comparison timing STROBE · 5 synchronized with the operation clock 10 is to generate the one-pulse comparison timing STROBE · 5 in response to the generation of the one-pulse operation clock 10. However, the time phase between the operation clock 10 and the comparison timing STROBE · 5 can be set in the timing generator 4 before the measurement is performed. Next, data FH ·
The exclusive OR circuit 11 of 15 and the expected value 9 performs an exclusive OR operation and performs a logical comparison to classify FH · 15 and the expected value 9 as coincidence, ie, PASS, and non-coincidence, ie, Fail. Next, a comparison result holding circuit capable of holding a mismatch result when data F / P · 16 which has been logically compared every 10 operation clocks is detected as a mismatch, that is, Fail, even once in the logical comparison. Enter in 12. After the measurement of the device under test 1 is completed, the comparison result is read, and the output of the DUT-1 is compared with the comparison voltage VO-6.
In the comparison with the expected value 9 at the designated comparison timing point, a match or a mismatch was detected. Using the prior art method, the comparison voltage VO · 6
When a change point of the output data Dout 17 of the DUT 1 is detected or a delay time is classified based on the expected value 9, the comparison timing STROBE
Numeral 5 outputs a signal obtained by sequentially changing the time phase difference. Therefore, the measurement of the same device under test 1 is repeatedly performed, and the time required for the measurement of the device 1 is disadvantageously increased. When the device to be measured is, for example, a memory, how long it takes from the input of an address signal to the output of output data, that is, In order to measure whether it moves at the timing and align the shipping quality to users,
Rank classification must be performed. For this purpose, the comparison timing STROBE synchronized with one pulse of the operation clock is used.
Is compared with a specified voltage level of the output data Dout of the DUT, that is, an expected value with respect to the comparison voltage VO, and a change point of the DUT is detected to be classified. According to the method of the prior art, for example, if the data is classified into five ranks, it is not possible to determine which rank should be determined unless measurement is performed six times. Therefore, six pulses of the operation clock are required to measure the change point once. Therefore, as in recent years, the capacity of a memory has been remarkably increased, such as 4 Mbits or 16 Mbits.
At present, it takes 5 to 10 minutes / piece for one search when the M bits are to be measured, and 30 to 60 for six searches.
It takes a minute / piece of measurement time. In addition, it is expected that the capacity will be increased by a factor of four for each generation, and the measurement time will be further increased. Accordingly, an object of the present invention is to reduce the number of search execution circuits for the same ratio measurement target device and to realize a logic comparison circuit capable of significantly reducing the measurement time of the device. In order to achieve the above object, in a logic comparison circuit of a semiconductor test apparatus according to the present invention, a comparison timing STROBE · 5 for searching for one pulse of an operation clock is provided. And a plurality of timing generators 40 are provided for this purpose.
Accordingly, a timing comparator 3 for comparing the timings with the comparison timing STROBE · 5 of a plurality of pulses, a strobe number counting circuit for counting a plurality of comparison timings STROBE · 5 of n pulses, and an n-cycle comparison timing STROBE · 5 Comparison timing STROBE classified into
Separation circuit 8 is provided. The comparison result separation circuit 14 separates the comparison data separated into n systems into the timing comparison results of the n systems, and detects whether the timing comparison result of the n systems and the expected value 9 match or not. Logical comparison circuit 11 and comparison result holding circuit for holding mismatch information of the logical comparison result
12 is provided as a logical comparison circuit. In the example of detecting the change point of the output data of the DUT,
Comparison timing Within the search range by STROBE,
In the prior art, for example, six measurements were performed to search for six points. However, in the method according to the present invention, the comparison timing STOROBE is set to three pulses for one pulse of the operation clock. When searching for six points, only one-third measurement is required. In the example of rank classification of the delay time of the output data of the DUT, a plurality of, for example, three simultaneously measured DUs are measured.
For the group T, in the related art, the comparison timing STROBE is set to three pulses, and three times, for example, A,
B and C were classified. In the method of the present invention, the comparison timing STROBE is set to three pulses for one pulse of the operation clock.
Obtaining nine pieces of information for the DUT group also requires only one third of the measurement. FIG. 1 is a block diagram showing a configuration concept of the present invention. FIG. 2 shows a timing chart in the logic comparison circuit of the present invention. First, output data Dout · 17 from DUT · 1 and data obtained by comparing the comparison voltage VO · 6 with the level comparator 2 and a plurality of timing generators 40
The timing comparison is performed with the comparison timing STROBE · 5 in which a plurality of n pulses are generated for one pulse of the operation clock 10, and the timing comparison data of FH1 to FHn is output as the comparison result FH · 15. Next, the comparison timing STROBE · 5 output from the plurality of timing generators 40 is input to the strobe number counting circuit 7, and the number of strobes is counted as an n-ary counter. Here, n, which is an n-ary counter, indicates the number of comparison timings STROBE · 5 set for one pulse of the operation clock. Next, the output from the strobe number counting circuit 7
By inputting the CO and the comparison timing STROBE · 5 generated a plurality of times to the comparison timing separation circuit 8, the comparison timing STROBE · 5 is converted into S 1, S 2, S 3 according to the n output values of the strobe number counting circuit 7. ... Separate and output to Sn. That is, as shown in the timing chart of FIG. 2, when the output CO of the strobe number counting circuit 7 is CO = # 0, the comparison timing STROBE · 5 is input to the S1 line of the comparison timing separation circuit 8, and CO = # If it is 1, go to the S2 line, and if CO = # 2, go to the S3 line ... CO =
At the time of # n-1, control is performed so as to output to the Sn line. Next, the data FH1 to FHn, which have been subjected to the timing comparison by the timing comparator 3, are respectively output to the flip flops F1 to Fn of the comparison result separation circuit 14 by S1 to Sn output from the comparison timing separation circuit 8. Enter separately. At this point, each comparison timing STROBE
The timing comparison data in 5 is stored separately in F1 to Fn. Data stored in the F1 to Fn,
The exclusive OR of the expected value 9 is calculated and each comparison timing STRO
A logical comparison circuit 11 classifies FH1 to FHn in BE · 5 that do not match the expected value 9, that is, Fail, and matches, that is, PASS, into F / P · 16. In the present embodiment, as shown in FIG. 1, the logical comparison with the expected value 9 is performed based on the output from the comparison result separation circuit 14. The same result can be obtained by performing a logical comparison with Next, the mismatch information as a result of the logical comparison is
Comparison result holding circuit 12 that holds until the next measurement starts
, And hold it as mismatch information. Comparison result at each comparison timing STROBE ・ 5 after completion of predetermined measurement
By reading 13, it is possible to extract the result of the match or mismatch between the comparison voltage VO · 6 and the expected value 9 at the multiple comparison timing STROBE · 5 points for the output of the DUT · 1. According to the present invention, in the detection of the change point of the output data Dout · 17 of the DUT · 1 using the comparison voltage VO · 6 and the expected value 9, the range searched at the comparison timing STROBE · 5 is 1 / A plurality of comparison timings STROBE · 5 can be set at points divided into n, and the number of measurement executions required in the prior art can be reduced to 1 / n. In this embodiment of the present invention, the output data
Although the case of detecting the change point of Dout · 17 has been described in detail, in the rank classification of the delay time of the output data Dout · 17, a plurality of comparison timings STROBE · 5 are set within the range of the delay time to be classified. By setting points,
Similarly, it is possible to classify delay times by reducing the number of measurement executions required in the prior art to 1 / n. Further, in the present embodiment shown in FIG.
Although the case of only one DUT is shown, the case of simultaneously measuring a plurality of DUTs 1 can be realized by providing a plurality of circuits having the configuration according to the block diagram shown in FIG. 1 in parallel. Since the present invention is configured as described above, it has the following effects. According to the present invention, the DUT is set based on the comparison voltage VO and the expected value.
In the detection of the change point of the output data and the rank classification of the delay time, the range searched by the comparison timing STROBE is
Multiple comparison timing STROBE at 1 / n division
Can be set, simultaneous measurement is also possible,
The number of measurements was reduced to 1 / n, and the measurement time was significantly reduced. In addition, the circuit configuration of the present invention may include a strobe number counting circuit, a comparison timing separation circuit, and a comparison result separation circuit in addition to the measurement circuit according to the related art.
If it is desired to measure a plurality of devices at the same time, it is possible to provide a required number of devices in parallel, so that it is very easy to cope with an increase in the capacity of the DUT to be measured.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a configuration concept of an embodiment of the present invention. FIG. 2 shows a timing chart in the logical comparison circuit of the present invention. FIG. 3 shows a comparative example of detection of a change point of output data according to the present invention and the prior art. FIG. 4 shows a comparative example of ranking delay times according to the present invention and the prior art. FIG. 5 shows a block diagram and a timing chart showing a configuration concept of a conventional technique. [Description of Signs] 1 DUT 2 Level comparator 3 Timing comparator 4 Timing generator 5 Comparison timing STROBE 6 Comparison voltage VO 7 Strobe number counting circuit 8 Comparison timing separation circuit 9 Expected value 10 Operation clock 11 Logic comparison circuit 12 Comparison result holding circuit 13 Comparison result 14 Comparison result separation circuit 15 Timing comparison result FH 16 F / P 17 Dout 40 Multiple timing generator

Claims (1)

(57) [Claims] [Claim 1] For one pulse of the operation clock (10),
A plurality of timing generators (40) for generating a plurality of comparison timings STROBE (5) are provided, the output data Dout (17) from the DUT (1) and the comparison voltage VO
The timing comparator (3) compares the data obtained by level comparison with (6) by the level comparator (2) at the timing at each comparison timing STROBE (5) set point, and outputs the timing comparison data FH (15). And a strobe number counting circuit (7) that counts a plurality of comparison timings STROBE (5) output from the plurality of timing generators (40) as an n-ary counter. A comparison timing separation circuit (8) for separating and outputting a plurality of generated comparison timings STROBE (5) in accordance with the output CO of the data FH (15) obtained by the timing comparison by the timing comparator (3) and the comparison timing A comparison result separation circuit (14) is provided for inputting the outputs separated by the separation circuit (8). A logical comparison circuit (11) for taking an exclusive OR of the data output from each comparison result separation circuit (14) and the expected value (9) and classifying the data as a match or mismatch; A semiconductor test apparatus, comprising: a comparison result holding circuit (12) for inputting mismatch information from (1) and holding the information until the next measurement execution result information is input; Logical comparison circuit.