JP3378799B2 - Double decoder and satellite broadcast receiving apparatus including the same - Google Patents

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to a detection signal (detected video and audio signal) from a satellite broadcast receiving tuner.
The present invention relates to a double decoder for supplying a scramble decoder with a bitstream and a bitstream thereof and a satellite broadcast receiving device including the double decoder.

[0002]

2. Description of the Related Art In some paid satellite broadcasting, a signal is scrambled and sent, and the receiving side descrambles the signal for viewing. An electronic device called a set top box may be used for the scrambling. If this set-top box is connected to a television receiver or VTR having a satellite broadcast receiving function, it is possible to receive or record pay satellite broadcasts. Even if you have only one set-top box, you can receive satellite broadcasts on both television sets and VTRs by switching with a switch.

Such a switch function is called a double decoder. Double-decoders are generally always on, as the detection signal and the bitstream can arrive at any time.

Then, when a command for switching the switch to either the television receiver or the VTR comes from the microcomputer or the like, the switch is switched to the necessary side.

[0005]

However, in such a device, there is a problem that the power consumption during standby is increased because the power is always on. The problem of power consumption during standby has become a big social problem in recent years, and reduction of it is desired. In particular, since the double decoder and the scramble decoder are connected by a cable with a 75 ohm termination, the bias current of the output transistor at the final stage of the double decoder is wasted.

[0006]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and a detection signal and a bit stream from a first receiver are applied and a second signal is applied.
A double decoder to which the detection signal and the bit stream from the receiver are applied, and which selects the detection signal and the bit stream from any of the receivers and applies the selected scramble decoder to the scramble decoder. An amplifier that amplifies the bit stream, a full-wave rectifier circuit that full-wave rectifies the output signal of the amplifier, a capacitor that is charged by the output signal of the full-wave rectifier circuit, an output signal of the capacitor, and a reference voltage. A bitstream detection circuit including a level comparator for comparing levels is provided to detect the presence / absence of the bitstream, and a power supply state to the double decoder is switched according to an output signal of the bitstream detection circuit. Characterize.

Further, according to the present invention, the detection signal and the bit stream from the first receiver are applied, and the detection signal and the bit stream from the second receiver are applied.
A double decoder for selecting a detection signal from any one of the receivers and a bit stream and applying it to a scramble decoder, wherein an amplifier for amplifying the bit stream from the first receiver and an output signal of the amplifier are provided. A full-wave rectification circuit for full-wave rectification, a capacitor charged by an output signal of the full-wave rectification circuit, and a level comparator for comparing the level of the output signal of the capacitor and a reference voltage are included to determine the presence or absence of the bit stream. A bitstream detection circuit for detecting is provided, and a bias is not applied to the output transistor at the final stage of the double decoder according to the output signal of the bitstream detection circuit.

[0008]

BEST MODE FOR CARRYING OUT THE INVENTION A double decoder of the present invention and a satellite broadcast receiving apparatus including the same will be described with reference to FIG. 1
Is applied with the detection signal and the bit stream from the satellite broadcast tuner 2 (first receiver) of the VTR, and the satellite broadcast tuner 3 (second receiver) of the TV receiver.
From the satellite receiver tuner 3 of the TV receiver is detected by a double decoder 4 which receives the detection signal and the bit stream from any of the receivers and selects the detection signal and the bit stream from any of the receivers. The bit stream detection circuit 5 is a scramble decoder, and 6 is a terminal to which a switch control signal for switching from the microcomputer to the satellite broadcast tuner 2 or the satellite broadcast tuner 3 is applied.

The double decoder 1 receives the detection signal and the bit stream from the satellite broadcast tuner 2 of the VTR and the detection signal and the bit stream from the satellite broadcast tuner 3 of the TV receiver, and outputs from the terminal 6. One of the detection signals and the bit stream is selected according to the switch control signal of. The selection is performed, for example, by the switch 7 inside the double decoder 1. The selected signal is applied to the output transistor 8 at the final stage of the double decoder 1 and is led from its emitter to the terminal 9. The resistors 10 and 11 indicate the impedance of the code connecting the double decoder 1 and the scramble decoder 5.
Since the impedances of the resistors 10 and 11 are small as described above, it becomes necessary to flow a large bias current even when the output transistor 8 is in the standby state.

In this way, the selected detection signal and bit stream are descrambled by the scramble decoder 5. The scrambled detection signal and the video signal and audio signal demodulated from the bit stream are returned to the satellite broadcast tuner 2 of the VTR or the satellite broadcast tuner 3 of the TV receiver, which is the transmission source.

When the satellite broadcast tuner 3 of the TV receiver is receiving satellite broadcast, the bit stream is continuously arriving at the terminal 12. Therefore, if it is detected that the bit stream arrives at the terminal 12,
The switch 7 may be switched so that the scramble decoder 5 selects the signal from the satellite broadcast tuner 3 of the TV receiver. A detection signal is applied to the terminal 13. The bitstream is detected by the bitstream detection circuit 4. Since the high and low signals continuously arrive in the bit stream, the bit stream detection circuit 4 can be configured by an integrating circuit or the like. When the bitstream does not arrive due to the detection output signal of the bitstream detection circuit 4, the power supply of the double decoder 1 is cut off. For example, the current of the current source 14 of the output transistor 8 at the final stage is cut off. As a result, the power consumption of the double decoder 1 is significantly reduced. In this case, switch 7
Is always set to the selected state of the TV satellite broadcast tuner 3, and is turned on when a bit stream arrives from the TV receiver satellite broadcast tuner 3.

FIG. 1 shows a case where the double decoder 1 and the bit stream detection circuit 4 are arranged in a set of home VTRs. Therefore, when the main power supply of the set of household VTRs is off, the double decoder 1 turns on the bitstream detection circuit 4 in the off state, and the double decoder 1 is turned on according to the detection output signal of the bitstream detection circuit. Add power.

In the description of FIG. 1, the double decoder 1 and the bit stream detection circuit 4 are shown as being arranged in a set of home VTRs, but the double decoder 1 and the bit decoder 1 are included in the set of the TV receiver. The same operation is possible when the bit stream detection circuit 4 is provided and the cord is connected to a home VTR.

FIG. 2 shows a specific circuit diagram of the bitstream detection circuit 4 of FIG.

2, reference numeral 20 is an amplifier for amplifying the bit stream, 21 is a full-wave rectifying circuit for full-wave rectifying the output signal of the amplifier 20, and 22 is charged by the output signal of the full-wave rectifying circuit 21. Condenser, 23 is condenser 22
Is a level comparator that compares the level of the output signal of the reference voltage with the reference voltage of the reference power supply 24.

A bit stream is applied to the input terminal 25 of FIG. The bit stream is amplified by the amplifier 20. The gain of the amplifier 20 is sufficiently high, and is set to a gain for performing a limiter operation on the input signal. The limiter-amplified signal is full-wave rectified by the full-wave rectifier circuit 21. The full-wave rectified signal is charged into the capacitor 22 from the point A via the buffer transistor 26.

If the bitstream arrives in succession,
The charge from the buffer transistor 26 to the capacitor 22 is continuously performed. Then, the charging voltage of the capacitor 22 rises and exceeds the reference voltage of the reference power supply 24. Then, an output terminal 27 of the level comparator 23 generates a "H" level determination output signal.

On the contrary, if the bit stream does not arrive,
Since the capacitor 22 is discharged by the action of the constant current source 28, the charging voltage of the capacitor 22 decreases and becomes lower than the reference voltage of the reference power supply 24. Then, the "L" level determination output signal is generated from the output terminal 27 of the level comparator 23.

Therefore, according to the circuit of FIG. 2, the presence / absence of a bit stream can be determined.

[0020]

According to the present invention, a bitstream detection circuit for detecting the presence / absence of a bitstream from the first receiver is provided, and the power supply state to the double decoder is supplied in accordance with the output signal of the bitstream detection circuit. Since it is switched, the power consumption during standby can be reduced. In particular, since the double decoder and the scramble decoder are connected by a cable with a 75 ohm termination, it is possible to reduce the bias current of the output transistor at the final stage of the double decoder, so that a large reduction can be achieved.

Furthermore, according to the present invention, an amplifier for amplifying the bit stream, a full-wave rectifier circuit for full-wave rectifying the output signal of the amplifier, and a capacitor charged by the output signal of the full-wave rectifier circuit, Since the presence / absence of a bit stream is detected by including a level comparator that compares the output signal of the capacitor with a reference voltage, the presence / absence of a bit stream can be reliably detected.

[Brief description of drawings]

FIG. 1 is a double decoder of the present invention.

FIG. 2 shows a specific circuit diagram of the bitstream detection circuit 4 of FIG.

[Explanation of symbols]

1 double decoder 2 VTR satellite tuner 3 Satellite TV tuner of TV receiver 4 bitstream detection circuit 5 scramble decoder 7 switch 8 output transistors

─────────────────────────────────────────────────── ─── Continuation of front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H04N 5/38-5/63 H04B 1/06 H04B 1/16

Claims (4)

(57) [Claims] 1. A detection signal and a bit stream from a first receiver are applied, and a detection signal and a bit stream from a second receiver are applied, and a detection signal from either receiver is applied. A double decoder for selecting a bit stream and applying it to a scramble decoder, the amplifier amplifying the bit stream from the first receiver, and a full-wave rectifying circuit for full-wave rectifying an output signal of the amplifier, A bitstream detection circuit for detecting the presence / absence of the bitstream is provided, which includes a capacitor charged by the output signal of the full-wave rectification circuit, and a level comparator for comparing the level of the output signal of the capacitor with a reference voltage. The power supply state to the double decoder is switched according to the output signal of the bit stream detection circuit. Bull decoder. 2. A detection signal and a bit stream from a first receiver are applied, and a detection signal and a bit stream from a second receiver are applied, and a detection signal from either receiver is applied. A double decoder for selecting a bit stream and applying it to a scramble decoder, the amplifier amplifying the bit stream from the first receiver, and a full-wave rectifying circuit for full-wave rectifying an output signal of the amplifier, A bitstream detection circuit for detecting the presence / absence of the bitstream is provided, which includes a capacitor charged by the output signal of the full-wave rectification circuit, and a level comparator for comparing the level of the output signal of the capacitor with a reference voltage. Bitst
The bitstream is not detected by the ream detection circuit.
The double decoder is characterized in that the bias is not applied to the output transistor at the final stage of the double decoder when and are detected . 3. A satellite broadcast receiving apparatus comprising a television receiver provided with the double decoder according to claim 1. 4. A V comprising the double decoder according to claim 1.
A satellite broadcasting receiver consisting of TR.