JP3381266B2 - Clock recovery device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock reproducing apparatus for reproducing a master clock from digital data reproduced by a video tape recorder for recording and reproducing digital data on a recording medium. 2. Description of the Related Art In recent years, clock reproduction apparatuses have been increasing the frequency of clock reproduction in accordance with high-density recording on a recording medium.
In addition, clock reproduction can be performed in a wide range to support special reproduction during reproduction. [0003] A conventional clock recovery device will be described below. FIG. 6 is a block diagram of this conventional clock recovery device. The reproducing heads 101A and 101B reproduce data recorded on a recording medium. The tape 103 records data. The rotary cylinder 102 has a pair of reproducing heads 101A and 101B mounted thereon, and rotates at high speed with a tape 103 wound thereon. The equalizer 109 compensates for the intersymbol interference of the reproduced signal generated in the recording / reproducing system. The quantizer 110 quantizes the reproduced signal into binary. The delay unit 126 delays the input digital data by a predetermined time and outputs the digital data. The phase comparison signal generator 120 outputs an exclusive OR of two input digital data. Clock recovery PLL unit 1
Reference numeral 21 comprises a charge pump type phase comparator 122, a loop filter 123, and a voltage controlled oscillator 124, and reproduces a master clock from reproduced digital data.
The identification timing adjustment unit 127 includes a resistor 128 and a capacitor 129, and adjusts the timing of the reproduced clock at the identification point. The discriminator 125 identifies the reproduced digital data at the rise of the reproduction clock. [0004] The operation of the above-described conventional clock recovery device will be described with reference to FIGS. 7, 8, 9 and 10. FIG.
FIG. 8 is a timing chart of the clock reproducing apparatus when reproducing a portion in which digital data having a half frequency of the recording master clock is recorded.
FIG. 9 is a timing chart of the clock reproducing device when the relative speed between the tapes A and 101B and the tape 103 is increased by 15% from that in FIG.
FIG. 10 is a timing chart of the clock reproducing apparatus when the relative speed between the tape 1B and the tape 103 is reduced by 15% from that in FIG. 7, and FIG. 10 is a diagram showing phase comparison characteristics at each relative speed. A tape 10 on which digital data is recorded
3 is wound around a rotating cylinder 102 rotating at high speed by 180 °, and a reproduced signal reproduced by switching a pair of reproducing heads 101A and 101B mounted on the rotating cylinder 102 every 180 ° is recorded and reproduced by an equalizer 109. The inter-symbol interference of the reproduced signal caused by the influence of The quantizer 110 quantizes the equalized reproduced signal into binary reproduced digital data, and supplies it to the delay unit 126 and the phase comparison signal generator 120. The delay unit 126 supplies the reproduced digital data h delayed by Tw ′ / 2 to the reproduced digital data g to the phase comparison signal generator 120 and the discriminator 125 as shown in FIG. The phase comparison signal generator 120 outputs a phase comparison signal i, which is the exclusive OR of the reproduced digital data g before delay and the reproduced digital data h after delay, to a clock reproduction PLL unit 121.
To the charge pump type phase comparator 122. Here, the phase comparison width Tg of the phase comparison signal i is set such that (the half cycle Tw '/ 2 of the reproduction clock) when the relative speed between the reproduction heads 101A and 101B and the tape 103 reaches the maximum as shown in FIG. (Phase comparison width Tg) is set so that when the phase comparison width Tg becomes (half cycle of the reproduction clock) <(phase comparison width), the rising and falling edges of the reproduction clock are within the phase comparison width Tg. This is because the clock reproduction PLL unit 121 cannot accurately lock the phase of the reproduced clock with respect to the reproduced digital data. Also, the reason why the phase comparison signal is generated only at the rising edge or the falling edge of the reproduced digital data is that when the reproduced clock is accurately locked at the phase and frequency by the clock reproduction PLL unit 121 with respect to the random digital data, When the phase is compared with the reproduction clock in a portion having no phase information, incorrect control is performed by the clock reproduction PLL unit 12.
This is because there is a risk that the device itself will do so. The clock recovery PLL unit 121 compares the phase of the recovered clock of the voltage controlled oscillator 124, which oscillates at a frequency close to the master clock, with the phase comparison signal by the charge pump type phase comparator 122. When the phase comparison signal is High and the recovered clock is Low Is operated when the phase comparison signal is high and the reproduction clock is high, and is charged under the other conditions. The phase comparison output is supplied to the loop filter 123 and the voltage is applied to the error signal after the band limitation. The control oscillator 124 is feedback-controlled.
Finally, the clock recovery PLL section 121 reproduces a reproduction clock j which rises at Tg / 2 of the phase comparison signal i shown in FIG. 7 and is locked in phase and frequency, and outputs a reproduction clock having a 180 ° phase difference from the reproduction clock j. This is supplied to the identification timing adjustment unit 127. The discrimination timing adjustment unit 127 shifts the timing of the reproduced digital data h of FIG. 7 by Td by the resistor 128 and the capacitor 129 so that the timing of the reproduced clock is located at the position of the reproduced clock k. (Not shown). The discriminator 125 discriminates the reproduced digital data h of FIG. 7 at each rising edge of the reproduced clock k, and supplies the discriminated digital data to a decoding circuit (not shown) at the subsequent stage. However, in the above-described conventional configuration, the phase comparison width of the phase comparison signal generated by the phase comparison signal generator 120 is set when the relative speed is increased to the maximum by the special reproduction. Clock recovery P shown in FIG.
In order to fix the reproduction clock of the LL unit 121 to Tw '/ 2, if the phase comparison characteristic of the charge pump type phase comparator 122 of the clock reproduction PLL unit 121 becomes lower than that of FIG. As the level decreases, a phase difference period in which the phase comparison sensitivity becomes zero occurs, and the phase comparison output decreases. The response from the free-running state of the reproduction clock of the clock reproduction PLL unit 121 to the reproduction digital data locked in phase and frequency. Time, for example, when the reproduced digital data is interrupted during the head switching period of the reproducing head 101A and the reproducing head 101B, the responsiveness when the reproduced digital data is reproduced again, and the edited portion where the phase of the reproduced digital data has no correlation is reproduced. Greatly affects the response of the Erroneous identification of total data.
Furthermore, in order for the discriminator 125 to correctly identify the reproduced digital data, it is necessary to prevent the reproduced digital data for identification from changing within a fixed time before and after the identification timing. In this way, the discrimination timing adjustment section 127 sets the T so that the discrimination timing of the reproduction clock comes at Ts = Th of the reproduction digital data h.
By adjusting only d, the optimum identification timing is made. However, since the identification timing adjustment unit 127 has frequency characteristics, when the relative speed changes, for example, when the relative speed is reduced by 15% from the relative speed in the normal reproduction state in FIG. 9 becomes smaller than Td in FIG. 7 and the identification timing position becomes Ts "<Th" of the reproduced digital data h as shown in FIG. 9 and deviates from the optimum identification timing position Ts "= Th". Conversely, when the relative speed increases by 15% relative to the relative speed in the normal reproduction state, the delay amount in the discrimination timing adjustment unit 127 becomes larger than Td in FIG. 7 and the discrimination timing position becomes the reproduction digital data as shown in FIG. h Ts'> T
h ', which is a deviation from the optimal identification timing position Ts' = Th'. Therefore, there is a problem that the reproduced digital data is erroneously identified due to the identification timing deviation especially in the direction in which the relative speed increases. The present invention solves the above-mentioned conventional problems. Even if the relative speed between the head and the tape changes, the phase comparison sensitivity to the phase difference of the charge pump type phase comparator of the clock reproduction PLL unit becomes zero. Eliminates the phase error period that ensures stable phase comparison characteristics, improves the response time from the free-running state of the playback clock to the playback digital data and locks it in phase and frequency, and at the same time identifies the timing of the playback digital data. It is an object of the present invention to provide a clock reproducing apparatus which can always set the clock signal at an optimum position to reduce erroneous identification of reproduced digital data. In order to achieve the above object, a clock recovery apparatus according to the present invention is provided with a tap for delaying input digital data at regular time intervals and outputting digital data at a plurality of timings. A delay means and a digital signal having a timing which is advanced in advance with respect to the timing of the digital data for identification from among a plurality of digital data of the output of the delay means with tap by the control signal, and which is always optimally delayed in the delay direction. 1
Data selection means for selecting and outputting only one of them, phase comparison signal generation means for generating a phase comparison signal from the two digital data at different timings, and a relative speed between the recording medium and the reproduction means for detecting a change in the frequency of the digital data. A relative speed detecting means for applying control to the data selecting means, and a clock for detecting and controlling the phase difference between the phase comparison signal and the feedback so that the frequency and phase of the reproduced clock coincide with the frequency and phase of the digital data. It has a configuration including reproduction PLL means and identification means for identifying digital data by a reproduction clock. According to the present invention, the timing of the digital data for identification is selected from a plurality of digital data at a plurality of timings taken out of the respective delay means under the control of the relative speed detecting means in accordance with the change of the relative speed. The digital data at the timing which is always optimally delayed in the delay direction is selected by the data selection means and added to the phase comparison signal generation means, thereby generating a phase comparison signal for phase comparison of the clock recovery PLL means. Even when the relative speed changes, there is no phase error period during which the phase comparison sensitivity of the phase comparator of the clock recovery PLL becomes zero, so that a stable phase comparison characteristic is always ensured, and the digital data for identification is always optimally identified. Act to obtain. An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of a clock reproducing apparatus according to an embodiment of the present invention. In FIG. 1, the reproducing head 1
01A and 101B reproduce the data recorded on the tape 103 and supply it to the equalizer 109. The tape 103 records data. The rotary cylinder 102 is mounted with the pair of reproducing heads 101A and 101B, and rotates at high speed with the tape 103 wound thereon. The cylinder speed detector 104 detects the rotation pulse of the rotary cylinder 102 and supplies the rotation pulse to the cylinder speed detector 116 of the relative speed detection unit 115. The control head 105 detects a control signal recorded on the tape 103 and supplies the control signal to the tape speed detector 117 of the relative speed detection unit 115. The reel 106 winds the tape 103. The reel rotation pulse detectors 107 and 108 detect the rotation pulse of the reel and supply it to the tape running direction detector 118 of the relative speed detector 115. The equalizer 109 compensates for the inter-symbol interference of the reproduced signal generated in the recording / reproducing system and supplies the equalized reproduced signal to the quantizer 110. The quantizer 110 quantizes the reproduction signal into binary values and supplies the reproduction digital data to the tapped delay digital signal generation unit 111. The tapped delay digital signal generation section 111 cascade-connects delay units 1 to Z for delaying a signal for a very short fixed time and generates digital data of a plurality of timings.
3 and supplies the output of the delay unit Z to the tapped delay digital signal generator 112 and the discriminator 125. The tapped delay digital signal generator 112 has the same configuration as the tapped delay digital signal generator 111 and supplies digital data at a plurality of timings to the multiplexer 114. Multiplexers 113, 114
Are delay digital signal generators 111 and 112 with taps.
One digital data at a certain timing is selected and output from the plurality of digital data at the timing by the control signal from the relative speed detection unit 115 and supplied to the phase comparison signal generator 120. Relative speed detector 11
5 is a cylinder speed detector 116 and a tape speed detector 11
7, tape running direction detector 118, relative speed calculator 11
9, heads 101A and 101B and tape 10
The control signal is supplied to the multiplexers 113 and 114 for detecting the relative speed between the three. The phase comparison signal generator 120 takes the exclusive OR of two input digital data with different timings and outputs the result.
It is supplied to the L section 121. Clock recovery PLL section 121
Is composed of a charge pump type phase comparator 122, a loop filter 123, and a voltage controlled oscillator 124 and reproduces a master clock from reproduced digital data. The discriminator 125 discriminates digital data for discrimination at every rise of the reproduction clock. The operation of the clock reproducing apparatus according to the present embodiment having the above components will be described below. The tape 103 on which the digital data is recorded is wrapped 180 ° around the rotating cylinder 102 which rotates at a high speed.
02 and a pair of reproducing heads 101A and 101
The reproduced signal reproduced by switching B every 180 ° is supplied to the quantizer 110 by the equalizer 109 reducing the inter-symbol interference of the reproduced signal caused by the influence of the recording / reproducing system.
The quantizer 110 quantizes the equalized reproduced signal into binary reproduced digital data, and supplies it to a tapped delayed digital signal generator 111 to convert the reproduced digital data delayed by the total delay time ZT into digital data for identification. At the same time, the signal is supplied to the tapped delay digital signal generator 112 and further ZT-delayed. Therefore, the tapped delay
From the digital signal generator 111 to the multiplexer 113
All timings of digital data supplied to are for identification
Phase advance relative to digital data timing
It becomes a thing. Similarly, a tapped delayed digital signal
Dies supplied from the generator 112 to the multiplexer 114
All digital data timings are digital data for identification.
The phase is relatively delayed from the data timing.
You. Delayed digital signal generators 111 and 112 with tap
The multiplexers 113 and 114 determine the relative speed between the reproducing heads 101A and 101B and the tape 103 by the multiplexers 113 and 114. From the result of the detection operation performed by the detection unit 115,
At this time, the multiplexer 113 controls one cycle of the reproduced clock at the relative speed to select digital data having a timing one quarter cycle ahead of the timing of the digital data for identification, and the multiplexer 114 controls the digital data for identification. Control is performed so as to select digital data having a timing that is delayed by 1/4 cycle from the data timing. Referring to FIG. 2, FIG.
Reproduces a portion in which digital data having a half frequency of a recording master clock is recorded,
1 when the reproduced clock is locked in phase and frequency with respect to the reproduced digital data.
3, the digital data b having a timing advanced by Tw / 4 phase with respect to the timing of the identification digital data a.
And the multiplexer 114 selectively outputs digital data c having a timing delayed by Tw / 4 phase. The phase comparison signal generator 120 generates an exclusive OR of the digital data b and the digital data c to generate a phase comparison signal d, and supplies the phase comparison signal d to the charge pump type phase comparator 122 of the clock recovery PLL unit 121. When the phase of the reproduced clock e of the voltage controlled oscillator 124 oscillating at a frequency close to the master clock is compared with the phase of the phase comparison signal by the charge pump type phase comparator 122 in the clock reproduction PLL section 121, the phase comparison signal is High and the reproduced clock e is Lo.
In the case of w, discharge is performed, the phase comparison signal is High, and when the reproduced clock e is also High, the operation is charging. In other conditions, the phase error signal is held. The voltage-controlled oscillator 124 is feedback-controlled by the limited error signal, and finally the clock recovery PLL unit 1
Reference numeral 21 reproduces a reproduction clock e locked at the phase and frequency rising at Tg / 2 of the phase comparison signal d. The reproduced clock f having a phase 180 ° different from that of the reproduced clock e is supplied to the discriminator 125 to discriminate the identification digital data a at the timing of Ts = Th. Next, a case where the relative speed is increased by 15% as compared with the case of FIG. 2 will be described with reference to FIG. Control is performed so as to output digital data b having a timing advanced by Tw '/ 4 phase, and digital data c having a timing delayed by Tw' / 4 phase with respect to the timing of the identification digital data a is output to the multiplexer 114. Control to be performed. When a phase comparison signal d obtained by performing an exclusive OR operation of the digital data b and the digital data c by the phase comparison signal generator 120 is applied to the charge pump type phase comparator 122 of the clock regeneration PLL unit 121, the clock regeneration PLL unit 1
The reproduced clock 21 reproduces the reproduced clock e locked at the phase and frequency rising at Tg '/ 2 of the phase comparison signal d, and supplies the discriminator 125 with the reproduced clock f 180 ° out of phase with the reproduced clock e. The digital data a for identification is identified at the timing of Ts '= Th'. Next, a case where the relative speed is reduced by 15% from the case of FIG. 2 will be described with reference to FIG. 4. Based on the calculation result of the relative speed detection unit 115, the multiplexer 113 determines the timing of the digital data a for identification. Tw "
Control is performed so as to output digital data b at a timing advanced by / 4 phase.
Control is performed so as to output digital data c having a delayed phase. When a phase comparison signal d obtained by taking an exclusive OR of the digital data b and the digital data c by the phase comparison signal generator 120 is applied to the charge pump type phase comparator 122 of the clock recovery PLL unit 121, the clock recovery PLL unit 121 The reproduced clock is the phase comparison signal d
The reproduction clock e that rises at Tg ″ / 2 and is locked in phase and frequency is reproduced, and the reproduction clock e
The reproduced clock f having a phase difference of 180 °
5 and the digital data a for identification is given by Ts ″ = T
h ". The phase comparison characteristic of the charge pump type phase comparator 122 at each of the relative speeds shown in FIGS. 2, 3 and 4 is not affected by the change in the relative speed as shown in FIG. As described above, according to this embodiment, two delayed digital signal generators with taps are connected in cascade, and reproduced digital data taken out from the connection is used as digital data for identification. In addition to the timing of the digital data for identification from among the digital data of each of the plurality of timings under the control of the relative speed detector in accordance with the change of the relative speed, the timing always optimally delayed in the delay direction. Digital data is selected by each multiplexer and added to the phase comparison signal generator to generate a phase comparison signal. Even if the speed is changed, there is no phase error period in which the phase comparison sensitivity of the charge pump type phase comparator of the clock recovery PLL unit becomes zero, and a stable phase comparison characteristic can always be secured.
The responsiveness of the LL section can be improved, and the digital data for identification is taken out from the connection section of the two delayed digital signal generators with taps, so that the adjustment of the identification timing of the reproduced clock is unnecessary and the optimal identification timing is always obtained. Can be obtained. As is apparent from the above embodiment, the clock recovery apparatus according to the present invention delays the input digital data at regular time intervals and outputs digital data at a plurality of timings. Means and a control signal, the digital data for identification is selected from a plurality of digital data at the output of the delay means with tap with respect to the timing of the digital data for identification, and one digital data of a timing always optimally delayed is always equal in the delay direction. Data selection means for selecting and outputting only the data, phase comparison signal generation means for generating a phase comparison signal from two digital data at different timings, and obtaining a change in the frequency of the digital data from the relative speed between the recording medium and the reproduction means. A relative speed detecting means for controlling the data selecting means, A clock recovery PL that detects a phase difference from a phase comparison signal and controls it by feedback so that the lock frequency and phase match the digital data frequency and phase.
By providing the L means and the identification means for identifying digital data by the recovered clock, there is no phase error period in which the phase comparison sensitivity of the charge pump type phase comparator of the clock recovery PLL means becomes zero even if the relative speed changes. Since a stable phase comparison characteristic can always be ensured, even when a portion where reproduced digital data is interrupted due to head switching such as a VTR or a portion where the phase of reproduced digital data has no correlation at an edit point is reproduced, the clock reproduction P
The LL means can respond quickly, and erroneous identification of reproduced digital data can be suppressed in a short time. Further, since the identification timing of the digital data for identification can be always adjusted to the optimum timing without adjustment, erroneous identification due to a timing shift can be reduced, and the practical effect is large.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of a clock reproducing device according to an embodiment of the present invention. FIG. 2 is a clock reproducing device according to an embodiment of the present invention. FIG. 3 is a timing chart when the reproduction clock of the clock reproduction PLL is locked in phase and frequency with respect to the reproduction digital data. FIG. 4 is a timing chart when the relative speed between the head and the tape is reduced by 15% compared to FIG. 2 in the clock reproducing apparatus according to the embodiment of the present invention. FIG. 5 is a diagram showing a phase comparison characteristic at each relative speed in the clock recovery device according to the embodiment of the present invention. FIG. 7 is a block diagram of a lock reproducing apparatus. FIG. 7 shows a conventional clock reproducing apparatus which reproduces a portion in which digital data having a frequency of 1/2 of a recording master clock is recorded. FIG. 8 is a timing chart when the relative speed between the head and the tape is increased by 15% as compared with FIG. 7 in the conventional clock reproducing apparatus. FIG. 9 is a timing chart in the conventional clock reproducing apparatus. FIG. 10 is a timing chart when the relative speed between the head and the tape is reduced by 15% compared to the case of FIG. 10. FIG. 10 is a phase comparison characteristic diagram at each relative speed in the conventional clock reproducing apparatus. Digital signal generators 113 and 114 Multiplexer 115 Relative speed detector 120 Phase comparison signal generator Vessel 121 clock reproduction PLL unit 125 identifier

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Claims (1)

(57) Claims 1. Tapped delay means for delaying input digital data at fixed time intervals and outputting digital data at a plurality of timings, and the tapped delay means by a control signal Data selection means for selecting and outputting only one digital data at a timing which is advanced from the plurality of output digital data at the timing of the identification digital data and which is always optimally delayed in the delay direction. A phase comparison signal generating means for generating a phase comparison signal from the two digital data at different timings; and a change in the frequency of the digital data is obtained from a relative speed between the recording medium and the reproducing means, and control is applied to the data selecting means. The relative speed detecting means and the frequency and phase of the recovered clock are Clock regeneration apparatus provided with identification means for identifying a clock reproduction PLL unit controlled by feedback by detecting the phase difference, the digital data by the recovered clock and said phase comparison signal to match the number and phase.