JP3381550B2 - Wiring formation method - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring forming method including a step of filling a connection hole with a conductive material layer such as W (tungsten). In particular, the conductive material layer formed so as to fill the connection hole is anisotropically etched. After making the plug thinner and forming the plug in the connection hole, the seam hole of the plug is processed by taper etching so that the size gradually increases from the inside toward the opening end, thereby making it possible to form a highly reliable wiring. It is a thing.

[0002]

2. Description of the Related Art Conventionally, as a method of forming a wiring of a semiconductor device such as an LSI, after forming a W layer so as to fill a connection hole,
It is known that the W layer is thinned by an etch back process, a part of the W layer is left as a plug in the connection hole, and a wiring material layer such as an Al alloy is formed by a reflow sputtering method so as to cover the plug ( See, for example, Japanese Patent Laid-Open No. 7-115074). 10 to 12 show a conventional method of this type.

In the process of FIG. 10, after forming the field insulating film 12 having the element hole 12A on the surface of the semiconductor substrate 10, a MOS transistor is formed in the element hole 12A by a known method. The MOS transistor shown is
The gate insulating film F, the gate electrode layer G, the side spacers H ₁ and H _2, and the source region S ₁ having a relatively low impurity concentration.
And a drain region D ₁ and a source region S and a drain region D having a relatively high impurity concentration.

Next, an interlayer insulating film 14 of silicon oxide or the like is formed by CVD (Chemical Vapor Deposition) so as to cover the MOS type transistor in the element hole 12A and the insulating film 12.
It is formed by the method. Then, a connection hole 14S reaching the source region S and a connection hole 14D reaching the drain region D are formed in the insulating film 14 by known photolithography and dry etching processing.

Next, an adhesion layer 20A made of Ti, TiN or the like covering the insides of the connection holes 14S and 14D and the insulating film 12.
Are formed by a sputtering method or the like. The adhesion layer 20A is provided to improve the adhesion of the W layer formed thereafter.

After that, the contact hole 14 is covered with the contact hole 14A.
A W layer 22A is formed by a blanket CVD method so as to fill S and 14D.

In the process of FIG. 11, the W layer 22A is thinned by an etch-back process, and the first and second portions of the W layer 22A are plugged into the connection holes 14S and 14D, respectively.
Leave as 4D. In this case, the etch back process is performed in two steps of main etching and over etching. In the main etching step, the adhesion layer 20A
Etching until exposed. In the over-etching step, as shown in FIG. 13, the etching residues 22a, 2a of the W layer 22A remaining in the recesses of the insulating film 14 and the like are shown.
Etching is performed so as to remove 2b.

In the process of FIG. 12, a wiring material layer 24 of Al alloy or the like is formed by a sputtering method or the like so as to cover the adhesion layer 20A and the plugs 22S and 22D. Then, the wiring material layer 24 is reflowed by heat treatment to improve the coverage at the step portions Q ₁ and Q ₂ . Thereafter, the wiring material layer 24 is patterned in accordance with a desired wiring pattern to form the plug 22.
A source wiring layer and a drain wiring layer which are respectively connected to S and 22D are formed.

[0009]

According to the above-mentioned prior art, when depositing the W layer 22A in the step of FIG. 10, as the W deposition on the inner walls of the contact holes 14S, 14D progresses, the contact holes 14S, 14D. The supply of the material gas (WF ₆ ) to the inside of the connection holes is limited, and the deposition rate of W becomes slower inside the connection holes 14S and 14D than at the outside of the connection holes 14S and 14D. Then, the W layer 22A is formed above the connection holes 14S and 14D.
When the opposing parts of the above contact and close the inside, the material gas is no longer supplied to the inside, and the deposition of W stops. As a result, the seam hole V is formed in the connection holes 14S and 14D.
₁ , V ₂ is formed.

In the etch back process of FIG. 11 , it is usual to carry out etching under anisotropic etching conditions in both steps of main etching and over etching. This is because if the etching is performed under isotropic etching conditions in any of the steps, the W layer 22A is removed and the plugs 22S and 22D cannot be formed.

As shown in FIG. 13, at the place where the concave portion is formed in the insulating film 14 due to the absence of the insulating film 12 or the presence of the wiring layers G _{1 to} G ₃ , the W layer 22A is formed at the end of the anisotropic main etching. Portions 22a and 22b are left unetched
Left as. This is because the W layer 22A is formed relatively thick in the concave portions of the insulating film 14 as indicated by thicknesses t ₁ and t ₃ and relatively thin in the convex portion of the insulating film 14 as indicated by thickness t _2. It is due to being done. W
The etching residues 22a and 22b made of (4) may cause a short circuit between the wirings and thus need to be removed.

Therefore, in the over-etching step, anisotropic etching is performed excessively in order to completely remove the etching residue. As a result, the upper portions of the plugs 22S and 22D are scraped as shown in FIG.
Concave portions R ₁ and R ₂ are formed. Also, the seam hole V ₁ ,
V ₂ is exposed. Furthermore, in the wide connection hole (or scribe region) as shown in FIG. 14, a part of the W layer 22A is left on the side wall of the concave portion of the insulating film 14 as a laterally bulging coating 22c.

After that, if the wiring material layer 24 is formed in the step of FIG. 12, the coverage is deteriorated at the points Q ₁ and Q _{2 in} FIG. 12 and the point Q ₃ in FIG. Although it is possible to improve the covering property by using the reflow-type sputtering method, it is difficult to eliminate the seam holes V ₁ and V ₂ . As another method, even if the wiring material layer 24 is formed by using the CVD method which is known to have good coverage, the inner diameters of the seam holes V ₁ and V ₂ are very small, and therefore the seam holes V ₁ and V _{2 are formed.} It is difficult for the CVD gas to enter the inside, and the seam holes V ₁ and V ₂ cannot be completely filled.

If the seam holes V ₁ and V ₂ are left as voids, the source wiring layer and the drain wiring layer come into contact with the voids. Therefore, the voids such as V ₁ and V ₂ may expand and move in the wiring layer due to electromigration or the like starting from the voids, causing disconnection, which lowers the reliability of the wiring. There is.

An object of the present invention is to provide a novel wiring forming method which can improve the reliability of wiring by eliminating the above voids.

[0016]

A wiring forming method according to the present invention comprises a step of preparing a substrate having a connected portion on one main surface, and a step of covering the connected portion on one main surface of the substrate. Forming an insulating film, forming a connection hole in the insulating film to reach the connection target portion, forming a conductive material layer so as to fill the connection hole and cover the insulating film; Of the conductive material layer as a plug so that the conductive material layer is thinned by anisotropic etching so as to connect to the connected portion in the connection hole, and a seam hole of the plug isotropically etched. Is the process of processing
Gradually from the inside of the seam hole toward the open end.
Increase in internal size and internal size above the bottom of the seam hole
As the number of wires increases to allow the embedding of wiring material,
The plug completely covers the bottom surface of the connection hole
And that the seam holes are processed so that
Forming a wiring material layer covering the insulating film and the plug after processing the seam hole of the plug ,
The inside of the processed seam hole of the plug is filled with the wiring material layer.
The method includes forming the wiring material layer so as to be exhausted, and patterning the wiring material layer to form a wiring layer connected to the plug.

According to the method of the present invention, the seam hole of the plug is processed by isotropic taper etching . this
In this case, the size gradually increases from the inside of the seam hole toward the open end, and the internal size above the bottom of the seam hole is the wiring.
The material should be increased to allow for embedding, and
So that the plug covers the bottom surface of the connection hole entirely.
The seam hole is processed. After the seam hole is processed in this manner, the wiring material layer is formed so as to cover the plug, so that the wiring material layer can be formed so as to fill the processed seam hole. Therefore, the seam hole is not left as a void, and the reliability of the wiring can be improved.

In the method of the present invention, a conductive barrier layer may be formed after the seam hole of the plug is processed and before the wiring material layer is formed to cover the plug. The barrier layer prevents diffusion of Al or the like forming the wiring material layer, so that the junction leak resistance can be improved. Further, the barrier layer can be used also as an adhesion layer, and the adhesion can be improved.

[0019]

1 to 7 show a wiring forming method according to an embodiment of the present invention, and steps (1) to (7) corresponding to the respective drawings will be sequentially described.

(1) A field insulating film 12 made of Si oxide is formed on the surface of a semiconductor substrate 10 made of, for example, Si (silicon) by a known selective oxidation method so as to have an element hole 12A. After forming a gate insulating film F on the semiconductor surface in the element hole 12A of the insulating film 12 by a thermal oxidation method or the like, a poly-Si layer or a polycide layer (a stack of a poly-Si layer and a silicide layer) is deposited and patterned. By doing so, the gate electrode layer G is formed. At this time, if desired, the gate insulating film F can be patterned in the same pattern as the gate electrode layer G.

Next, the source region S ₁ and the drain region having a relatively low impurity concentration are formed by a selective impurity introduction process (for example, ion implantation process) using the insulating film F and the electrode layer G as a stack and the insulating film 12 as a mask. Form D ₁ . And
A side spacer material such as Si oxide is deposited on the upper surface of the substrate and an etchback process is performed to form side spacers H ₁ and H ₂ on both sides of the gate electrode layer G.

Thereafter, a selective impurity introduction process (for example, an ion implantation process) is performed relatively using the gate portion GP including the insulating film F, the electrode layer G and the side spacers H ₁ and H ₂ and the insulating film 12 as a mask. A source region S and a drain region D having a high impurity concentration are formed.

(2) PSG (phosphosilicate glass) and BPSG (boron / phosphosilicate glass) are sequentially deposited so as to cover the MOS transistor in the element hole 12A and the insulating film 12 and have a thickness of about 0.8 μm. Interlayer insulating film 1 having
4 is formed. Then, the source connection hole 14S and the drain connection hole 14D having a diameter of about 0.45 μm are formed in the insulating film 14 by well-known photolithography and dry etching so as to reach the source region S and the drain region D, respectively.

(3) An adhesion layer 20 containing TiN, TiON, Ti, etc. is formed by sputtering or CVD, covering the insides of the connection holes 14S, 14D and the insulating film 12. As an example, the adhesion layer 20 is 5 to 50 (preferably 20).
After depositing the Ti film 16 with a thickness of nm, a Ti film with a thickness of 50 to 200 (preferably 100) nm is formed on the Ti film 16.
The N film 18 is deposited and formed. T instead of the TiN film 18
An iON film may be used.

The Ti film 16 can be deposited by a sputtering method, and the film forming conditions can be, for example, a substrate temperature: 150 ° C., an Ar flow rate: 30 sccm, a pressure: 3 mTorr, and a sputtering power: 1150 W.

For depositing the Ti film 16, it is preferable to use a collimating sputtering method or a long throw sputtering method. By using such a method, a sufficient Ti film thickness can be obtained at the bottom of the fine connection hole. Further, a Ti film having an ideal covering property can be formed by using the CVD method.

The material of the adhesion layer 20 is not limited to those described above, but an alloy of a refractory metal such as TiW, a metal silicide, or a stack of a metal silicide and a metal nitride such as TiN,
A laminated layer of a refractory metal and its nitride (or boride) may be used.

After forming the adhesion layer 20, in order to improve the heat resistance and the barrier property of the adhesion layer 20, a rapid thermal treatment (lamp annealing for 10 to 60 seconds at a substrate temperature of 500 to 800 ° C. in an N ₂ atmosphere is performed. Like Rapid Thermal Anneal
[RTA} processing) may be performed.

(4) The conductive material layer 2 made of a plug material such as W covering the insides of the connection holes 14S and 14D and the adhesion layer 20.
2 is formed by the CVD method. The thickness of the conductive material layer 22 is selected so that the connection holes 14S and 14D are filled with the conductive material.
That is, a film thickness of ½ or more of the diameter of the connection hole to be filled is selected, and as an example, 100 to 800 (preferably 40).
0-600) nm is selected. The thinner the conductive material layer 22, the less the load on the film forming apparatus.

As the material of the conductive material layer 22, a metal species having a compound having a high vapor pressure such as WF ₆ is selected. As an example, when W is deposited by the CVD method, the film forming conditions are: substrate temperature: 450 ° C. gas flow rate: WF ₆ / H ₂ / Ar = 40/400/225
The pressure can be 0 sccm and 10 kPa.

Examples of other metal materials include Mo and T
Any metal having a low boiling point and high vapor pressure compound gas such as a, Ti, Ni, Cu and Pt can be used similarly to W. As the metal source gas exemplified here, MoF
₆ [deposition temperature Td = 400 to 800 ° C.], TaF ₂ [T
d = 600 to 1000 ° C.], TiCl ₄ [Td = 350
To 600 ° C.], Ni (CO) ₄ [Td = 100 to 300]
C], Pt (CO) ₂ Cl ₂ [Td = 200 to 600
℃] is known.

When forming the conductive material layer 22, the seam holes V ₁ and V ₂ are formed in the connection holes 14S and 14D as described above.

(5) Conductive material layer 2 by etch back treatment
2 is thinned and the first and second portions of the conductive material layer 22 are plugged into the connection holes 14A and 14B, respectively.
Leave as. The etch back process is performed in two steps of main etching and over etching.

In the main etching step, the conductive material layer 22 is dry-etched under anisotropic etching conditions until the adhesion layer 20 is exposed. When the dry etching at this time is performed by the RIE (reactive ion etching) method, the etching conditions are, for example, gas flow rate: SF ₆ / Ar = 30 to 140/40 to 140.
(Preferably 110/90) sccm High frequency power: 450 W Pressure: 32 Pa

To detect the etching end point of W, the emission intensity of F ⁺ (wavelength 704 nm) is monitored, and the emission intensity of F ⁺ increases (at the time when the derivative of the emission intensity increases).
Can be performed by detecting.

The main etching may be performed until the adhesion layer 20 is removed on the insulating film 14 and the insulating film 14 is exposed.

After the main etching, over-etching is performed with the same etching device (or another etching device). In the overetching step, V ₁ ,
Each seam hole such as V ₂ is processed so that its diameter gradually increases from the bottom toward the opening end (so that the side wall inclination angle of each seam hole becomes smaller than 90 ° (so-called forward taper shape). Taper etching is applied to each seam hole)
At the same time, dry etching is performed under isotropic etching conditions so as to completely remove the etching residue of W such as 22a and 22b in FIG.

In order to shorten the etching time, it is preferable to carry out over-etching in the same etching apparatus as the main etching by changing the etching conditions. The etching conditions are, for example, gas flow rate: SF ₆ / Ar / O ₂ = 50 to 180/0 to 9
0/0 to 50 (preferably 140/0/5) sccm, high frequency power: 200 W, pressure: 27 Pa. Here, the reason why O ₂ gas is added is to facilitate the processing of the seam hole into a forward tapered shape. H _{2 that} can be a source of oxygen instead of O ₂ gas
O, it may be used O ₃ (ozone) gas such as.

As a result of the over-etching, the seam holes such as V ₁ and V ₂ increase in size from the bottom toward the opening end as shown in FIG. 5, and are filled up by the wiring material layer formed thereafter. It will be easy.

(6) Plug 2 in connection holes 14S, 14D
The wiring material layer 24 is formed by a sputtering method, a CVD method, or the like so as to cover the exposed portions of the 2S, 22D and the adhesion layer 20, and reflowed so that the wiring material layer 24 sufficiently fills the seam holes V ₁ , V ₂ if necessary. Perform processing.

As the wiring material layer 24, an Al layer or Al-
An Al alloy layer such as Si or Al-Si-Cu can be formed to a thickness of 100 to 1000 (preferably 500) nm by a sputtering method. The film forming conditions at this time may be, for example, substrate temperature: 200 ° C., Ar flow rate: 33 sccm, pressure: 2 mTorr, and sputtering power: 9000 W. After forming the layer 24 in this manner, the substrate 10 having the layer 24 is heated to 400 to 550 ° C. to reflow the layer 24, thereby forming the seam holes V ₁ ,
V ₂ is fully filled with layer 24. In this case, the connection hole 14
In the flat part away from S and 14D, the film thickness does not change even when the layer 24 flows.

When the collimate sputtering method or the long throw sputtering method is used when the layer 24 is sputtered, a sufficient initial film thickness can be obtained even at the bottom of the seam hole of the fine plug, so that the hole can be filled under a simpler reflow condition. .

As the wiring material layer 24, Cu or a Cu alloy (Cu-Cr, Cu-Z) is used instead of the Al or Al alloy layer.
r, Cu-Pd, etc.) may be used, and in this case, the target at the time of sputtering is merely replaced with Cu or a Cu alloy.

As a film forming method suitable for filling the seam holes V ₁ and V ₂ , a PVD (physical vapor deposition) method or a CVD method may be used instead of the above-mentioned reflow sputtering method.

When the PVD method is used, film formation and hole filling can be simultaneously achieved without an independent reflow process. For example, when the high temperature sputtering method is used, the substrate 10 is heated while the Al or Al alloy forming the wiring material layer 24 is sputtered, and finally the substrate temperature is 400 to 55.
Film formation and hole filling can be achieved all at once by heating to 0 ° C.

Further, when the CVD method is used, there is an advantage that the seam hole of the fine plug can be easily filled in corresponding to the miniaturization of the connection hole. For example, a film can be formed using a gas such as dimethyl aluminum hydride (DMAH) and H ₂ gas (carrier gas) at a substrate temperature of 100 to 250 ° C. and a gas flow rate of 200 to 500 sccm. In this case, when the substrate temperature is set low, the formed Al layer (layer 24) does not reflow, so that the coverage is conformal. Therefore, the Al layer (layer 2
4) is heated in a vacuum or in an inert gas for reflow to fill the seam pores with an Al layer (layer 2).
4) can be obtained.

It is also possible to fill the seam holes V ₁ and V ₂ by growing a metal layer only on the plugs 22S and 22D by selecting growth conditions selective to the base.

Instead of directly covering the plugs 22S and 22D and the adhesion layer 20 to form the wiring material layer 24 as described above, the plugs 22S and 22D and the adhesion layer 20 are directly covered to form a conductive barrier layer. After forming 23, the barrier layer 2
Alternatively, the wiring material layer 24 may be formed on the wiring 3. In this case, the barrier layer 23 can prevent the diffusion of Al or the like forming the wiring material layer 24, so that the junction leak resistance can be improved. The barrier layer 23 is C
It also functions as an adhesion layer when the wiring material layer 24 is formed by the VD method. Therefore, the reliability can be further improved.

The barrier layer 23 can be formed by sequentially depositing a Ti layer and a TiN layer (or a TiON layer) by a sputtering method or the like in the same manner as the adhesion layer 20 described above.

The material of the barrier layer 23 is not limited to those described above, but an alloy of a refractory metal such as TiW, a metal silicide, a stack of a metal silicide and a metal nitride such as TiN, a refractory metal and its nitride. (Or boride) and the like may be used.

After forming the barrier layer 23, the barrier layer 23
In order to improve the heat resistance and the barrier property of the above, a rapid thermal treatment (RTA treatment) may be performed at a substrate temperature of 500 to 800 ° C. for 10 to 60 seconds in an N ₂ atmosphere.

A conductive cap layer 26 may be formed on the wiring material layer 24 regardless of whether or not the barrier layer 23 is formed. The cap layer 26 can be formed by sequentially depositing a Ti layer of about 7 nm and a TiN layer of about 40 nm, for example. The cap layer 26 prevents light reflection during photolithography, prevents oxidation of the wiring material layer 24, and protects the wiring material layer 24 from A.
It has a function of preventing diffusion of l and the like.

(7) The wiring material layer 24 is patterned by the well-known photolithography and dry etching processes to leave the first and second portions 24S and 24D of the layer 24 connected to the plugs 22S and 22D, respectively. When the barrier layer 23 and / or the cap layer 26 are formed, both layers are patterned together with the wiring material layer 24 to form the first and second portions 23S and 23D of the layer 23 and / or the first and second portions of the layer 26. The second portions 26S and 26D are left.

Source wiring layer 28 connected to the plug 22S
S includes the remaining portion 24S of the wiring material layer 24, and is the layer 23 when the barrier layer 23 and / or the cap layer 26 is formed.
23S and / or the remaining portion 26S of the layer 26. Drain wiring layer 28D connected to the plug 22D
Includes the remaining portion 24D of the wiring material layer 24, and includes the barrier layer 2
3 and / or when the cap layer 26 is formed, it also includes the remaining portion 23D of the layer 23 and / or the remaining portion 26D of the layer 26.

In the above embodiment, the wiring layers 28S and 2 connected to the source region S and the drain region D, respectively.
8D was formed, but by applying the steps of FIGS.
It is possible to form upper layer wiring such as 8S and 28D connected to the wiring layer.

[0056] In the above embodiment has been processed into wholly forward tapered to V _1, V _2, etc. seam holes of in the step of FIG. 5, the seam holes as illustrated for the seam holes V ₁ in FIG. 9 Only the upper part may be processed into a forward tapered shape. That is, the seam hole V ₁ is divided into an upper portion and a lower portion with a position intermediate between the bottom portion and the opening end as a boundary, and the lower portion having a depth h to the bottom portion has a substantially constant diameter d except near the bottom portion and from the lower portion. The seam hole V ₁ may be machined so that the diameter gradually increases from d to the opening end in the upper portion reaching the opening end.

In the plug structure of FIG. 9, the seam hole V
The wiring material layer (corresponding to 24 in FIG. 6) such as an Al alloy formed on the plug 22S having ₁ is reflowed to form the seam hole V.
_{When 1} is buried, if h / d is 1.0 or less, the lower part of the seam hole V ₁ can be buried with the reflowed wiring material. Also, a wiring material layer such as Al alloy (corresponding to 24 in FIG. 6)
Is formed by the MOCVD (Metalorganic CVD) method, the lower part of the seam hole V ₁ can be filled with the wiring layer even if h / d is about 2.0.

According to the embodiment of the present invention described above, the following operational effects can be obtained.

(A) Since the wiring material layer 24 can be formed so as to fill the seam holes V ₁ and V ₂ processed as shown in FIG. 6, the seam holes V ₁ and V ₂ serve as voids. It is not left behind and the coverage of the wiring material layer 24 is improved. Therefore, the reliability of the wiring is significantly improved.

(B) In a wide connection hole (or scribe region) as shown in FIG. 8, a part of the conductive material layer 22 is formed on the side wall of the concave portion of the insulating film 14 by isotropic over-etching to form a smooth concave surface. Since the smoothing film 22d having a curved surface is left, the coverage of the wiring material layer 24 is improved.

(C) The isotropic overetching is 22a, 2a in FIG. 13 as compared with the anisotropic overetching.
It is easy to remove the etching residue as shown as 2b. That is, in isotropic overetching, etching proceeds not only in the vertical direction but also in the horizontal direction.
Etching residue that is difficult to remove by anisotropic over-etching can be removed in a short time. Therefore, the overetching time can be shortened and the manufacturing cost can be reduced by improving the throughput.

(D) When the overetching time is shortened, the amount of film loss of the plugs 22S and 22D shown in FIG. 5 is reduced, so that the coverage of the wiring material layer 24 is improved.

(E) The wiring material layer 24 of Al alloy or the like has a smaller resistivity than the conductive material layer 22 of W or the like. Therefore, FIG.
As compared with the case where most of the connection holes are filled with W plugs as shown in FIG. 2, the case where the connection holes are filled with the conductive material of the layer 22 and the wiring material of the layer 24 as shown in FIG. The resistance of the entire plug can be reduced. Moreover, in the plug structure shown in FIG. 6, the seam hole V as shown in FIG.
_{Since 1} and V ₂ are not left as voids, the resistance of the entire plug can be further reduced. Therefore, a high-performance LSI with low wiring resistance can be realized.

[0064]

As described above, according to the present invention, the conductive material layer formed so as to fill the contact hole is thinned by anisotropic etching to form a plug in the contact hole, and then isotropic.
The plug seam hole is processed by taper etching of
Then, gradually move from the inside of the seam hole toward the open end.
Increased size and internal size above the bottom of the seam holes
The width of the wiring material so that it can be embedded.
Even the plug remains so that the bottom of the connection hole is completely covered
Since it was done, it is arranged so as to fill the processed seam holes.
A wire layer can be formed. Therefore, the seam holes are
Is not left behind and the seam hole has a low resistivity
Can be filled with the wiring material, and an effect that highly reliable and low resistance wiring can be realized at low cost can be obtained.

Further, if a conductive barrier layer is formed after the seam hole of the plug is processed and before the wiring material layer is formed, the junction leak resistance and the adhesion can be improved, and the reliability of the wiring is further improved. There is also an effect.

[Brief description of drawings]

FIG. 1 is a substrate cross-sectional view showing a transistor forming step in a wiring forming method according to an embodiment of the present invention.

FIG. 2 is a substrate cross-sectional view showing an interlayer insulating film forming step and a connection hole forming step that follow the step of FIG.

FIG. 3 is a substrate cross-sectional view showing an adhesion layer forming step following the step of FIG.

4 is a substrate cross-sectional view showing a conductive material layer forming step following the step of FIG.

FIG. 5 is a substrate cross-sectional view showing an etchback process following the process of FIG.

6 is a substrate cross-sectional view showing a wiring material layer forming step following the step of FIG.

FIG. 7 is a substrate cross-sectional view showing a wiring patterning process that follows the process of FIG.

8 is a substrate cross-sectional view showing a wide connection hole (or a scribe region) in the process of FIG.

FIG. 9 is a cross-sectional view showing a modified example of seam hole processing.

FIG. 10 is a substrate cross-sectional view showing a conductive material layer forming step in a conventional wiring forming method.

FIG. 11 is a substrate cross-sectional view showing an etchback process following the process of FIG.

12 is a substrate cross-sectional view showing a wiring material layer forming step following the step of FIG.

FIG. 13 is a substrate cross-sectional view showing an etching state in the process of FIG.

14 is a substrate cross-sectional view showing a wide connection hole (or a scribe region) in the process of FIG.

[Explanation of symbols]

10: semiconductor substrate, 12: field insulating film, 14: interlayer insulating film, 16: Ti layer, 18: TiN layer, 20: adhesion layer, 22: conductive material layer, 22S, 22D: plug, 23:
Barrier layer, 24: Wiring material layer, 26: Cap layer, 28
S, 28D: wiring layer.

Continuation of front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 21/768 H01L 21/28

Claims (2)

(57) [Claims] 1. A step of preparing a substrate having a connected portion on one main surface; a step of forming an insulating film on the one main surface of the substrate to cover the connected portion; Forming a connection hole reaching the connected portion; forming a conductive material layer so as to fill the connection hole and cover the insulating film; and thin the conductive material layer by anisotropic etching to form the connection. A step of leaving a part of the conductive material layer as a plug in the hole so as to connect to the connected portion, and a step of processing the seam hole of the plug by isotropic taper etching , wherein the inside of the seam hole is Open from
The size gradually increases toward the mouth end and the seam hole
The internal size from the bottom to the top should allow the embedding of wiring material.
In order to increase
The seam hole so that it remains with the entire surface covered.
And a step of forming a wiring material layer covering the insulating film and the plug after processing the seam hole of the plug ,
The inside of the processed seam hole of the plug is filled with the wiring material layer.
A wiring forming method comprising: forming the wiring material layer so as to be exhausted; and forming a wiring layer connected to the plug by patterning the wiring material layer. 2. The method further comprises the step of forming a conductive barrier layer over the insulating film and the plug after processing the seam hole of the plug and before forming the wiring material layer, wherein the wiring material layer is formed. In the forming step, the wiring material layer is formed so as to cover the barrier layer, and in the step of forming the wiring layer, a wiring layer including the barrier layer and the wiring material layer is patterned to form a wiring layer formed of the remaining portion of the wiring layer. The wiring forming method according to claim 1, wherein the wiring is formed.