JP3382068B2 - Signal processing device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention is used in a signal processing device for a high resolution radar.

[0002]

2. Description of the Related Art High resolution radars such as synthetic aperture radars are
It is used to observe the ground and the sea, regardless of the weather. In FIG. 17, a radar is mounted on an airplane, for example,
An example of observing the ground will be shown. In this case, the traveling direction of the airplane, that is, the radar is called the azimuth direction, and the direction of emitting the radio wave (beam 1) is called the range direction. The radar emits a radio wave by dividing it into short pulses, and receives a reflected wave reflected by an object. When the object A and the object B are close to each other in the same range direction as shown in FIG. 17, the reflected pulses overlap as shown in FIG. 18, and the object A and the object B are received on the radar reception image. Cannot be separated and recognized. Therefore, in the high-resolution radar, the received data is subjected to chirp compression (hereinafter referred to as range compression) by the signal processing device to improve the resolution in the range direction. Also,
In FIG. 17, the object A and the object C are close to each other in the azimuth direction. At this time, azimuth compression can be performed to improve the resolution in the azimuth direction.

In addition, in order to recognize the changing state of volcanic activity and ship movements with a high resolution radar, it is necessary to process a large amount of continuous data with a signal processing device in real time. ing. FIG. 19 is a block diagram showing a configuration of a conventional signal processing device, where 1 is an input data memory for storing input image data from the outside,
Reference numeral 8 denotes an arithmetic processing unit that performs range compression processing, range migration processing, and azimuth compression processing on the input image data stored in the input data memory 1, and outputs the output image data. Reference numeral 7 stores the output image data. Output data memory.

The conventional signal processing apparatus is configured as described above, and the arithmetic processing unit 8 performs the range compression processing and range migration shown below for a large amount of input image data input to the input data memory 1 from the outside. By executing the processing and the azimuth compression processing in order, output image data with improved image resolution is output.

FIG. 20 is a flow chart showing the processing contents of the arithmetic processing unit 8 described above. 18 to 21 show the processing contents of the range compression processing, 22 to 24 show the processing contents of the range migration processing, and 25. ˜ 28 show the processing contents of the azimuth compression processing. The input image data, range compressed image data, distance corrected image data, and output image data shown below are two-dimensional data having two axes, the azimuth axis direction and the range axis direction. The range compression processing is to take a correlation between the input image data and the range reference function. That is, the FFT is added to the one-dimensional input image data obtained by dividing the input image data along the range axis direction.
(Fast Fourier Transform
Ion) calculation (step 18), multiplication with a range reference function that correlates with the one-dimensional input image data to improve resolution in the range direction (step 19), and IFF
T (Inverse Fast Fourier Tr)
information) calculation (step 20). By performing the above operation for all the one-dimensional input image data, range compressed image data with improved resolution in the range direction is obtained.

This range compressed image data shows the composition of the distance in the range axis direction and the distance in the azimuth axis direction. Therefore, even if the distance in the range axis direction is the same,
The coordinates in the range axis direction are displaced by the distance movement amount that is a function of the azimuth value. In the range migration processing, the distance shift amount is calculated for each one-dimensional range compressed image data that is divided along the range axis, that is, has a unique azimuth value from the unique azimuth value (step 2).
2) Then, the one-dimensional range compressed image data is rearranged along the range axis by the distance movement amount which is the calculation result (step 23), and as a result, the distance corrected image data is obtained.

The azimuth compression processing correlates the distance corrected image data with the azimuth reference function. Therefore, the FFT calculation is performed for each one-dimensional distance correction image data obtained by dividing the distance correction image data along the azimuth axis direction (step 25).
And in order to improve the resolution in the azimuth direction, multiplication with an azimuth reference function that correlates with the one-dimensional distance correction image data (step 26) and IFFT calculation (step 2).
7) is performed and the above operation is performed for all the one-dimensional distance correction image data to obtain output image data.

Next, the azimuth compression process will be described in more detail. FIG. 21 shows the distance-corrected image data after the range compression process and the range migration process. In the figure, the range direction is the x-axis and the azimuth direction is the y-axis. The distance-corrected image data is set in the range direction, for example, x _0.
To y ₂₀₄₈ and 2048, and y ₀ to y ₁₀₂₄ and 1024 in the azimuth direction. The one-dimensional distance-corrected image data obtained by dividing the distance-corrected image data, which is the input of the azimuth compression processing, along the azimuth axis direction is 2048 lines as shown in the figure. The azimuth compression processing is completed for all of these 2048 lines, and one image data is completed. Furthermore, in the azimuth compression process, 1
The FFT calculation (step 25), the multiplication with the azimuth reference function (step 26), and the IFFT calculation for the partial one-dimensional distance correction image data obtained by dividing the one-dimensional distance correction image data into units of the length of the correlation length. (Step 27) is being performed. An example thereof will be described with reference to FIG. FIG. 22 shows an example in which the one-dimensional distance correction image data divided along the azimuth axis direction corresponding to the range direction x ₁ is further divided by the correlation length. Here, the correlation length is 256 pixels in the azimuth direction. As shown in the figure,
With respect to the one-dimensional distance corrected image data in the section from y ₀ to y ₂₅₅ , the calculation of step 27 is performed from step 25 to obtain one pixel of output image data. Next, similar processing is performed on the one-dimensional distance correction image data in the section from y ₁ to y _{256, which is} shifted by one pixel in the azimuth direction. In this way, y
The same processing is continuously performed from ₇₆₈ to y ₁₀₂₃ section, and x =
An image of one line of the output image corresponding to the x ₁ section (y ₀ , y ₁₀₂₃ ) is obtained. Therefore, in this example, the azimuth compression processing repeats the processing from step 25 to step 2048 times (1024-256 + 1) times.

The conventional signal processing device has the above-mentioned arithmetic processing unit 8
Since a general-purpose computer such as a workstation is used in the above, and the processing is sequentially performed according to the processing flow shown in FIG. 20, it takes a time of several minutes to several hours to process the data obtained in the observation time of several seconds. I needed it.

[0010]

The conventional signal processing apparatus is constructed as described above. Therefore, in the conventional range compression process, F performed in the range compression process is performed.
Since the FT operation, the multiplication with the range reference function, and the IFFT operation are sequentially processed, there is a problem that much processing time is required. Further, in the conventional azimuth compression process, since the FFT operation performed in the azimuth compression process, the multiplication with the azimuth reference function, and the IFFT operation are sequentially processed, there is a problem that a lot of processing time is required. there were. Further, in the range compression processing, there is a problem that the next processing cannot be executed until the processing of the data for one image is completed. Further, in the azimuth compression processing, the one-dimensional distance correction image data in the azimuth direction is further divided by the correlation length and sequentially processed in time series, so that there is a problem that much processing time is required. Further, since one image is stored for each of the input data and the output data for the range compression process, there is a problem that a large amount of memory is required.

The present invention has been made to solve the above problems, and it is possible to obtain a signal processing device capable of high-speed signal processing by multiplexing the range compression processing and the azimuth compression processing. To aim. Another object of the present invention is to obtain a signal processing device capable of reducing the size of memory required for compression processing.

[0012]

A signal processing apparatus according to the present invention comprises an input data storage means for storing input data,
In a signal processing device comprising a compression means for compressing and outputting input data, and an output means for outputting the compressed data, the compression processing means comprises a reference function memory storing a reference function, and input data. By switching between the FFT operator for performing FFT operation on the above, the first multiplier for multiplying the output of the FFT operator and the output of the reference function memory, the output of the FFT operator and the output of the first multiplier. A pre-stage arithmetic means having a first switch for outputting, an internal memory for storing an output of the pre-stage arithmetic unit, a second multiplier for multiplying the internal memory by the reference function memory output, and I
It is characterized by comprising an IFFT arithmetic unit for performing an FFT operation, and a post-stage arithmetic unit having a second switch for switching the internal memory output to the IFFT arithmetic unit and the second multiplier for output.

The FFT calculator has first and second FFT calculators that receive input data and perform FFT calculations, respectively. The first FFT calculator is an FFT for the first multiplier. The calculation result is output, and the first switch switches the output of the first multiplier and the output of the second FFT calculator to output them to the internal memory.
The FT calculator inputs the data in the internal memory to the IFFT
It has a first IFFT arithmetic unit for performing an arithmetic operation and a second IFFT arithmetic unit for performing an IFFT arithmetic operation by inputting the output of the second multiplier, and the second switch switches the data in the internal memory. And outputs to the first IFFT and the second multiplier.

The first switch is provided between the FFT calculator and the first multiplier, alternately outputs the output of the FFT calculator to the internal memory and the first multiplier, and at the same time, outputs the first switch. The second switch is located between the second multiplier and the IFFT calculator, and alternately outputs the internal memory output and the output of the second multiplier to the IFFT calculator.

The input data storage means inputs data having a range direction and an azimuth direction of the synthetic aperture radar, and the compression processing means performs range compression processing means for compressing the data in the range direction and compression in the azimuth direction. It is characterized by being at least one of the azimuth compression processing means for performing.

[0016]

[0017]

[0018]

In the signal processing apparatus of the present invention, the pre-stage arithmetic unit and the post-stage arithmetic unit are respectively provided with multipliers for performing the arithmetic operation with the reference function. Can be multiplied with. By alternately switching the multiplication with the reference function between the pre-stage arithmetic unit and the post-stage arithmetic unit, the waiting time of the FFT arithmetic unit and the IFFT arithmetic unit can be reduced and high-speed compression processing can be performed.

Further, according to the present invention, the first and second FFT calculators and the first and second IFFT calculators are provided,
A high-speed compression process is performed by switching these four arithmetic units with a switch.

Further, in the present invention, the connection between the FFT calculator and the first multiplier is switched by the first switch. In addition, the connection between the IFFT calculator and the second multiplier is the second
Switch with the switch.

Further, in the present invention, the compression processing in the range direction and the azimuth direction of the synthetic aperture radar is executed by the above-mentioned compression processing means to speed up the compression processing.

[0022]

[0023]

[0024]

【Example】

Example 1. In this embodiment, an embodiment for speeding up the range compression processing means provided in a signal processing device of a high resolution radar such as a synthetic aperture radar will be described. Conventionally, range compression processing has been performed in the order of FFT calculation processing, multiplication processing with an azimuth reference function, and IFFT calculation processing. Range compression processing means in this embodiment,
Two series of dedicated hardware, that is, an FFT calculator, a reference function memory, a multiplier, and an IFFT calculator are installed in parallel, and these two series are switched at a predetermined time to accelerate the range compression processing.

FIG. 1 is a block diagram of the range compression processing means in this embodiment. In the figure, 9
Is a pre-stage arithmetic means, and 10 is an internal memory. The internal memory 10 is a two-port memory that can independently write to and read from the memory. 11 is a post-stage arithmetic means, 36
Is a first pre-stage arithmetic unit that performs FFT computation, multiplication of the FFT computation result and the range reference function in the pre-stage computing means 9. 31a is an FFT in the first front-stage arithmetic unit 36.
A first FFT calculator for performing calculation, 32a is a range reference function memory for holding a range reference function as data, 33
a is a first multiplier that multiplies the output of the first FFT calculator 31a and the range reference function. 37 is the pre-stage calculation means 9
In the above, it is a second pre-stage arithmetic unit that performs only FFT arithmetic. Reference numeral 31b is a second FFT calculator that performs an FFT calculation in the second pre-stage calculator 37. Reference numeral 38 denotes a first rear-stage arithmetic unit that performs only IFFT operation in the rear-stage arithmetic unit 11, and 34a denotes a first rear-stage arithmetic unit 38.
It is a first IFFT calculator that performs an IFFT calculation. 39
Is a second post-stage arithmetic unit that performs, in the post-stage arithmetic unit 11, multiplication with the range reference function and IFFT arithmetic of the multiplication output. Reference numeral 32b is a range reference function memory that holds the range reference function as data in the second post-stage arithmetic unit 39. The range reference function memory may not be divided into 32a and 32b, and one range reference function memory may be shared. 33b is a second multiplier for multiplying the range reference function by the output of the internal memory 10, and 34b is a second multiplier 33.
It is a second IFFT calculator for performing IFFT calculation of b output. Reference numeral 40 is a second switch for switching the input of the post-stage arithmetic means 11, and 41 is a first switch for switching the output of the front-stage means 9.

In FIG. 1, the first pre-stage arithmetic unit 3
6 and the second pre-stage arithmetic unit 37, the one-dimensional input image data is input and processed, but the output processing result is the first pre-stage arithmetic operation selected by the first switch 41. 1 to the internal memory 1
Output to 0. However, as shown in FIG. 2, a third switch 41a for switching the input of the pre-stage arithmetic means 9 may be added. At this time, the first switch 41 and the third switch 41a are assumed to move together. In this case, one of the first pre-stage arithmetic unit 36 and the second pre-stage arithmetic unit 37 selected by the third switch 41a and the first switch 41 processes the input data, and this is the result. The intermediate data is output to the internal memory 10. Also, FIG.
Then, the first post-stage arithmetic unit 38 and the second post-stage arithmetic unit 39
Are both connected to the output line. However, since only the arithmetic unit selected by the second switch 40 performs arithmetic processing, only the output from the arithmetic unit selected by the second switch 40 is output. Further, as shown in FIG. 2, a fourth switch 40a may be added. The fourth switch 40a and the second switch 40 move together. Alternatively, in FIG. 1, the first switch 41 may be provided at a position where the input of the pre-stage arithmetic means 9 is switched. Also,
The second switch 40 may be provided at a position where the output of the post-stage calculation means 11 is switched.

The data flow of the range compression processing means 2 configured as described above is shown in FIG. The time is divided based on the processing time of the pre-stage arithmetic means 9, and the i-th section is set as the processing section i. In the processing section i, the first switch 41 in the pre-stage arithmetic means 9 selects the first pre-stage arithmetic unit 36. The i-th input one-dimensional input image data i is multiplied by the FFT operation and the range reference function, and the intermediate data i that is the result is output to the internal memory 10.
The internal memory 10 stores the intermediate data i. Further, at the same time that the one-dimensional input image data i is processed by the pre-stage calculation means 9, the internal memory 10 is processed by the processing section i-
The intermediate data i-1 stored in 1 is output to the post-stage arithmetic means 11. In the latter-stage computing means 11, the second switch 40
Selects the second post-stage arithmetic unit 39, and outputs the intermediate data i-1
In the latter-stage arithmetic unit, multiplication with the range reference function and IFF
T calculation is performed, and the resulting one-dimensional range compressed image data i-1 is output.

Next, in the processing section i + 1, in the pre-stage arithmetic means 9, the first switch 41 operates as the second pre-stage arithmetic unit 37.
Select. FF for one-dimensional input image data i + 1
T operation is performed and the intermediate data i + 1 is output to the internal memory 10. The internal memory 10 stores the intermediate data i + 1. Further, the internal memory 10 outputs the intermediate data i to the post-stage arithmetic means 11 simultaneously with the start of the processing of the pre-stage arithmetic means 9. In the post-stage arithmetic means 11, the second switch 40 selects the first post-stage arithmetic unit 38, and I for the intermediate data i.
The FFT operation is performed, and the resulting one-dimensional range compressed image data i is output. Here, the time required for the multiplication with the FFT operation and the range reference function and the time required for the multiplication with the range reference function and the IFFT operation are substantially the same. The time required for FFT calculation and the time required for IFFT are almost the same. Then, the pre-stage calculation means 9
Thus, the time required for processing the one-dimensional input image data and the time required for processing the intermediate data of the preceding section by the post-stage calculation means 11 can be made substantially the same in any processing section. Therefore, by continuously performing the above processing, the processing of the pre-stage arithmetic means 9 and the post-stage arithmetic means 11 can be simultaneously performed within one processing section,
Range compression processing can be performed on continuous one-dimensional input image data. FIG. 4 shows a comparison between the time required for the conventional range compression processing and the time required for the range compression processing having the configuration shown in FIG. Since the range compression processing means described in this embodiment can process the input data i and the input data i + 1 in parallel, it is possible to process twice as much input data as in the prior art at the same time.

As described above, the FFT operation performed by the first pre-stage arithmetic unit 36 and the multiplication with the range reference function, the multiplication with the range reference function performed by the second post-stage arithmetic unit 39, and the IFFT operation are the same processing. The second pre-stage arithmetic unit 37 that processes within the section
And the IF performed by the first post-stage arithmetic unit 38.
By switching between the switch 40 and the switch 41 so that the FT operation and the FT operation are processed in the same processing section, the waiting time of the pre-stage arithmetic means and the post-stage arithmetic means can be reduced for each processing zone. Can generate and output data.

Example 2. This embodiment describes azimuth compression processing means. As shown in the conventional example, in the azimuth compression process as well as the range compression process, the FFT calculation process, the multiplication process with the azimuth reference function, and the IFFT calculation process are performed in this order. Therefore, as in the first embodiment, an FFT arithmetic unit, a reference function memory, which is dedicated hardware,
Two series of multipliers and IFFT calculators are installed in parallel, and these two series are switched at a predetermined time to accelerate the azimuth compression processing.

FIG. 5 is a block diagram of the azimuth compression processing means 4 in this embodiment. The main difference between FIG. 5 and FIG. 1 is that the azimuth reference functions 45a and 45b are used instead of the range reference functions 32a and 32b. Further, the switch is the third switch 41a as shown in FIG.
The fourth switch 40a may be added. As described in the above embodiment, the azimuth compression processing means 4 uses the FFT operation performed by the first pre-stage arithmetic unit 36 and the multiplication with the azimuth reference function, and the azimuth reference function performed by the second post-stage arithmetic unit 39. Are processed in the same processing section, and the FFT calculation performed by the second pre-stage arithmetic unit 37 and the IFFT calculation performed by the first post-stage arithmetic unit 38 are processed in the same processing section. By switching between the second switch 40 and the first switch 41, the waiting time of the pre-stage arithmetic means and the post-stage arithmetic means can be reduced for each processing section, so that one-dimensional azimuth compressed image data can be generated and output in real time. .

Example 3. In this embodiment, an example in which the same result as that of the range compression processing means described in the first embodiment is realized with a smaller hardware configuration will be described.

FIG. 6 is a block diagram of the range compression processing means of this embodiment. Reference numeral 2 is a range compression processing means.
The range compression processing 2 is performed by the pre-stage arithmetic means 9 and the post-stage arithmetic means 1.
1, a range reference function memory 52, and an internal memory 10. The pre-stage arithmetic means 9 includes an FFT arithmetic unit 51, a first multiplier 33a, and a first switch 41. The first switch 41 is provided between the FFT calculator 51 and the first multiplier 33a, and outputs the output of the FFT calculator 51 to the internal memory 10 or outputs it to the first multiplier 33a. ,
They are switched alternately. The second-stage arithmetic unit 11 includes a second multiplier 33b, a second switch 40, and an IFFT arithmetic unit 54. The second switch 40 is provided between the second multiplier 33b and the IFFT calculator 54, and has the internal memory 1
The output of 0 and the output of the second multiplier 33b are alternately IFF
Output to the T calculator. The range reference function memory 52 is referred to by the first multiplier 33a and the second multiplier 33b.

FIG. 7 shows an example in which the switch of the range compression processing means 2 in FIG. 6 has the same function, but the switch is installed at a different position. In FIG. 7, the first switch 41 is placed in the pre-stage arithmetic means 9 and is connected to the first multiplier 33a.
And the internal memory 10. First switch 41
Is the output from the FFT calculator 51 and the first multiplier 33a.
And the output from are switched alternately. Second switch 40
Is placed in the post-stage arithmetic means 11, and is connected to the internal memory 10 and the second memory.
It is located between the multipliers 33b of. Second switch 40
Is for switching the output from the internal memory 10 to the second multiplier 33b or the IFFT calculator 54.

FIG. 8 shows another example of how to hold the switches of the range compression processing means 2. In addition to the first switch 41 and the second switch 40, a third switch 41a and a fourth switch 40a are provided. The first switch 41 and the third switch 41a are provided in the pre-stage arithmetic means 9, and both switches are located in front of and behind the first multiplier 33a. Further, the first switch 41 and the third switch 41a move in synchronization. Second switch 40 and fourth switch 40
a is provided in the post-stage arithmetic means 11, and both switches are located in front of and behind the second multiplier 33b. Further, the fourth switch 40a and the second switch 40 move in synchronization.

The data flow of the range compression processing means 2 of this embodiment will be described with reference to FIGS. 6 and 3. Processing section i
At this time, in the pre-stage arithmetic means 9, the first switch 41 selects the first multiplier 33a. For the i-th one-dimensional input image data i, the FFT operation and the range reference function are multiplied, and the resulting intermediate data i is output to the internal memory 10. The internal memory 10 stores the intermediate data i. Further, at the same time when the processing for the one-dimensional input image data i is started by the pre-stage calculation means 9, the internal memory 10 stores the intermediate data i-1 stored in the processing section i-1.
Is output to the post-stage calculation means 11. In the post-stage arithmetic means 11, the second switch 40 selects the IFFT arithmetic unit 54, performs multiplication with the range reference function and IFFT arithmetic on the intermediate data i-1, and outputs the result, which is a one-dimensional range compressed image. The data i-1 is output. Next, processing section i + 1
At this time, in the pre-stage processing means 9, the first switch 41 selects the output to the internal memory 10. The pre-stage calculation means 9 is
The FFT operation is performed on the one-dimensional input image data i + 1, and the intermediate data i + 1 is output to the internal memory 10. The internal memory 10 stores the intermediate data i + 1. Also,
Simultaneously with the start of the processing of the pre-stage arithmetic means 9, the internal memory 10
Outputs the intermediate data i to the post-stage arithmetic means 11. In the post-stage arithmetic means 11, the second switch 40 connects the output from the internal memory 10 to the IFFT arithmetic unit 54. That is,
In the post-stage arithmetic means 11, only IFFT arithmetic processing is performed. In the latter-stage arithmetic means 11, the IF for the intermediate data i
FT operation is performed, and the resulting one-dimensional range compressed image data i is output.

By continuously performing the above processing, the processing of the pre-stage arithmetic means 9 and the post-stage arithmetic means 11 can be simultaneously performed within one processing section, and range compression processing can be performed on continuous one-dimensional input image data. You can As described in the above embodiment, the amount of one-dimensional input image data that is twice as large as that in the conventional range compression process can be processed. In addition, in the range compression processing means 2 in this embodiment, 1
Two FFT calculators, two multipliers, one range reference function memory, one internal memory and one IFFT calculator, by switching between two FFT calculators and multipliers , Range reference function memory, IFF
It is possible to process the same amount of one-dimensional input image data as the range processing means described in the first embodiment having the T calculator and one internal memory. That is, it is possible to perform high-speed range compression processing and reduce hardware costs.

Example 4. FIG. 9 is a block diagram of the azimuth compression processing means used in this embodiment. The azimuth compression processing means 4 in FIG. 9 is obtained by replacing the range reference function memory 52 of the range compression processing means shown in FIG. 6 with an azimuth reference function memory 55. Therefore, even in the azimuth compression processing means 4, one having the same processing capacity as the hardware having two FFT calculators, multipliers, azimuth reference function memories, and IFFT calculators
One FFT calculator, two multipliers, one azimuth reference function memory, one IFFT calculator and one internal memory can be obtained by switching with a switch. That is, it is possible to obtain the azimuth compression processing means capable of processing more data with less hardware.

Example 5. In this embodiment, the method of holding the memory after the range compression processing and the memory means when the range migration processing is not performed in the synthetic aperture radar will be described. FIG. 10 is a block diagram of the synthetic aperture radar in this embodiment. 1a is an input data storage means. The input data storage means 1a stores the input image data of the synthetic aperture radar. Reference numeral 2 is a range compression processing means. Reference numeral 3 is a memory means for storing the range compressed image data output from the range compression processing means 2. Reference numeral 4 is an azimuth compression processing means. An output unit 5 outputs the output image data output from the azimuth compression processing unit.

FIG. 11 is a block diagram of the memory means 3. The memory means 3 includes a writing means 61, a memory 62,
The reading means 63 is provided. The writing unit 61 writes the one-dimensional range compressed image data output from the range compression processing unit 2 in the memory 62. In the memory 62, as R addresses, addresses 1 to 2048 are assigned in the range direction. In the azimuth direction, 1 to 25
The A address of 6 is attached. Reading means 63
When 256 lines of one-dimensional range compressed image data are stored in the memory 62, the stored range compressed image data is divided along the azimuth axis direction,
The dimensional range compressed image data is output to the azimuth compression processing means 4. Here, the size of the memory 62 in the azimuth direction is equal to or larger than the correlation length.

FIG. 12 is a conceptual diagram for explaining a method of storing the one-dimensional range compressed image data in the memory 62. In the signal processing apparatus of the synthetic aperture radar of this embodiment, one input image is 2048 in the range direction and 1024 in the azimuth direction. In FIG. 12, 64 indicates one screen of range compressed image data. The one-dimensional range compressed image data in the range direction will be called a frame. The range-compressed image data 1 screen 64 indicates that, when the input image data of one image is range-compressed, the range compression processing means 2 outputs frames 1024 to 1024. The memory 62 can store 256 frames. Reference numeral 65 is a state of the memory 62 in which the frames 1 to 256 are stored in the memory 62. The frame output from the range compression processing unit 2 is written in the memory 62 by the writing unit 61. When 256 frames are stored in the memory 62,
The reading means 63 divides the data along the azimuth axis direction. The one-dimensional range compressed image data in the azimuth axis direction (hereinafter referred to as column data) is output to the azimuth compression processing means 4. The azimuth compression processing means 4 carries out an FFT operation and an azimuth reference function for one column data, executes an IFFT operation, and outputs one pixel of output image data whose resolution is improved in the azimuth direction to the output means 5. Output. The reading means 63 reads the column data 1, the column data 2, the column data 3, ..., The column data 204 from the memory 62.
Up to 8 are sequentially output to the azimuth compression processing means 4. The azimuth compression processing means 4 processes the 2048 column data one after another. When the read means 63 outputs the column data 2048, the write means 61 stores the 257th frame 257 output from the range compression processing means 2 in the memory 6
Overwrite on top of frame 1, which is the oldest frame stored in 2. 66 is a memory 6 in which the frames 2 to 257 are stored in the memory 62.
The state of 2 is shown. The reading means 63 again sets the column data 1
In the order of frame 2 to frame 257 and output to azimuth compression processing means 4. The reading means 63 is
In this way, the column data 1 to the column data 2048 consisting of 256 pixels are output.

FIG. 13 is a diagram showing the flow of processing of the writing means 61. In S41, the counter is set to 1. In S42, one frame output from the range compression processing means 2 is written in the memory 62. As the address when writing to the memory 62, the value of the counter is used as the value of the A address of the memory 62. In S43, 1 is added to the counter. In S44, it is checked whether or not the counter is 257. If no, the process returns to S42 and the next frame is written in the memory 62. If yes in S44, the process proceeds to S45. In S45, the counter is set to 0. In S46, 1 is added to the counter. In S47, it is checked whether or not the counter value is 257. If yes, the counter is set to 1 in S48. Next, S4
Proceed to 9. If NO in S47, the process proceeds to S49. S49 is a reading process. The read process is
It is executed by the reading means 63. The read process will be described later. In S50, the writing unit 61 receives the read end notification from the reading unit 63. In S51, it is checked whether or not there is a frame to be written, and if no, the process ends. If yes, in S52, the counter value is set to the A address of the memory 62, one frame is written, and the process returns to S46. The above is the processing flow of the writing means 61 in the memory means 3. The writing means 61 uses a counter to obtain the A address of the memory 62 into which one frame is written, from the value of the counter.

FIG. 14 is a diagram showing a processing flow of the reading means 63. In S61, the column counter is set to 1. In S62, 256 pixels of column data are read starting from a pixel whose counter value is the A address of the memory 62 and whose column counter value is the R address. For example, the state 66 of the memory 62 in which the frames 2 to 257 are stored in the memory 62 shown in FIG. 12 is taken as an example. The reading unit 63 is passed the counter value = 2 used in the writing unit 61. Reading means 63
To read the column data 1, the counter value = 2 to 2 as the A address of the memory 62, the column counter value =
1 is obtained from 1 as an R address. (A address, R address) = (2,1) is set as one pixel at the head, and reading is sequentially performed in parallel with the azimuth axis until the A address becomes 256, the address is returned to (1,1), and the counter value = Two
Pixels are continuously read out up to the A address before this (in this case, the A address is 1). In this way, 2 of column data 1
Take out 56 pixels.

At S63, 1 is added to the column counter. In S64, it is checked whether the value of the column counter is 2049, and if it is no, the process returns to S62. If yes, S
At 65, a read end notification is issued. The read end notification is passed from the reading unit 63 to the writing unit 61.

As described above, when the writing means 61 stores the frames output from the range compression processing means 2 in the memory 62, and the number of frames corresponding to the correlation length is stored in the memory 62, the reading means 63 causes the reading means 63 to read. The column data parallel to the azimuth direction is read and passed to the azimuth compression processing means 4. The column data is the number 204 corresponding to the length in the range direction.
Eight rows are taken out.

As described with reference to FIG. 13, when one frame is newly rewritten, a new frame cannot be written until the reading unit 63 reads the 2048 column data to the azimuth compression processing unit 4. In the above example, the column data is read and the azimuth compression operation is performed by 2048
The time for the column is shorter than the time for the range compression processing means 2 to process one frame. In this case, the size of the memory 62 in the azimuth direction may be equal to the correlation length, which is 256 in this example. However, there is a case where the time for reading the column data and performing the azimuth compression calculation for the 2048 columns exceeds the time for performing the range compression processing for one frame. At this time, the size of the memory 62 in the azimuth direction is
It is required to be 2 to 3 times the correlation length. The read processing means reads the column data 2048, and while the azimuth compression processing means 4 is performing the azimuth compression processing for each of them, writes the frame output from the range compression processing means 2 to the A address 257 or lower of the memory 62. .

FIG. 15 shows the memory 62 with 256 × 2048.
3 times, that is, 768 × 2048. The correlation length at this time is also 256. Frame 1 to frame 7
Write sequentially from A address 1 to 768 up to 68,
Meanwhile, the reading means 63 reads the column data including 256 pixels in the azimuth direction from the column data 1 to the column data 2048, as described above. The reading means 63 is
When the column data 2048 has been read out, the column data is read out in the same manner with A addresses 2 to 257 as frame targets. When the number of frames output from the range compression processing unit 2 becomes 768 or more, the writing unit 61 again sets the frame 76 to the position where the A address is 1.
Write 9

As described above, in this embodiment, the frame output from the range compression processing means is temporarily stored, the column data having the length of the correlation length parallel to the azimuth axis direction is formed, and the azimuth compression processing means is formed. The memory means for reading is described above. When the range compression processing means finishes processing the number of frames equal to the size of the correlation length, column data can be formed by the memory means and output to the azimuth compression processing means. Therefore, the range compression processing and the azimuth compression processing can be performed in parallel. Can be executed. Therefore, a faster signal processing device can be obtained.

Example 6. The signal processing device of the synthetic aperture radar described in this embodiment is a case where the range migration process is omitted. The conventional signal processing device has a buffer for one image for input image data before the range compression process, and waits for a buffer for one image for the range compressed image data after the range compression process. In this embodiment, a case will be described in which a buffer corresponding to two images provided before and after the range compression processing means is provided as one data storage area. FIG. 16 is a block diagram of the signal processing device of this embodiment. The input image data of the synthetic aperture radar is input to the data storage area 6 and
The data input to the range compression processing means 2 is output. The range-compressed image data that has been range-compressed by the range compression processing means 2 is output to the data storage area 6. Data obtained by dividing the range compressed image data from the data storage area 6 in the size of the correlation length along the azimuth axis direction is output to the azimuth compression processing means 4. The azimuth compression processing means 4 outputs the azimuth-compressed output image to the output means 5. As described above, in the data storage area 6, a state in which input image data is input, a state in which the input data is output to the range compression processing unit 2, and a range compression range-compressed by the range compression processing unit 2 are performed. The state in which the image data is stored and the state in which the range compressed image data is output to the azimuth compression processing are mixed.

For example, the correlation length is 256. 256 in the azimuth direction and 2 in the range direction in the data storage area 6
The 048 memory size is defined as one section. The data storage area 6 is divided into a section for inputting input image data, a section for outputting input image data, a section for storing range compressed image data, and a section for dividing and outputting range compressed image data in the azimuth direction. There is at least one compartment. At this time, the size of the data storage area 6 needs to be at least 256 × 4 = 1024 in the azimuth direction and 2048 in the range direction. Conventionally, the ratio of the size of the data storage area 6 to the buffer corresponding to two images provided before and after the range compression processing means is determined by the size of one image in the azimuth direction and the size of the correlation length.

As described above, by combining the two image buffers provided before and after the range compression processing means into one area, the memory size in the signal processing device can be reduced.

[0052]

As described above, according to the present invention, the FF
A high-speed compression process that does not cause a waiting time in the T calculation and the IFFT calculation can be performed.

Further, according to the present invention, the FFT operation and the I
High-speed compression processing can be performed by duplicating and switching FFT operations.

According to the present invention, the FFT operation and the IFFT can be performed by switching the connection of the multiplier with the switch.
High-speed signal processing that does not cause waiting time for calculation can be performed. Moreover, since it is sufficient to provide one FFI and one IFFT computing unit, respectively, the hardware cost can be reduced.

Further, according to the present invention, the compression processing in the range direction and the azimuth direction of the synthetic aperture radar can be performed at high speed.

[0056]

[0057]

[Brief description of drawings]

FIG. 1 is a block diagram of range compression processing means in an embodiment of the present invention.

FIG. 2 is another block diagram of the range compression processing means in the embodiment of the present invention.

FIG. 3 is a diagram for explaining a temporal processing flow of the range compression processing means of FIG.

FIG. 4 is a diagram showing a comparison of processing time between the range compression processing unit of FIG. 1 and a conventional range compression processing unit.

FIG. 5 is a block diagram of azimuth compression processing means in an embodiment of the present invention.

FIG. 6 is a block diagram of range compression processing means in an embodiment of the present invention.

FIG. 7 is another block diagram of the range compression processing means in the embodiment of the present invention.

FIG. 8 is another block diagram of the range compression processing means in the embodiment of the present invention.

FIG. 9 is a block diagram of azimuth compression processing means in an embodiment of the present invention.

FIG. 10 is a block diagram of a signal processing device according to an embodiment of the present invention.

FIG. 11 is a block diagram of a memory means in an embodiment of the present invention.

FIG. 12 is a diagram for explaining how to store a frame in a memory according to an embodiment of the present invention.

FIG. 13 is a diagram showing a processing flow of a writing means in an embodiment of the present invention.

FIG. 14 is a diagram showing a processing flow of a reading means in an embodiment of the present invention.

FIG. 15 is a diagram showing another example of the memory in the embodiment of the present invention.

FIG. 16 is a block diagram of a signal processing device according to an embodiment of the present invention.

FIG. 17 is a diagram showing a usage example of a radar in a conventional example.

FIG. 18 is a diagram showing a state of reflected pulses of a radar in a conventional example.

FIG. 19 is a block diagram showing a configuration of a conventional signal processing device.

FIG. 20 is a flowchart of an arithmetic processing unit in a conventional signal processing device.

FIG. 21 is a diagram showing one-dimensional distance correction image data along the azimuth axis direction from the distance correction image data in the conventional example.

FIG. 22 is a diagram showing an example in which one-dimensional distance correction image data in the azimuth direction is divided by a correlation length.

[Explanation of symbols]

1 input data memory, 1a input data storage means, 2
Range compression processing means, 3 memory means, 4 azimuth compression processing means, 5 output means, 6 data storage area, 7
Output data memory, 8 arithmetic processing unit, 9 pre-stage arithmetic means, 10 internal memory, 11 post-stage arithmetic means, 31a
First FFT calculator, 31b Second FFT calculator, 3b
2a, 32b, 52 range reference function memory, 33a
1st multiplier, 33b 2nd multiplier, 34a 1st IFFT calculator, 34b 2nd IFFT calculator, 36
First pre-stage arithmetic unit, 37 Second pre-stage arithmetic unit, 38
First post-stage arithmetic unit, 39 Second post-stage arithmetic unit, 40 Second switch, 40a Fourth switch, 41 Second switch, 41a Third switch, 45a, 45b,
55 azimuth reference function memory, 51 FFT calculator,
54 IFFT calculator, 61 writing means, 62, 6
7 memory, 63 read means, 64 range compressed image data 1 screen, 65, 66 state of memory 62.

─────────────────────────────────────────────────── ─── Continuation of front page (72) Hideo Yoshinaga 325 Kamimachiya, Kamakura City, Kanagawa Mitsubishi Electric Corporation Kamakura Factory (56) Reference JP-A-2-243987 (JP, A) JP-A-6 -167567 (JP, A) JP 63-27783 (JP, A) JP 58-22982 (JP, A) JP 58-191979 (JP, A) (58) Fields investigated (Int.Cl) .7, DB name) G01S ⁷ /00-7/42 G01S 13/00-13/95 G06F 17/14 G06T 1/00 H03H 17/02 671

Claims (4)

(57) [Claims] 1. A signal processing device comprising an input data storage means for storing input data, a compression means for compressing and outputting the input data, and an output means for outputting the compressed data. Is a reference function memory that stores a reference function, an FFT calculator that performs an FFT operation on input data,
A first multiplier for multiplying the output of the FFT calculator and the output of the reference function memory, the output of the FFT calculator and the first
A first-stage arithmetic unit having a first switch for switching and outputting the output of the multiplier, an internal memory for storing the output of the former-stage arithmetic unit, and a second unit for multiplying the internal memory by the output of the reference function memory. And a second switch for switching between the internal memory output to the IFFT calculator and the second multiplier to output the IFFT calculator and the second switch. A signal processing device characterized by: 2. The FFT calculator has first and second FFT calculators that respectively receive input data and perform FFT calculations, and the first FFT calculator is the first multiplier. The FFT calculation result is output to, and the first switch is
The IFFT arithmetic unit switches the first multiplier output and the second FFT arithmetic unit output to output to the internal memory, and the IFFT arithmetic unit inputs the data of the internal memory to perform an IFFT arithmetic operation. And the second above
Second IF for performing IFFT operation by inputting the multiplier output of
An FT calculator, and the second switch switches data in the internal memory to switch the first IFFT and the second IFFT.
2. The signal processing device according to claim 1, wherein the signal processing device outputs the signal to the multiplier. 3. The first switch is provided between the FFT calculator and the first multiplier, and outputs the output of the FFT calculator alternately to the internal memory and the first multiplier, and The second switch is located between the second multiplier and the IFFT calculator, and alternately outputs the internal memory output and the output of the second multiplier to the IFFT calculator. 1. The signal processing device according to 1. 4. The input data storage means inputs data having a range direction and an azimuth direction of the synthetic aperture radar, and the compression processing means performs range compression processing means for compressing the data in the range direction and azimuth direction. 4. The signal processing device according to claim 1, wherein the signal processing device is at least one of azimuth compression processing means for performing the compression.