JP3383107B2 - Communication method and communication system - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a communication method for performing communication between a master device and a plurality of processing blocks of a slave device having different processing speeds, and a communication system comprising the master device and the slave device.

[0002]

2. Description of the Related Art When data received by a slave device from a master device is used by a plurality of processing blocks in the slave device, the processing speeds of the plurality of processing blocks may differ from each other.

In such a case, as a communication method between the plurality of processing blocks of the master device and the slave device,
Conventionally, the following three methods have been considered.

The first method is, for example, 3 in the slave device.
Assuming that the processing speeds of the two processing blocks are all different, FIG. 5A shows the clock CK1 supplied from the master device to the slave device, and FIG. 5B shows the data DA1 communicated between the master device and the slave device. In addition, independent communication packets 1a, 1b, 1c are set for the respective processing blocks having different processing speeds, the frequency of the clock CK1 is changed, and communication is performed between the master device and the respective processing blocks.

The second method is similar to the 3 in slave device.
Assuming that the processing speeds of the two processing blocks are all different, FIG. 6A shows the clock CK2 supplied from the master device to the slave device, and FIG. 6B shows the data DA2 communicated between the master device and the slave device. , Each processing block is included in one communication packet 1d,
Periods Pa, Pb, P corresponding to each processing block
In c, directly by the single frequency clock CK2,
Communication is performed with the master device.

[0006] The third method is similar to the third method in the slave device.
Assuming that the processing speeds of the two processing blocks are all different, a buffer memory corresponding to each processing block is provided in the slave device, and the data transfer from the master device to each processing block is shown in FIG. As shown by the clock CK3 supplied to the device and the data DA3 transmitted from the master device to each buffer memory in FIG. 7B, first, the period Px corresponding to each buffer memory in one communication packet 1e is shown. , Py, Pz, a single high-frequency clock CK3 is used to store the data DA3 from the master device in the respective buffer memories, and the data DA3 shown in FIGS.
7D, F, and 7C show clocks CKx, CKy, and CKz used for transmitting data from the respective buffer memories to the respective processing blocks in the slave device.
H indicates the data DAx, DAy, DAz transmitted from the respective buffer memories to the respective processing blocks, and thereafter, in the slave device, a clock CK having a frequency corresponding to the processing speed of the respective processing blocks.
x, CKy, CKz, data DAx, DAy, from each buffer memory to each processing block.
DAz is transmitted.

[0007]

However, according to the first conventional communication method, independent communication packets 1a, 1b, 1c are set for the respective processing blocks having different processing speeds.
Since communication is performed between the master device and each processing block, extra time is required for arbitration between the master device and the slave device, and there is a disadvantage that the master device is locked in communication for a long time.

Further, in the second conventional communication method, since the master device directly communicates with each processing block by the single frequency clock CK2, the frequency of the clock CK2 has the slowest processing speed. It has to be adjusted to the processing speed of the processing block, and there is a drawback that the master device is also restricted in communication for a long time.

Furthermore, the third conventional communication method requires not only a buffer memory corresponding to each processing block in the slave device, but also communication between each buffer memory and each processing block. A circuit for controlling the master device independently and a circuit for generating independent clocks CKx to KCz with respect to the clock CK3 supplied from the master device to the slave device are required, which makes the configuration of the slave device complicated and expensive. There is.

Therefore, an object of the present invention is to provide a master device,
In a communication method for performing communication between a plurality of processing blocks of slave devices having different processing speeds, and in a communication system including the master device and the slave device, the master device is shortened in communication and the slave It is possible to omit the circuit that controls the communication in the slave device in the device independently of the master device, and the circuit that generates an independent clock for the clock supplied from the master device to the slave device. It is to simplify the structure and reduce the cost.

[0011]

(1) A first communication system of the present invention corresponding to the above problem is a communication system including a master device and a slave device, and the slave devices have different processing speeds. The master device includes a plurality of processing blocks, a common clock line, a common data line, and a control circuit for controlling communication of the plurality of processing blocks, and the master device is configured to control the processing of each processing block with respect to the slave device. A clock signal having a frequency corresponding to a processing speed is combined and transmitted, and the control circuit of the slave device selects a processing block having a processing speed corresponding to the frequency of the clock signal from the plurality of processing blocks. According to the above, communication is performed between the master device and the plurality of processing blocks. (2) A second communication system of the present invention, which addresses the above-mentioned problems, is configured to include a master device and a slave device, and the master device sends clock signals of different frequencies to the slave device, The slave device controls communication between a first processing block having no buffer memory, a second processing block having a buffer memory, a common clock line, a common data line, and the first and second processing blocks. When the clock signal has a low frequency, the control circuit selects the first processing block to execute communication with the master device, and when the clock signal has a high frequency, And selecting the second processing block to execute communication with the master device.

(3) A third communication system of the present invention which addresses the above-mentioned problems is a communication system including a master device and a slave device, wherein the master device has a first frequency to the slave device. Or a clock signal of a second frequency higher than the first frequency is selectively supplied, and the slave device includes a first processing block including a first terminal device, a second terminal device and a buffer memory. A second processing block, a common clock line, a common data line, and a control circuit for controlling communication between the first and second processing blocks, wherein the control circuit has a clock signal of the first frequency. In synchronization with the above, the data from the first terminal device is directly transmitted to the master device, and the data received from the second terminal device is stored in the buffer memory. Is 憶, in synchronization with the clock signal of the second frequency supplied from the master device to transmit the data stored in the buffer memory to the master device, characterized in that. (4) A fourth communication system of the present invention, which addresses the above-mentioned problems, is a communication system including a master device and a slave device, wherein the master device sends a clock signal of a first frequency to the slave device. Or selectively supplying a clock signal having a second frequency lower than the first frequency,
The slave device includes a first processing block including a first terminal device and a buffer memory, a second processing block including a second terminal device, a common clock line, a common data line, and the first and second processing blocks. A control circuit for controlling the communication of the two processing blocks, the control circuit causing the buffer memory to receive the data from the master device in synchronization with the clock signal of the first frequency, and the control circuit of the second frequency. The data stored in the buffer memory is transmitted to the first terminal device in synchronization with a clock signal, and the second terminal device is made to directly receive the data from the master device. (5) A fifth communication system according to the present invention, which addresses the above-mentioned problems, includes a master device, a slave device, a clock line for supplying a clock signal from the master device to the slave device, the master device, and the master device. A communication system including a data line for transmitting and receiving data to and from a slave device, wherein the master device has a clock signal of a first frequency or a second frequency higher than the first frequency in the clock line. A clock signal is selectively supplied, and the slave device includes a first processing block including a first terminal device, a second processing block including a second terminal device and a buffer memory, and the first and second processing blocks. And a control circuit for controlling the communication of the master device, wherein the master device has a clock signal of the first frequency in the first period and the second frequency The clock signals are supplied to the clock lines in the order of clock signals, the clock signals of the second frequency and the clock signals of the first frequency are supplied to the clock lines in the order of a second period, and the control circuit In the first period, in synchronization with the clock signal of the first frequency, while directly transmitting the data from the first terminal device to the master device,
Storing the data received from the second terminal device in the buffer memory, transmitting the data stored in the buffer memory to the master device in synchronization with the clock signal of the second frequency, and in the second period. , The second
The buffer memory receives data from the master device in synchronization with a frequency clock signal, and the data stored in the buffer memory is transmitted to the second terminal device in synchronization with the first frequency clock signal. At the same time, the first terminal device is made to directly receive the data from the master device.

(6) The first slave device of the present invention, which addresses the above-mentioned problems, includes a plurality of processing blocks having different processing speeds, a common clock line, and a common data line.
A slave device having a control circuit for controlling communication of the plurality of processing blocks, wherein the control circuit receives a clock signal of a frequency corresponding to a processing speed of each processing block from the master device, From the processing block of 1), communication is performed with the master device by selecting a processing block having a processing speed corresponding to the frequency of the received clock signal. (7) A second slave device according to the present invention, which addresses the above-mentioned problems, includes a first processing block having no buffer memory, a second processing block having a buffer memory, a common clock line, and a common data line. And the first and second
A slave device comprising: a control circuit for controlling communication of a processing block, wherein the control circuit receives a clock signal of a first frequency and a clock signal of a second frequency higher than the first frequency from a master device. , When the received clock signal is at the first frequency, selects the first processing block to execute communication with the master device,
When the received clock signal has the second frequency, the second processing block is selected to perform communication with the master device. (8) A third slave device according to the present invention, which addresses the above-mentioned problems, includes a first processing block including a first terminal device, a second processing block including a second terminal device and a buffer memory, and a common clock line. And a common data line,
A slave device comprising: a control circuit for controlling communication between the first and second processing blocks, wherein
The clock signal of the frequency and the clock signal of the second frequency higher than the first frequency are received, and the control circuit synchronizes the clock signal of the first frequency with the data from the first terminal device. The master device is made to directly transmit the data, and the buffer memory is made to store the data received from the second terminal device, and the data stored in the buffer memory is made to the master device in synchronization with the clock signal of the second frequency. It is characterized by transmitting. (9) According to a fourth slave device of the present invention, which corresponds to the above problem, a first processing block including a first terminal device and a buffer memory, a second processing block including a second terminal device, and a common clock line. And a common data line,
A slave device comprising: a control circuit for controlling communication between the first and second processing blocks, wherein
Receiving a clock signal of a frequency and a clock signal of a second frequency lower than the first frequency, the control circuit
The buffer memory receives data from the master device in synchronization with the clock signal of the first frequency, and the data stored in the buffer memory in synchronization with the clock signal of the second frequency is stored in the first terminal. And transmitting the data from the master device directly to the second terminal device. (10) A fifth slave device of the present invention, which addresses the above-mentioned problems, includes a first processing block including a first terminal device, and a second processing block.
A second processing block including a terminal device and a buffer memory, a common clock line, a common data line,
A slave device comprising: a control circuit for controlling the communication of the first and second processing blocks, wherein a clock signal of a first frequency from a master device and a second frequency higher than the first frequency from a master device. The clock signals are received in the order of the clock signals, the clock signals of the second frequency and the clock signals of the first frequency are received in the order of the second period, and the control circuit receives the clock signals in the order of the first period in the first period. In synchronization with a clock signal of one frequency, the data from the first terminal device is directly transmitted to the master device, and the data received from the second terminal device is stored in the buffer memory, and the data of the second frequency is stored. In synchronization with the clock signal, the data stored in the buffer memory is transmitted to the master device, and the data of the second frequency is transmitted in the second period. The buffer memory receives data from the master device in synchronization with the lock signal, and the data stored in the buffer memory is transmitted to the second terminal device in synchronization with the clock signal of the first frequency. The first terminal device is made to directly receive the data from the master device.

(11) Here, in the first to fifth communication systems, the master device is a game machine body, the slave device is a relay connected to the game machine body, and The communication system can be configured as a game machine system as a plurality of connected terminals. (12) Furthermore, the communication method of the present invention corresponding to the above problem is a communication method of performing communication between a master device and a plurality of processing blocks of a slave device, wherein the plurality of processing blocks have different processing speeds. When a block is included, the master device sends to the slave device a clock signal having a frequency corresponding to the processing speed of each processing block in combination, and the clock signal is sent between the master device and the plurality of processing blocks. The communication is performed at a speed corresponding to each processing block in one communication packet. (13) Furthermore, another communication method of the present invention corresponding to the above problem is a communication method for performing communication between a master device and a plurality of processing blocks of a slave device, wherein the plurality of processing blocks have a processing speed When including different processing blocks, the master device transmits to the slave device a clock signal having a frequency corresponding to the processing speed of each of the processing blocks, and the slave device outputs the clock signals from the plurality of processing blocks. By selecting a processing block having a processing speed corresponding to the frequency of the clock signal, communication is performed between the master device and the plurality of processing blocks at a speed according to each processing block. To do.

In the communication system (slave device thereof) or communication method of the present invention, for example, when three processing blocks having different processing speeds are provided in the slave device, the clock supplied from the master device to the slave device is shown in FIG. 4A. As shown by CK and data DA communicated between the master device and the slave device in FIG. 4B, in one communication packet 1f, the frequency can be changed according to the difference in the processing speed of each processing block. The clock CK allows communication between the master device and each processing block in the periods Pe, Pf, and Pg. Therefore, communication can be performed between the master device and each processing block at an optimum communication speed, and the time during which the master device is restricted by communication can be shortened.
Moreover, the clock supplied to each processing block can be the same as the clock supplied from the master device to the slave device, and communication in the slave device is controlled independently of the master device. A circuit and a circuit that generates an independent clock with respect to the clock supplied from the master device to the slave device are not required, and the configuration of the slave device can be simplified and reduced in cost.

[0016]

BEST MODE FOR CARRYING OUT THE INVENTION An example of the communication method and communication system of the present invention will be described below, taking the case of a home game machine system and the communication method therefor as an example.

FIG. 1 shows an example of the game machine system. In a game machine system 10 as a communication system, a game machine main body 20 outputs a video and a sound as a result of the processing and outputs a video / audio output to an operator. Connected to device 90,
The repeater 30 is connected to the game machine body 20, and the repeater 30
The terminals 41, 42 and 43 are connected to the terminal. The game machine main body 20 constitutes a master device, and the repeater 30 and the terminals 41 to 43 constitute a slave device 50.

In this case, the repeater 30 is connected to the terminal 41.
A buffer memory is not provided therein, and communication is directly performed between the game machine main body 20 which is a master device and the terminal 41 without passing through the buffer memory as described later. The terminal 41 has a relatively low processing speed, and thus the processing block 61 configured by the terminal 41 has a relatively low processing speed.

For the terminals 42 and 43, the FIFO buffer 3 is provided as a buffer memory in the repeater 30.
2, 33 are provided, and the game machine body 2 is a master device.
0 and the terminals 42 and 43, as described later,
Communication is performed via the O buffers 32 and 33. The terminals 42 and 43 have relatively slow processing speeds like the terminal 41, but the communication between the game machine main body 20 and the terminals 42 and 43 is performed via the FIFO buffers 32 and 33, so that the FIFO The processing block 62 composed of the buffer 32 and the terminal 42, and the processing block 63 composed of the FIFO buffer 33 and the terminal 43 are
The processing speed is relatively high when viewed from the game machine main body 20 which is the master device.

In addition to the repeater 30, a processing block 61 is provided.
Control circuit 35 for controlling execution and stop of communication
Is provided.

The game machine body 20 and the repeater 30 are provided with a selection signal line 71, a clock line 72, and a game machine body 20.
Data line 73 for data transmission from the
And a data line 74 for data transmission from the repeater 30 to the game machine body 20.

The selection signal line 71 is connected to the game machine main body 20.
Sends a selection signal for selecting one of the repeaters 30 connected to the game machine body 20,
The selection signal is supplied to the control circuit 35.

The clock line 72 is connected to the game machine main body 20.
, The clock CK whose frequency is changed as described later
Is transmitted, and its clock CK is supplied to the control circuit 35, and at the same time, the respective processing blocks 61, 62, 6
3 is supplied. The control circuit 35 generates a selection signal for selecting the processing blocks 61, 62, 63 from the clock CK and sends it to the processing blocks 61, 62, 63.

The game machine system 10 having the above structure
2 will be described with reference to FIGS. 2 and 3.

Even when data is transmitted from the game machine main body 20 which is the master device to the terminals 41 to 43 of the slave device 50,
Even when data is transmitted from the terminals 41 to 43 to the game machine main body 20, communication is performed in three phases in one communication packet.

That is, the game machine body 20 to the terminal 41
2 to 43, the slave device 50 is selected by the selection signal transmitted from the game machine body 20 to the selection signal line 71. First, in the first phase, as shown by a period P11 in FIG. Game console body 20
The clock CK transmitted from the clock line 72 to the clock line 72 is the high-speed clock CKh, and the processing block 62 is selected by the selection signal from the control circuit 35.
3 is supplied only to the processing block 62, and the data DAb is stored in the FIFO buffer 32 at high speed.

Next, in the second phase, the clock CK from the game machine main body 20 is similarly set to the high-speed clock CKh as shown in the period P12 of FIG.
The processing block 63 is selected by the selection signal from the control circuit 35, and the clock CKh and the data DAc sent from the game machine main body 20 to the data line 73 are supplied only to the processing block 63, so that the data DAc is sent to the FIFO buffer 33 at high speed. Stored in.

Next, in the third phase, as shown in the period P13 of FIG. 2, the clock CK from the game machine main body 20 is set to the low speed clock CKl corresponding to the processing speed of the terminals 41 to 43, and the control is performed. The processing block 61 is selected by the selection signal from the circuit 35, and the clock CKl
The data DAa sent from the game machine main body 20 to the data line 73 is supplied to the processing block 61, and the data DAa is directly sent to the terminal 41 at a low speed.

At the same time, in the third phase, the clock CKl from the game machine main body 20 is also supplied to the processing blocks 62 and 63 by the selection signal from the control circuit 35, and FI is supplied in the periods P11 and P12, respectively.
The data DAb and DAc from the game machine main body 20 stored in the FO buffers 32 and 33 are transmitted from the FIFO buffers 32 and 33 to the terminals 42 and 43 at low speed.

When data is transmitted from the terminals 41 to 43 to the game machine main body 20, the slave device 50 is selected by the selection signal sent from the game machine main body 20 to the selection signal line 71. First, in the first phase, , Fig. 3
The clock CK sent from the game machine main body 20 to the clock line 72 as shown in period P21 of
A low-speed clock CKl corresponding to the processing speed of No. 3 is selected, and the processing block 61 is selected by the selection signal from the control circuit 35, and the clock CKl is processed by the processing block 61.
And the data DBa from the terminal 41 is directly transmitted to the game machine body 20 at a low speed.

At the same time, in the first phase, the clock CKl from the game machine main body 20 is also supplied to the processing blocks 62 and 63 by the selection signal from the control circuit 35, and the data DB from the terminals 42 and 43, respectively.
b and DBc are slowly stored in the FIFO buffers 32 and 33.

Next, in the second phase, the clock CK from the game machine main body 20 is set to the high-speed clock CKh as shown by the period P22 in FIG. 3, and the processing block 62 is generated by the selection signal from the control circuit 35. Is selected, the clock CKh is supplied only to the processing block 62, and the data DBb from the terminal 42 stored in the FIFO buffer 32 in the period P21 is transmitted from the FIFO buffer 32 to the game machine body 20 at high speed.

Next, in the third phase, the clock CK from the game machine main body 20 is similarly set to the high-speed clock CKh as shown in the period P23 of FIG.
The processing block 63 is selected by the selection signal from the control circuit 35, the clock CKh is supplied only to the processing block 63, and the data DBc from the terminal 43 stored in the FIFO buffer 33 in the period P21 is transferred from the FIFO buffer 33 to the game. It is transmitted at high speed to the machine body 20.

Thus, according to the above-mentioned example, the period P
13 or P21, the game machine body 2 which is the master device
0 and the slave device 50 perform low-speed communication, but the periods P11, P12 or the period P13 preceding the period P13.
Since high-speed communication is performed between the game machine main body 20 and the slave device 50 in the periods P22 and P23 after 21.
The time during which the game machine main body 20, which is the master device, is restricted by communication is shortened.

Moreover, in the slave device 50, communication within the slave device 50 is performed by the game machine main body 20 which is the master device.
And a circuit for generating an independent clock with respect to the clock CK supplied from the game machine main body 20 to the slave device 50 are not required, and the configuration of the slave device 50, that is, the configuration of the relay device 30 is not required. Simplifies
The cost can be reduced.

Note that the present invention is not limited to the home-use game machine system and the communication method therefor, but also a communication method for performing communication between a plurality of processing blocks of the master device and the slave device having different processing speeds, and It can be widely applied to a communication system including the master device and the slave device.

[0037]

As described above, according to the present invention, it is possible to shorten the time during which the master device is locked in the communication and to control the communication in the slave device independently of the master device in the slave device. It is not necessary to provide a circuit for generating a clock independent of a clock supplied from the master device to the slave device, and the configuration of the slave device can be simplified and the cost can be reduced.

[Brief description of drawings]

FIG. 1 is a functional block diagram showing an example of a communication method and a communication system of the present invention.

FIG. 2 is a time chart for explaining the operation.

FIG. 3 is a time chart for explaining the operation.

FIG. 4 is a diagram for explaining a communication method of the present invention.

FIG. 5 is a diagram showing a first conventional communication method.

FIG. 6 is a diagram showing a second conventional communication method.

FIG. 7 is a diagram showing a third conventional communication method.

[Explanation of symbols]

10 Game console system (communication system) 20 Game console body (master device) 30 repeaters 32,33 FIFO buffer 35 Control circuit 41-43 terminals 50 slave devices 61-63 processing blocks 72 clock lines 73,74 data lines

Claims (13)

(57) [Claims] 1. A communication system comprising a master device and a slave device, wherein the slave device comprises a plurality of processing blocks having different processing speeds, a common clock line, a common data line, and the plurality of processes. And a control circuit for controlling block communication, wherein the master device sends a clock signal having a frequency corresponding to a processing speed of each processing block to the slave device in combination, and the master device controls the slave device. A communication system in which a circuit performs communication between the master device and the plurality of processing blocks by selecting a processing block having a processing speed corresponding to the frequency of the clock signal from the plurality of processing blocks. 2. A master device and a slave device are included, the master device sends clock signals of different frequencies to the slave device, and the slave device has a first process without a buffer memory. A block, a second processing block having a buffer memory, a common clock line, a common data line, and a control circuit for controlling communication between the first and second processing blocks, the control circuit comprising: When the clock signal has a low frequency, the first processing block is selected to perform communication with the master device, and when the clock signal has a high frequency, the second processing block is selected and the master device is selected. A communication system for performing communication with the user. 3. A communication system including a master device and a slave device, wherein the master device provides the slave device with a clock signal of a first frequency or a second signal higher than the first frequency.
A clock signal of a frequency is selectively supplied, and the slave device includes a first processing block including a first terminal device, a second processing block including a second terminal device and a buffer memory, and a common clock line, A common data line and a control circuit that controls communication between the first and second processing blocks are provided, and the control circuit synchronizes with data from the first terminal device in synchronization with the clock signal of the first frequency. Is directly transmitted to the master device, and the data received from the second terminal device is stored in the buffer memory, and the data is stored in the buffer memory in synchronization with the clock signal of the second frequency supplied from the master device. A communication system for transmitting the generated data to the master device. 4. A communication system including a master device and a slave device, wherein the master device provides the slave device with a clock signal of a first frequency or a second frequency lower than the first frequency.
A clock signal of a frequency is selectively supplied, and the slave device includes a first processing block including a first terminal device and a buffer memory, a second processing block including a second terminal device, and a common clock line, A common data line and a control circuit that controls communication between the first and second processing blocks are provided, and the control circuit synchronizes data from the master device with the clock signal of the first frequency. The data stored in the buffer memory is transmitted to the first terminal device in synchronization with the clock signal of the second frequency, and the second terminal device directly receives the data from the master device. Communication system to receive. 5. A master device, a slave device, a clock line for supplying a clock signal from the master device to the slave device, and a data line for transmitting and receiving data between the master device and the slave device. A communication system including:
A clock signal of a frequency or a clock signal of a second frequency higher than the first frequency is selectively supplied, and the slave device includes a first processing block including a first terminal device, a second terminal device, and a buffer memory. And a control circuit for controlling communication between the first and second processing blocks, wherein the master device has a clock signal of the first frequency and a clock of the second frequency in a first period. Supplying clock signals to the clock lines in the order of signals, supplying clock signals to the clock lines in the order of the second frequency clock signal and the first frequency clock signal in a second period, and the control circuit , In the first period, the data from the first terminal device is directly transmitted to the master device in synchronization with a clock signal of a first frequency. In addition to storing the data received from the second terminal device in the buffer memory, causing the data stored in the buffer memory to be transmitted to the master device in synchronization with a clock signal of the second frequency, In the two periods, the buffer memory receives data from the master device in synchronization with the clock signal of the second frequency, and the data stored in the buffer memory is synchronized with the clock signal of the first frequency. A communication system, which causes the second terminal device to transmit the data and causes the first terminal device to directly receive the data from the master device. 6. A plurality of processing blocks having different processing speeds, a common clock line, and a common data line,
A slave device having a control circuit for controlling communication of the plurality of processing blocks, wherein a clock signal having a frequency corresponding to a processing speed of each processing block is received from a master device, From the processing blocks, the slave device that communicates with the master device by selecting a processing block having a processing speed corresponding to the frequency of the received clock signal. 7. A first processing block having no buffer memory, a second processing block having a buffer memory,
A slave device comprising a common clock line, a common data line, and a control circuit for controlling communication between the first and second processing blocks, the clock signal having a first frequency from a master device, and the first frequency. A second higher frequency clock signal, the control circuit selects the first processing block to perform communication with the master device when the received clock signal has the first frequency. A slave device that selects the second processing block and executes communication with the master device when the received clock signal has the second frequency. 8. A first processing block including a first terminal device, a second processing block including a second terminal device and a buffer memory, a common clock line, a common data line, and the first and second processing blocks. A slave device comprising a control circuit for controlling the communication of two processing blocks, wherein the control device receives a clock signal of a first frequency and a clock signal of a second frequency higher than the first frequency from a master device, Synchronizes with the clock signal of the first frequency, transmits the data from the first terminal device directly to the master device, stores the data received from the second terminal device in the buffer memory, Second
A slave device that causes the data stored in the buffer memory to be transmitted to the master device in synchronization with a clock signal of a frequency. 9. A first processing block composed of a first terminal device and a buffer memory, a second processing block composed of a second terminal device, a common clock line, a common data line, and the first and second processing blocks. A slave device comprising: a control circuit for controlling the communication of two processing blocks, wherein a clock signal of a first frequency and a clock signal of a second frequency lower than the first frequency are received from a master device, , The data from the master device is received by the buffer memory in synchronization with the clock signal of the first frequency, and the data stored in the buffer memory is synchronized with the clock signal of the second frequency. A slave device that causes the second terminal device to directly receive the data from the master device while transmitting the data to the terminal device. 10. A first processing block including a first terminal device, a second processing block including a second terminal device and a buffer memory, a common clock line, a common data line, and the first and second processing blocks. A slave device comprising: a control circuit for controlling the communication of two processing blocks, wherein a clock signal of a first frequency and a clock signal of a second frequency higher than the first frequency are in this order from a master device. A clock signal is received, a signal is received in the order of the clock signal of the second frequency and the clock signal of the first frequency in a second period, and the control circuit is a clock signal of the first frequency in the first period. In synchronization with the above, the data from the first terminal device is directly transmitted to the master device, and the buffer memory receives the data from the second terminal device. Data is stored, the data stored in the buffer memory is transmitted to the master device in synchronization with the clock signal of the second frequency, and in the second period, in synchronization with the clock signal of the second frequency. , The data from the master device is received by the buffer memory, the data stored in the buffer memory is transmitted to the second terminal device in synchronization with the clock signal of the first frequency, and the first terminal device is also transmitted. A slave device which causes the master device to directly receive data from the master device. 11. The master device comprises a game machine body, the slave device comprises a repeater connected to the game machine body, and a plurality of terminals connected to the repeater, and the communication system comprises a game. The communication system according to claim 1, wherein the communication system is configured as a machine system. 12. A communication method for performing communication between a master device and a plurality of processing blocks of a slave device, wherein when the plurality of processing blocks include processing blocks having different processing speeds, the master device causes the slave to operate. A clock signal having a frequency corresponding to the processing speed of each of the processing blocks is combined and sent to the device, and each processing block is sent to each device in one communication packet between the master device and the plurality of processing blocks. A communication method that communicates at a corresponding speed. 13. A communication method for performing communication between a master device and a plurality of processing blocks of a slave device, wherein when the plurality of processing blocks include processing blocks having different processing speeds, the master device causes the slave to operate. A clock signal having a frequency corresponding to the processing speed of each of the processing blocks is combined and transmitted to the device, and the slave device outputs a processing block having a processing speed corresponding to the frequency of the clock signal from the plurality of processing blocks. A communication method for performing communication between the master device and the plurality of processing blocks at a speed according to each processing block by selecting the selected one.