JP3383209B2 - PLL frequency synthesizer and electronic tuner - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL frequency synthesizer, and more particularly to a PLL frequency synthesizer capable of setting a frequency division ratio of a programmable divider with a simple structure and an electronic tuner using the same.

[0002]

2. Description of the Related Art The structure of a conventional PLL frequency synthesizer is shown in FIG. In the figure, 5 is a voltage-controlled oscillator (hereinafter, referred to as V) whose frequency is variable according to an input control voltage.
(Referred to as CO), 15 is a programmable divider that divides the signal output from the VCO 5 at a dividing ratio according to the divided data, 17 is a reference oscillator that generates a reference signal,
Reference numeral 16 is a phase comparator that compares the signal output from the programmable divider 15 with the phase of the reference signal output from the reference oscillator 17, and generates a DC voltage according to the phase difference between the two signals, and 18 is a loop filter. , 13 are microcomputers as data generating means for outputting frequency-divided data by an input device (not shown), and 14 is a shift register.

In the PLL frequency synthesizer having the above configuration, the frequency fr output from the reference oscillator 17
Is input to the phase comparator 16, and the output frequency fvco of the VCO 5 is set to 1 / N by the programmable divider 15.
Is compared with the frequency-divided signal and the DC component is extracted by the loop filter 18 and is input to the VCO 5 as a control voltage. The VCO 5 changes its frequency in accordance with the input control voltage and acts so as to match the phase of the signal from the reference oscillator 17, and the output frequency fvco of the VCO 5 stabilizes at a constant value. That is, the output frequency fvco of the VCO in the PLL frequency synthesizer is fvco = N × fr (1). At this time, the frequency division ratio 1 / N in the programmable divider 15 is set in accordance with the frequency division data output from the microcomputer 13 based on the setting operation by the input means (not shown). Therefore, the output frequency fvco of the VCO 5 can be set by changing the frequency division ratio 1 / N of the frequency divider 15.

FIG. 6 shows a conventional super-heterodyne tuner TU using the PLL frequency synthesizer S. This tuner TU is used, for example, for receiving a digitally modulated received signal such as a digital CATV. After the received signal inputted from the input terminal 1 through the filter 7 is amplified by the high frequency amplifier 8, 1 to the frequency conversion unit A, and the high frequency signal input here is converted into the first intermediate frequency by mixing with the oscillation frequency of the first local oscillator 5a in the first frequency mixer 3, and , The first intermediate frequency signal is amplified through the filter 9 and the intermediate frequency amplifier 10 and then sent to the second mixing section 4 of the second frequency conversion section B, where the oscillation of the second local oscillator 5b is generated. The frequency is mixed with the frequency to be converted into the second intermediate frequency, and the filter 11 is converted from the second intermediate frequency signal.
A desired signal is extracted via the output terminal 2 and output from the output terminal 2 via the amplifier 12. As described above, the tuner TU is a so-called double super tehrodyne system tuner that performs frequency conversion in two stages by the first and second frequency conversion units A and B.

Here, the first PLL circuit A1 in the first frequency converter A (constituted by 5 and 15 to 18) and the second PLL circuit B1 in the second frequency converter B are: Both have the same configuration as the PLL circuit a in the PLL frequency synthesizer S. That is, the PLL circuit A shown in FIG.
1, 15a and 15b of B1 are PLL circuits a shown in FIG.
16a and 16b have the same structure as that of
6 and 17a and 17b are 17 and 18a and 18b are 17
Each has the same configuration. Further, each programmable divider 15a, 1 shown in FIG.
5b includes shift registers 14a and 14b as in FIG.
Frequency division ratio data is input from the microcomputer 13 via the, and the programmable dividers 15a and 15b frequency-divide the output signals from the local oscillators 5a and 5b according to the frequency division ratio data. However, the frequency division data input to the programmable dividers 15a and 15b are different, and the frequency division ratio data for creating the channel frequency to be selected is input to the programmable divider 15a in the first frequency conversion unit A. Is
In the programmable divider 15b in the second frequency converter B, the division ratio data for obtaining the second intermediate frequency required for demodulation is set.

[0006]

As described above, in the conventional PLL frequency synthesizer S, since the frequency division ratio of the programmable divider 15 is controlled according to the data from the microcomputer 13,
A data bus for transmitting the frequency division ratio data from the microcomputer 13 is required. Since digital data is transmitted on this data bus, digital noise may be included, and the noise causes the PL noise.
There is a possibility of impairing the performance of a device using the L frequency synthesizer S, such as an electronic tuner.

In particular, when the PLL synthesizer is used for each local oscillator of the double superheterodyne tuner as described above, there is a problem that it takes time from power-on to start of receiving operation. That is, FIG.
In the electronic tuner TU shown in FIG.
The frequency division ratio data is sent to the programmable divider 15b of the frequency conversion unit B, the second PLL circuit B1 is locked at the specified frequency, and then the first PLL circuit A1 of the first frequency conversion unit A is selected. Since the division ratio data for receiving the station frequency is transmitted, there is a problem that the receiving operation takes time. Further, since it is necessary to send the frequency division ratio data to the second PLL circuit each time, there is a problem that a program for creating the data is required and a memory is required accordingly.

The present invention has been made in view of the above-mentioned problems of the prior art. It is not necessary to send the frequency division data from the data generating means such as a microcomputer in setting the fixed frequency division ratio for the frequency dividing circuit, and the power supply is provided. It is an object of the present invention to provide a PLL frequency synthesizer that can eliminate the control data bus as well as a quick time response after being turned on, and an electronic tuner using the PLL frequency synthesizer.

[0009]

The present invention has the following constitution in order to solve the problems of the above-mentioned conventional techniques. That is, the gist of the present invention is a voltage-controlled oscillator that changes the oscillation frequency according to the input control voltage, and a programmable divider that divides the oscillation frequency output from the voltage-controlled oscillator according to the division ratio data. , A reference oscillator for generating a reference signal, and a phase comparison between the reference signal output from the reference oscillator and the signal divided by the programmable divider, and an error signal corresponding to the phase difference between the two signals In a PLL frequency synthesizer including a phase comparator that outputs as a control voltage of a controlled oscillator, a data storage unit that stores one or more preset frequency division ratio data and an arbitrary frequency division ratio data can be output. A programmable divider for generating desired frequency division ratio data in the frequency division ratio data stored in the data generation means and the data storage means. The division ratio data outputted from said data generating means and a fixed mode in which the input and out of the variable mode to enter to the programmable divider, those having a mode selecting means for selecting one mode, the.

[0010] In P LL frequency synthesizer that have a above-described configuration, in a case to output an arbitrary frequency is not set in advance from the voltage controlled oscillator, to select the variable mode by the mode selection means, required for the data generating means Enter the division ratio to obtain the frequency. Then, the data generation means outputs the division ratio data corresponding to the input division ratio, and the programmable divider receiving the division ratio divides the frequency of the signal output from the voltage controlled oscillator based on the division ratio data. To do. When the fixed mode is selected by the mode selection means, the fixed data stored in the data storage means is output to the programmable divider, and the programmable divider divides the signal output from the voltage controlled oscillator according to the input division ratio. Do a lap.

[0011] As the mode selecting means, it would be to configure a single memory formed by storing Jo Tokoro division ratio of the change-over switch to be selectively connected to the programmable divider and a data generating means To be Furthermore <br/>, in fixed mode, it is also possible to provide a memory selection means for selectively connected to the programmable divider a plurality of memory formed by storing different division ratio data, to this structure For example, the required multiple frequencies can be set quickly. Further, each part excluding the mode selecting means and the signal generating means, it is conceivable to collecting Sekika.

Further, first frequency conversion unit to obtain a first intermediate frequency signal and a signal output from the high-frequency signal and a first local oscillation circuit which is received by mixing in the first mixer circuit And a second frequency conversion unit configured to obtain a second intermediate frequency signal by mixing the first intermediate frequency signal and the signal output from the second local oscillation circuit by the second mixing circuit. In a super-heterodyne tuner having the above, the PLL frequency synthesizer is used for controlling the second local oscillation circuit .

[0013] Then, according to the above configuration, the second local oscillation circuit, selecting a second mode of the PLL frequency synthesizer constituting this without performing data transmission between the data generating means It is possible to set a fixed frequency division ratio of the programmable divider, and it is possible to automatically oscillate at a predetermined oscillation frequency after the power is turned on. The setting of the frequency division ratio of the programmable divider of the PLL frequency synthesizer used for the second frequency conversion section, it is also possible to perform fixed mode and variable mode appropriately selected and, only in the fixed mode It is also possible to set it, which can further simplify the configuration.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. 1 is a block diagram showing an embodiment of a PLL frequency synthesizer S1 according to the present invention, FIG. 2 is a block diagram showing a first embodiment of an electronic tuner according to the present invention, and FIG. 3 is an electronic device according to the present invention. FIG. 4 is a block diagram showing a second embodiment of the tuner, and FIG. 4 is a block diagram showing a third embodiment of the present invention. In each of the drawings, the same or corresponding parts as those of the above-described conventional art are designated by the same reference numerals, The details of the explanation are omitted.

As shown in FIG. 1, the PLL frequency synthesizer S1 shown in the first embodiment of the present invention is similar to the conventional PLL frequency synthesizer shown in FIG.
5, programmable divider 15, phase comparator 16,
A PLL circuit a1 including a reference frequency oscillator 17 and a loop filter 18 is provided, and data generating means including a microcomputer 13 and a shift register 14 is provided. However, in this embodiment, a changeover switch (data selection means) 22 is inserted in a line connecting the shift register 14 and the programmable divider 15, and the changeover switch 22 connects and disconnects the shift register 14 and the programmable divider 15. However, this is different from the above-mentioned prior art. Further, in this embodiment, the other parts except the data generating means such as the microcomputer 13 are integrated.

Further, in the first embodiment, a memory 20 for storing a fixed frequency division ratio is provided, and this memory 20 can be connected to and disconnected from the programmable divider 15 by the changeover switch 22. The memory 20 and the shift register 14 are selectively connected to the programmable divider 15 by the changeover switch 22, which is also different from the above-mentioned prior art.

In the PLL frequency synthesizer S1 having the above configuration, in the PLL circuit a1, the signal output from the VCO 5 is divided by the division ratio set by the programmable divider 15, and the divided signal and the reference oscillator 17 are provided. The phase comparison with the signal frequency output from is performed by the phase comparator 16, and the DC voltage according to the phase difference is input as a control voltage to the VCO 5 via the loop filter 18, and the VCO 5 is adjusted according to the DC voltage. The frequency is changed to reduce the phase difference. At this time, as the frequency division data for setting the frequency division ratio of the programmable divider 15, there are two types, namely, the fixed frequency division ratio data stored in the memory 20 and the variable frequency division ratio data transmitted from the microcomputer 13. Yes, each data is selectively input to the programmable divider 15 by switching the changeover switch 22. Here, the data from the microcomputer 13 generally comprises binary serial data corresponding to the frequency division ratio N and a clock, and the serial data is converted into parallel data by the shift register 14.

Assuming that the programmable divider 15 is composed of 14 bits and the fixed division ratio is 1500, the binary data representing 1500 is 0001.
It becomes 0111011100. This data is stored in the memory 20
When the fixed mode is used, the operation unit (not shown) is operated to input a switching signal to the input terminal 21, and the mode changeover switch 22 is set to the fixed mode side, so that the data from the memory 20 is stored. Is output and the frequency division ratio of the programmable divider 15 is set to 1500, and the oscillation frequency corresponding to the frequency division ratio 1500 is obtained from the VCO 5.

Next, when it is desired to freely set the oscillation frequency of the VCO 5, a switching signal is input to the input terminal 21 and the mode selector switch 21 is set to the second mode side. For example, when the frequency division ratio is 1000, the following data is sent from the microcomputer. 000011110
1000 This data is converted into parallel data by the shift register 14 and the programmable divider 15
Is input to the programmable divider 15 and a frequency division ratio of 1000 is set, and an oscillation frequency corresponding to this frequency division ratio is obtained from the VCO 5.

Thus, the PLL in the above embodiment
In the frequency synthesizer S1, when a specific frequency signal is generated from the VCO 5, the frequency division ratio is set based on the frequency division ratio data read from the memory 20. It is not necessary to transmit the division ratio data to the programmable divider 15 via the data bus. For this reason, the possibility that the frequency division ratio data contains digital noise is greatly reduced as compared with the conventional case, and the performance of a device such as a tuner using this is significantly improved. In the above embodiment,
A single memory 20 that stores predetermined frequency division ratio data is provided, and in the fixed mode, a constant frequency division ratio is always set. It is also possible to store data and selectively read out the division ratio data stored in the memories in the fixed mode. In this case, in addition to the mode selecting means, it is necessary to provide the memory selecting means in the fixed mode.

FIG. 2 is a block diagram showing a first embodiment of the electronic tuner TU1 according to the present invention. In FIG. 2, parts that are the same as or correspond to those in the above-described conventional technique are denoted by the same reference numerals, and detailed description thereof will be omitted. The electronic tuner TU1 in this embodiment has an input terminal 1 and an output terminal 2 similarly to the electronic tuner TU shown in the above-mentioned related art.
And a filter 7, a high frequency amplifier 8, a first frequency conversion unit A, a filter 9, an intermediate frequency amplifier 10, a second frequency conversion unit B, a filter 11 and an amplifier 13 in this order. There is.

In the first frequency converter A, the programmable divider 15a is connected to the microcomputer 13 via the shift register 14a. This point is also the same as in the prior art, but this embodiment The memory 20 and the shift register 14b connected to the microcomputer 13 can be selectively connected to the programmable divider 15b of the second frequency conversion unit B in the embodiment by a changeover switch (mode selecting means) 22. This is a significant difference from the prior art. That is, the changeover switch 2
2 shows that when a predetermined switching signal is input to the input terminal 21 by the operator from the operation unit (not shown), the data input terminal of the programmable divider 15b is shifted to the shift register 14b.
Output terminal of the memory 20 or the output terminal of the memory 20. The other configuration is shown in FIG.
This is the same as the conventional technique shown in FIG.

In the electronic tuner TU1 having the above configuration, the high frequency signal input from the input terminal 1 is input to the first mixer circuit 3 of the first frequency converter A through the filter 7 and the amplifier 8. . First local oscillator 5a
Outputs a signal having a frequency corresponding to the high frequency signal desired to be selected, and is mixed with the high frequency signal in the mixer circuit 3 to obtain a first intermediate frequency signal. At this time, the dividing ratio data corresponding to the tuning frequency set by the operator by the input device (not shown) is sent from the microcomputer 13 to the programmable divider 15a of the first frequency converter A via the register 14a. The programmable divider 15a divides the signal from the local oscillator 5a based on the divided data. Then, the first intermediate frequency signal mixed and converted with the output signal of the first local oscillator 5a is passed through the filter 9 and the intermediate frequency amplifier 10 to the second mixer circuit 4 of the second frequency converter B. Sent to. In the second mixer circuit 4, the input first intermediate frequency signal and the output signal from the second local oscillator 5b are mixed and converted into a second intermediate frequency signal.

At this time, the programmable divider 15b of the second frequency converter B is connected to one of the output terminals of the shift register 14b or the memory 20, and the frequency division ratio sent from the one output terminal. Divide according to the data. Since the frequency division ratio optimal for demodulation is set in the memory 20 during normal operation, the operator inputs a mode selection command to the input terminal of the changeover switch 22 and sets the output terminal of the memory 20 to the programmable divider 15b. Connected to. As a result, the frequency division ratio data stored in the memory 20 is input to the programmable divider 15b, and a constant frequency is output from the second local oscillator 5b. Then, the second intermediate frequency signal output from the second frequency conversion unit B is the filter 11
And output from the output terminal 2 via the amplifier 12.

As described above, in this embodiment, since the fixed division ratio data is input to the programmable divider 15b and the data is not transmitted from the microcomputer 13, the data is not transmitted to the programmable divider 15b. It is extremely unlikely that a transmission error will occur, and the response time after power-on can be greatly shortened, and excellent performance as a tuner can be obtained.
Further, a program for transmitting the frequency division ratio data to the second PLL circuit B1 is not necessary, and the memory capacity can be reduced.

By the way, the frequency of the second local oscillator 5b is proportional to the reference frequency, as can be seen from the equation (1). Therefore, depending on the accuracy of the reference frequency, an error may occur in the second local oscillator 5b. May occur. Depending on the application, this error may not be negligible, and the frequency may be corrected by changing the second local oscillation frequency. This is because the changeover switch 21 is set to the variable mode, the shift register 14b and the programmable divider 15b are connected to each other, and the frequency division ratio data corresponding to the correction frequency is sent from the microcomputer 13 to the provider 15b. The frequency is set in 5b.

In the electronic tuner TU1 in the above-described embodiment, the fixed mode and the variable mode can be selected in the second frequency converter B, but in general, the above-mentioned frequency error can be ignored. In many cases, the frequency is not required to be corrected, and in such a case, a constant frequency division ratio is used as in the electronic tuner TU2 according to the second embodiment of the present invention shown in FIG. A fixed divider 27 that divides the frequency may be provided. In FIG. 3, the same or corresponding parts as those of the first embodiment are designated by the same reference numerals. According to this second embodiment, the shift register 1 in the first embodiment is
4b and the connection to the microcomputer 13, the memory 20 and the like can be deleted, and a divider having a simpler and cheaper circuit configuration than the programmable divider 15b can be used as a divider, resulting in a significant cost reduction. It will be possible.

FIG. 4 is a block diagram showing an electronic tuner TU3 according to the third embodiment of the present invention. In FIG. 4, the same or corresponding parts as those of the above-mentioned embodiments are designated by the same reference numerals, and their description will be omitted. Omit the details of. In the third embodiment shown here, while the shift register 14b in the first embodiment is deleted, a plurality of memories (here, two memories are connected to the programmable divider 15b).
Each memory 28, 29 stores different division ratio data, and the connection between the programmable divider 15b and each memory 28, 29 is switched by inputting a switching signal to the input terminal 21 and switching the switch 22. By doing so, it can be selectively performed. Therefore, also in the third embodiment, the mode for setting the frequency division ratio is only the fixed mode as in the second embodiment, but in the fixed mode, the changeover switch 22 selects among the plurality of frequency division ratios. Either one can be selected.

Further, according to the third embodiment, even when the second local oscillation frequency is different depending on the system, it is possible to cope with it and to obtain high versatility. For example, in a CATV application, a frequency in the 500 MHz band is used in a system in the reception frequency band 54 MHz to 550 MHz, and 54 M
In the system of Hz to 750 MHz, the frequency of 900 MHz band is used, and in the case of commonly designing the second PLL circuit B1 in such a different system, one system is used as in the second embodiment. It is not possible to deal with it only by the frequency division ratio, and if the variable mode is provided as in the first embodiment, the cost becomes high. Therefore, in the third embodiment, different frequency division ratio data are stored in the plurality of memories 28 and 29 in the fixed mode, and these data are selectively used.
By providing an intermediate configuration between the first embodiment and the second embodiment, it is possible to support a plurality of systems at low cost.

In the above description, the case where the PLL frequency synthesizer of the present invention is used for an electronic tuner has been described as an example, but the PLL frequency synthesizer according to the present invention can be applied to devices other than the electronic tuner. . Further, in the first frequency conversion unit A in the first to third embodiments of the electronic tuner, the frequency division ratio can be changed to an arbitrary value by the microcomputer 13, so to speak, only in the variable mode. Although the one including the PLL circuit A1 controlled by is used, it is also possible to configure the first frequency converter like the second frequency converter so that the variable mode and the fixed mode can be selected. Further, depending on the receiving device to be applied, it is also possible to use a frequency conversion unit capable of setting one or more frequency division ratios in the first frequency conversion unit, and the electronic tuner according to the present invention is particularly It is not limited to the embodiment. Further, at least one circuit of the local oscillation circuit 5b and the mixer circuit 4 in the first to third embodiments of the electronic tuner and the PLL frequency synthesizer constituting the present invention are integrated to occupy these circuits. By reducing the area, it is possible to suppress the radiation of the high frequency signal, suppress the generation of an unnecessary signal due to the interference between the first local oscillation signal and the second local oscillation signal, or reduce the unnecessary radiation from the tuner.

[0031]

As described above, according to the PLL frequency synthesizer of the present invention, it is not necessary to send the frequency division ratio data from the data generating means such as the microcomputer when setting the fixed frequency division ratio for the divider, so that the power is turned on. The later time response becomes faster, and since the control data bus can be eliminated, the possibility that bus noise is mixed in the frequency division ratio data is reduced. Therefore, according to the electronic tuner using the PLL frequency synthesizer of the present invention, it is possible to realize high performance with an inexpensive configuration, simplify the control program, and reduce the memory. is there.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a PLL frequency synthesizer according to the present invention.

FIG. 2 is a block diagram showing a first embodiment of an electronic tuner according to the present invention.

FIG. 3 is a block diagram showing a second embodiment of an electronic tuner according to the present invention.

FIG. 4 is a block diagram showing a third embodiment of an electronic tuner according to the present invention.

FIG. 5 is a block diagram of a conventional PLL frequency synthesizer.

FIG. 6 is a block diagram of a conventional electronic tuner.

[Explanation of symbols]

1 input terminal 2 output terminals 3 First mixer circuit 4 Second mixer circuit 5,5a, 5b VCO 7, 9, 11 filters 8, 10, 12 amplifier 13 Microcomputer 14, 14a, 14b shift register 15,15a, 15b Programmable divider 16, 16a, 16b Phase comparator 17, 17a, 17b Reference signal oscillator 18, 18a, 18b loop filter 20, 28, 29 memory 21 Input terminal 22 Changeover switch 27 Fixed Divider A First frequency converter A1 PLL circuit B Second frequency converter B1 PLL circuit

─────────────────────────────────────────────────── ─── Continuation of the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H03L ⁷ /06-7/23 H04B 1/26 H03J 5/02

Claims (4)

(57) [Claims] And 1. A voltage controlled oscillator for changing the oscillation frequency according to a control voltage input, a programmable divider for dividing in accordance with the oscillation frequency output from the voltage controlled oscillator to the frequency division ratio data, the reference frequency performs a reference oscillator for generating a signal, a phase comparison between the divided signal reference frequency signal outputted from the reference oscillator and by the programmable divider, said voltage control error signal corresponding to the phase difference between the two signals A PLL frequency synthesizer including a phase comparator for outputting as a control voltage of an oscillator, a data storage unit for storing one or more preset frequency division ratio data, and a frequency error for correcting the frequency error of the reference oscillator. Correction frequency
And possible data generating means outputs a frequency division ratio data corresponding to the number, the fixed mode and to enter the desired frequency division ratio data in the frequency division ratio data stored in the data storage means to the programmable divider wherein among the variable mode the frequency division ratio data outputted from the data generating means is input to the programmable divider, and mode selection means for selecting one mode, comprising a frequency to a reference frequency signal of the reference oscillator Error occurs
If the variable mode is selected,
A PLL frequency synthesizer characterized by correcting a frequency error of a reference oscillator . 2. The mode selecting means comprises a single memory storing a predetermined frequency division ratio and a changeover switch for selectively connecting the data generating means to the programmable divider. PL according to claim 1.
L frequency synthesizer. 3. The memory selection means for selectively connecting a plurality of memories storing different division ratio data to a programmable divider in the fixed mode, according to claim 1 or 2. PLL frequency synthesizer. 4. A received high frequency signal and a first local oscillator circuit.
The signal output from the channel is mixed in the first mixer circuit.
First frequency conversion adapted to obtain a first intermediate frequency signal
And a first local frequency signal and a second local oscillator
The signal output from the vibration circuit is mixed in the second mixing circuit.
Second frequency conversion adapted to obtain a second intermediate frequency signal
Odor of a super-heterodyne system with parts
Te, and characterized in that claims 1 using 3 PLL frequency synthesizer according to any one of the control of the second local oscillation circuit
An electronic tuner to do .