JP3384671B2 - Phase comparator - Google Patents

Description

Description: BACKGROUND OF THE INVENTION [0001] 1. Field of the Invention [0002] The present invention relates to an EFM from a CD.
The present invention relates to a PLL circuit that generates a clock for identifying a signal, and relates to a phase comparator in the PLL circuit. 2. Description of the Related Art Generally, in order to identify an EFM signal reproduced from a CD, a clock synchronized with the EFM signal is generated by a PLL circuit. As shown in FIG. 4, the PLL circuit includes a VCO 1 for generating a clock signal PCK,
A phase comparator 2 that compares the phases of the EFM signal reproduced from D and the clock signal PCK from the VCO 1 to output phase difference signals S1 and S2, and phase difference signals S1 and S2 output from the phase comparator 2. And a charge pump 3 that charges and discharges a low-pass filter (LPF) 4 connected to the subsequent stage. The output of the LPF 4 is supplied to the VCO 1 to change the output frequency of the VCO 1. [0003] Conventionally, in such a PLL circuit, a circuit shown in FIG. That is, in FIG. 5, reference numeral 5 denotes a three-stage D flip-flop 51, 52, 53, a shift register in which an EFM signal from a CD is input to a data terminal D in the first stage, and 6 denotes an input EFM signal and a shift register. 5, an exclusive NOR (EX-NOR) gate for detecting a mismatch with the output signal Q1 of the first stage, and an exclusive OR (7) for detecting a mismatch between the output signals Q2 and Q3 of the second and third stages of the shift register 5 EX-OR) gate,
Reference numeral 8 denotes an inverter for inverting the clock signal PCK from the VCO 1. The clock signal PCK is input to the first and second clock terminals CK of the shift register 5, and the clock inverted by the inverter 8 is applied to the last clock terminal CK. An inverted signal of the signal PCK is input. FIG. 6 is an operation timing chart of this phase comparator. When an EFM signal and a clock signal PCK as shown in FIGS.
6 outputs a detection signal S2 having a constant pulse width of H level corresponding to a half cycle of the clock signal PCK, as shown in FIG. On the other hand, as shown in FIG. 6, the EX-NOR gate 6 sets the pulse width in accordance with the phase difference between the EFM signal and the clock signal PCK on the basis of the L level pulse width for a half cycle of the clock signal PCK. Is output, and an output signal shown in FIG. 6C is generated from the charge pump 3 based on these signals S1 and S2. [0005] In recent years, there has been a great demand for increasing the reproduction speed of CDs, and in order to realize this, the operating speed of the phase comparator must also be increased. In the above-described conventional phase comparator 2, when the operation speed is relatively low, the charge pump 3 surely generates an output signal shown in FIG. However, since the charge pump 3 is configured to charge and discharge the capacitor in the LPF 4, if the operation speed of the phase comparator 2 is increased, the charge and discharge times cannot be ignored. Therefore, the output signal waveform of the charge pump 3 becomes The detection signals S1,
In contrast to S2, as shown in FIG. 6, most of the inclined portion before reaching the fixed value A is occupied. Accordingly, when the phase difference changes in such a state, if the phase difference increases, the signal portion of the constant value A shifts in the direction of increasing the pulse width as shown by the arrow a. Will increase in proportion to the phase difference. However, when the phase difference decreases, the pulse width shifts in the direction of decreasing the pulse width along the inclined portion as shown by the arrow b, and the output of the charge pump 3 decreases without being proportional to the phase difference. That is, as shown in FIG. 7, the relationship between the phase difference and the output of the charge pump has an asymmetric characteristic in the method of increasing the phase difference and in the direction of decreasing the phase difference. I will. According to the present invention, there is provided a frequency divider for dividing a first input signal by １ ／, and a four-stage shifter for inputting an output signal of the frequency divider to a first stage. A register, a first detector for detecting a mismatch between an output signal of a second stage of the shift register and an output signal of the frequency divider, and a mismatch between a third stage and a fourth stage of the shift register. And a second detector for detecting the second input signal as a clock signal and inputting it to the first stage of the shift register, and using an inverted signal of the second input signal as a clock signal at the next stage and subsequent stages of the shift register. This object is achieved by inputting and outputting detection signals of the first and second detectors to a subsequent charge pump. In the present invention, since the pulse width of the detection signal is increased, the output of the charge pump is proportional to the phase difference both when the phase difference increases and when the phase difference decreases.
The lock stability of the PLL is ensured. FIG. 1 is a circuit diagram showing an embodiment of the present invention. An input EFM signal is first expanded by a 1/2 frequency divider 10 to have a cycle twice as long. You. 11, four D flip-flops (D-FF) 111, 112, 1
13 and 114, and the output signal S4 of the 1/2 frequency divider 10 is input to the data terminal D of the D-FF 111 in the first stage. The clock signal PCK from the VCO 1 is input to the clock terminal CK of the D-FF 111 at the first stage, and the inverted signal of the clock signal PCK inverted by the inverter 12 is output from the second to fourth stages of the shift register 11. -Input to the clock terminals CK of the FFs 112 to 114. The output signal S4 of the 1/2 frequency divider 10
EX-NOR gate 13 for detecting a mismatch between output signals Q2 and Q2 of the second stage of shift register 11, and an EX-NOR gate 13 for detecting mismatch between output signals Q3 and Q4 of the third and fourth stages of shift register 11. An OR gate 14 is provided, and the detection signals S5 and S6 of the EX-NOR gate 13 and the EX-OR gate 14 are input to the charge pump 3 in the subsequent stage. FIG. 2 shows an operation timing chart of the phase comparator of FIG. 1, and the operation will be described below with reference to FIG. First, the D-FFs 113 and 114 at the third and fourth stages of the shift register 11 operate using the inverted signal of the clock signal PCK, which is in phase, as a clock.
Since the output signal Q3 of the D-FF 113 at the previous stage is input to the EX-OR gate 14, the EX-OR gate 14 outputs the pulse-like detection signal S6 that is at the H level during the period in which the output signal Q3 does not coincide with the output signal Q4 in FIG. Output as shown. That is, the pulse width of the detection signal S6 is one cycle period from the fall to the fall of the clock signal PCK, and the pulse width is doubled as compared with the conventional FIG. On the other hand, the first-stage D-FF 111 captures the output signal S4 of the 1/2 frequency divider 10 at the rising of the clock signal PCK (FIG. 2D), and the second-stage D-FF 112 outputs the rising of the clock signal PCK. Output signal Q1 of the previous stage at the fall
(Fig. 2E). And EX-NOR gate 1
3 starts outputting an L-level detection signal S5 when the output signal S4 rises or falls to detect a mismatch between the output signal S4 and the output signal Q2, and thereafter the clock signal PCK rises. Next, when the clock signal PCK falls, the output of the L-level signal ends. Therefore, the pulse width of the detection signal S5 is EF
When the rise of the M signal coincides with the fall of the clock signal PCK, it becomes one cycle of the clock signal PCK,
On the basis of this pulse width, when the phase difference increases, the pulse width spreads up to a maximum of 1.5 cycles of the clock signal PCK, and when the phase difference decreases, the pulse width narrows down to a minimum of 0.5 cycles of the clock signal PCK. Therefore, the output of the charge pump 3 is
As shown in FIG. 6, the pulse width is 2 compared to the conventional FIG.
It is enlarged twice. Therefore, when the operation speed of the phase comparator increases, the output of the charge pump 3 has a waveform having a slope similar to that of the related art immediately after rising and falling as shown in FIG. Therefore, the signal portion having the constant value A always follows the inclined portion. Therefore, when the phase difference increases, the arrow a
In the case where the signal portion of the constant value A is widened and the phase difference is reduced as shown by, only the signal portion of the constant value A is narrowed as shown by the arrow b. The output will be proportional to the phase difference. For this reason, as shown in FIG. 3, the relationship between the charge pump output and the phase difference always has a proportional characteristic, and the stability of the PLL lock is ensured. According to the present invention, even when the operation speed of the phase comparator is increased, the stability of the lock in the PLL can be reliably ensured.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit diagram showing an embodiment of the present invention. FIG. 2 is an operation timing chart of the embodiment of the present invention. FIG. 3 is a characteristic diagram illustrating a relationship between a phase difference and a charge pump output in the embodiment of the present invention. FIG. 4 is a block diagram showing a general configuration of a PLL. FIG. 5 is a circuit diagram showing a conventional example of the present invention. FIG. 6 is an operation timing chart of a conventional example of the present invention. FIG. 7 is a characteristic diagram showing a relationship between a phase difference and a charge pump output in a conventional example of the present invention. [Description of Signs] 1 VCO 2 Phase comparator 3 Charge pump 4 LPF 5, 11 Shift register 6, 13 EX-NOR gate 7, 14 EX-OR gate 8, 12 Inverter 10 1/2 frequency divider

Claims (1)

(57) [Claim 1] A frequency divider for dividing a first input signal by １ ／, and a four-stage shift register for inputting an output signal of the frequency divider to a first stage. A first level when the output signal of the second stage of the shift register and the output signal of the frequency divider do not match.
A first detector that outputs an output signal of the shift register, and when the output signals of the third and fourth stages of the shift register do not match.
An output signal of a second level opposite to the first level is output.
A second detector that outputs a second input signal as a clock signal to a first stage of the shift register, and an inverted signal of the second input signal as a clock signal to a subsequent stage of the shift register. Enter the charge
A phase comparator wherein the detection signals of the first and second detectors are output to a subsequent charge pump so that the output of the pump outputs a signal having a constant value .