JP3386293B2 - Method for manufacturing semiconductor integrated circuit device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device manufacturing technique, and more particularly to a complementary MOSFET (CMOS).
A semiconductor integrated circuit device (bipolar-CMOS LS) in which an integrated circuit is composed of an FET and a bipolar transistor.
The present invention relates to a technique effective when applied to I).

[0002]

2. Description of the Related Art High speed and CM of bipolar transistors
In recent years, bipolar-CMOS LSIs that combine the high integration and low power consumption of OSFETs have been used in high-speed memory LS in recent years.
The application to I etc. is increasing.

FIG. 14 shows a bipolar-CMOS SRA.
FIG. 6 is a cross-sectional view showing an example of a diffusion layer structure of a semiconductor substrate used for manufacturing M.

The semiconductor substrate 100 shown in the figure is made of p-type single crystal silicon, and has p-type wells 101, 1 on its main surface.
03 and n-type wells 102 and 104 are provided alternately. The p-type well 101 is provided in the memory array region, and on its main surface, for example, an n-channel type MIS is formed.
An SRAM memory cell including an FET and a load resistance element is formed. p-type well 103 and n-type well 10
2, 104 are provided in the peripheral circuit area around the memory array area. An n-channel MISFET is formed on the main surface of the p-type well 103, a p-channel MISFET is formed on the main surface of the n-type well 102, and an n-type well 104 is formed.
Npn-type bipolar transistors are respectively formed on the main surfaces of the.

The p-type well 101 in the memory array region
A p-type buried layer 105 is provided under the. The p-type buried layer 1 is formed under the p-type well 103 and the n-type wells 102 and 104 in the peripheral circuit region.
07 and n-type buried layers 106 and 108 are provided, respectively. The n-type well 104 and the n-type buried layer 108 therebelow form the collector region of the npn-type bipolar transistor.

The p-type buried layer 10 in the memory array region
An n-type isolation layer 109 is provided under the element 5. At the edge of the memory array region, that is, at the boundary between the memory array region and the peripheral circuit region, the n-type buried layer 110 is adjacent to the p-type buried layer 105, and the n-type buried layer 110 is adjacent to the p-type well 101. Wells 111 are provided respectively, and a p-type buried layer 112 is provided between the n-type buried layer 110 and the n-type well 106 in the peripheral circuit region.
, N-type well 111 and n-type well 10 in the peripheral circuit region
P-type wells 113 are provided between the two. The end of the n-type isolation layer 109 in the memory array region extends to the bottom of the n-type buried layer 110 adjacent to the memory array region.

As described above, the semiconductor substrate 100 has the p-type well 101 in the memory array region and the p-type well 101 below the p-type well 101.
The type buried layer 105 is completely surrounded by an n-type isolation layer 109, an n-type buried layer 110, and an n-type well 111 having a conductivity type different from that of the semiconductor substrate 100, whereby carriers generated in the peripheral circuit are generated. This prevents a problem that a memory cell malfunctions (information inversion) by invading into the p-type well 101 in the memory array region.

Regarding the bipolar-CMOS SRAM having the semiconductor substrate structure as described above, for example, "Hanse / Kenho 374""Ultra High Speed SRAM and 0.7 μm Hi-for Mobile Radio" issued by Hitachi, Ltd. Bi
There is a description in "Research on CMOS process".

[0009]

SUMMARY OF THE INVENTION
Bipolar-CMO using semiconductor substrate as shown in FIG.
As a result of examining the manufacturing process of the SRAM, it was found that there are the following problems.

The semiconductor substrate structure shown in FIG. 14 has the structure shown in FIG.
5 to 24 are formed according to the manufacturing process. In these figures, only the memory array region and the region adjacent thereto (the region where the n-type buried layer 110 is formed) are shown, and the peripheral circuit region is not shown.

First, as shown in FIG. 15, the semiconductor substrate 1
After the surface of No. 00 is thermally oxidized to form the silicon oxide film 114, the silicon nitride film 115 is deposited on the entire surface of the semiconductor substrate 100 by the CVD method, and then the silicon nitride film 115 is etched by using the photoresist 116 as a mask. By patterning the n-type isolation layer (10
The silicon nitride film 115 is left in the region where 9) is formed.

Next, after removing the photoresist 116, the surface of the semiconductor substrate 100 is thermally oxidized to grow a silicon oxide film 114 in a region not covered with the silicon nitride film 115, as shown in FIG. A thick silicon oxide film 114a is formed.

Next, after removing the silicon nitride film 115 by etching, as shown in FIG. 17, an n-type impurity (for example, phosphorus) is ion-implanted into the semiconductor substrate 100 using the thick silicon oxide film 114a as a mask. Then, as shown in FIG. 18, the n-type isolation layer 109 is formed by heat-treating the semiconductor substrate 100 and extending and diffusing this n-type impurity.

Next, after the silicon oxide film 114 and the thick silicon oxide film 114a on the surface of the semiconductor substrate 100 are removed by wet etching, the surface of the semiconductor substrate 100 is thermally oxidized to be newly oxidized, as shown in FIG. A silicon film 117 is formed. Since the silicon oxide film 114 and the silicon oxide film 114a have different thicknesses, a step is generated on the surface of the semiconductor substrate 100 when these films are removed, and the region where the n-type isolation layer 109 is formed is different from other regions (thick oxides). The height difference is higher than that of the region covered with the silicon film 114a.

Next, as shown in FIG. 20, the semiconductor substrate 1
After the silicon nitride film 118 is deposited on the entire surface of the semiconductor device 00 by the CVD method, the silicon nitride film 118 is patterned by etching using the photoresist 119 as a mask to leave the silicon nitride film 118 on the semiconductor substrate 100 in the memory array region. Then, using the photoresist 119 and the silicon nitride film 118 as a mask, an n-type impurity (for example, antimony) is ion-implanted into a region adjacent to the memory array region.

Next, after removing the photoresist 119, as shown in FIG. 21, the semiconductor substrate 100 is heat-treated to extend and diffuse the n-type impurities, so that an n-type region is formed in a region adjacent to the memory array region. The buried layer 110 is formed. By this heat treatment, the silicon oxide film 117 covering the surface of the n-type buried layer 110 grows to become a thick silicon oxide film 117a.

Next, after removing the silicon nitride film 118 covering the surface of the memory array region by etching, as shown in FIG. 22, a p-type impurity (for example, BF) is added to the semiconductor substrate 100 using the thick silicon oxide film 117a as a mask. ₂ ) is ion-implanted, and then, as shown in FIG. 23, the p-type impurity is extended and diffused to form a p-type buried layer 105 on the n-type isolation layer 109.

Next, the silicon oxide film 117 and the thick silicon oxide film 117a on the surface of the semiconductor substrate 100 are removed by wet etching. At this time, since the silicon oxide film 117 and the silicon oxide film 117a have different film thicknesses, as shown in FIG. 24, a step is formed on the surface of the semiconductor substrate 100 and the region where the p-type buried layer 105 is formed, that is, the memory array. The region has a higher step than the region adjacent thereto (the region where the n-type buried layer 110 is formed).

However, a step of forming the n-type isolation layer 109 between the region where the n-type isolation layer 109 extends below the n-type buried layer 110 and the other region ( Since the step is already formed in FIG. 19), after all, between the memory array region and the region of the n-type buried layer 110 where the n-type isolation layer 109 does not extend therebelow. Causes a large step as shown by the arrow in FIG.

Therefore, in the next step, an epitaxial layer is grown on the semiconductor substrate 100, then the p-type well 101 is formed in the epitaxial layer of the memory array region, and the n-type is formed in the upper epitaxial layer of the n-type buried layer 110. When each well 111 is formed, p
A step is formed between the main surface of the type well 101 and the main surface of the n-type well 111, that is, at the end of the memory array region.

As a result, when a memory cell is formed on the main surface of the p-type well 101 in a later step, the film thickness of the photoresist varies between the inside and the end of the memory array region due to the step. , As a result, the characteristics of the memory cells formed inside the memory array region and the memory cells formed at the end of the memory array region vary, resulting in a bit defect at the end of the memory array region. Easier to do.

An object of the present invention is to provide a method for manufacturing a semiconductor integrated circuit device, wherein an isolation layer having a conductivity type different from those of the well is provided below a well in a memory array region via a buried layer having the same conductivity type as the well. It is an object of the present invention to provide a technique capable of reducing the step difference at the end of the memory array region.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0024]

Among the inventions disclosed in the present application, a brief description will be given to the outline of typical ones.
It is as follows.

According to the method of manufacturing a semiconductor integrated circuit device of the present invention, a second conductivity type first semiconductor layer is formed in a first conductivity type semiconductor substrate, and then the second conductivity type first semiconductor layer is formed. After forming the second semiconductor layer of the first conductivity type, a third semiconductor layer of the second conductivity type is formed adjacent to the second semiconductor layer of the first conductivity type, and thereafter, the third semiconductor layer of the first conductivity type is formed. Forming a fourth semiconductor layer of the first conductivity type on the second semiconductor layer, and
A method of manufacturing a semiconductor integrated circuit device, comprising: forming a fifth semiconductor layer of a second conductivity type on a third semiconductor layer of a conductivity type so as to be adjacent to a fourth semiconductor layer of the first conductivity type; It includes (a) to (g).

(A) After forming a first silicon oxide film on the main surface of a semiconductor substrate of the first conductivity type, a first silicon nitride film is formed on the first silicon oxide film, and then,
Patterning the first silicon nitride film by etching using the first photoresist as a mask, (b)
After introducing a second conductivity type impurity into the main surface of the semiconductor substrate using the first photoresist and the first silicon nitride film as a mask, the first photoresist is removed, and then the semiconductor is removed. Thermal oxidation of the main surface of the substrate to grow the first silicon oxide film in the region where the impurities of the second conductivity type are introduced to thicken the film;
(C) After removing the first silicon nitride film, the semiconductor substrate is heat-treated to extend and diffuse the impurities of the second conductivity type to form a first semiconductor layer of the second conductivity type. Step (d), after removing the first silicon oxide film, forming a second silicon oxide film on the main surface of the semiconductor substrate, and then forming a second nitride film on the second silicon oxide film. Patterning the second silicon nitride film by etching using a second photoresist as a mask after forming the silicon film, (e) using the second photoresist and the second silicon nitride film as a mask After introducing impurities of the second conductivity type into the main surface of the semiconductor substrate,
By removing the second photoresist and then heat treating the semiconductor substrate, the impurities of the second conductivity type are elongated and diffused to form a third semiconductor layer of the second conductivity type. The second on the third semiconductor layer of the second conductivity type
The step of growing the silicon oxide film of to increase the film thickness, (f)
After removing the second silicon nitride film, impurities of the first conductivity type are introduced into the main surface of the first semiconductor layer of the second conductivity type by using the thickened second silicon oxide film as a mask. Then, by heat treating the semiconductor substrate,
Forming a second semiconductor layer of the first conductivity type by extending and diffusing the impurities of the first conductivity type, (g) removing the second silicon oxide film, and then forming a second semiconductor layer of the first conductivity type. Forming a fourth semiconductor layer of the first conductivity type on the second semiconductor layer, and forming a fifth semiconductor layer of the second conductivity type on the third semiconductor layer of the second conductivity type.

[0027]

According to the above-mentioned means, in the step (c) of forming the first semiconductor layer of the second conductivity type, the region where the first semiconductor layer is formed has a lower step than other regions, In the step of forming the second semiconductor layer of the first conductivity type on the first semiconductor layer, the region where the second semiconductor layer is formed has a higher step than other areas, and therefore these steps are mutually different. It is possible to reduce the difference in level between the second semiconductor layer of the first conductivity type and the third semiconductor layer of the second conductivity type formed adjacent to the second semiconductor layer of the first conductivity type.

[0028]

Embodiments of the present invention will now be described in detail with reference to the drawings.

This embodiment is an n-channel type MISFET.
And a n-channel MIS
The present invention is applied to a method for manufacturing a bipolar-CMOS LSI which forms an integrated circuit with a peripheral circuit including an FET, a p-channel type MISFET and an npn type bipolar transistor.

First, as shown in FIG. 1, the surface of a semiconductor substrate 1 made of p-type single crystal silicon is thermally oxidized to form a silicon oxide film 2, and then CVD is performed on the entire surface of the semiconductor substrate 1.
The silicon nitride film 3 is deposited by the method.

Next, as shown in FIG. 2, the silicon nitride film 4 is patterned by etching using the photoresist 4 as a mask to remove the silicon nitride film 3 in the memory array region, and then the photoresist 4 and the silicon nitride film are removed. An n-type impurity (for example, phosphorus) is ion-implanted into the main surface of the semiconductor substrate 1 using the film 3 as a mask.

Next, after the photoresist 4 is removed, the surface of the semiconductor substrate 1 is thermally oxidized to grow the silicon oxide film 2 in the region into which the n-type impurity is introduced, as shown in FIG. , A thick silicon oxide film 2a is formed.

Next, after the silicon nitride film 115 is removed by etching, as shown in FIG. 4, the semiconductor substrate 1 is heat-treated to extend and diffuse the n-type impurities, so that the semiconductor in the memory array region is exposed. The n-type isolation layer 5 is formed on the substrate 1.

Next, the thick silicon oxide film 2a covering the upper portion of the n-type isolation layer 5 and the silicon oxide film 2 in the other regions are removed by wet etching, and then, as shown in FIG.
As shown in, the surface of the semiconductor substrate 1 is thermally oxidized to form the silicon oxide film 6. Since the silicon oxide film 2 and the silicon oxide film 2a have different film thicknesses, when these films are removed, a step is formed on the surface of the semiconductor substrate 1 and the region covered with the thick silicon oxide film 2a, that is, the n-type isolation layer. The area where 5 is formed has a lower step than other areas.

Next, as shown in FIG. 6, after depositing a silicon nitride film 7 on the entire surface of the semiconductor substrate 1 by the CVD method, the silicon nitride film 7 is patterned by etching using the photoresist 8 as a mask to form an n-type. The silicon nitride film 7 in the region where the buried layer is to be formed is removed, and then, using the photoresist 8 and the silicon nitride film 7 as a mask, n-type impurities (for example, antimony) are ion-implanted into the main surface of the semiconductor substrate 1.

Next, after the photoresist 8 is removed, as shown in FIG. 7, the surface of the semiconductor substrate 1 is heat-treated to elongate and diffuse the n-type impurities so that the n-type buried layer 9, 10 and 11 are formed. By this heat treatment,
The silicon oxide film 6 covering the surfaces of the n-type buried layers 9, 10, and 11 grows to form a thick silicon oxide film 6.
a.

Next, after removing the silicon nitride film 7 by etching, as shown in FIG. 8, p-type impurities (for example, BF ₂ ) are ion-implanted into the semiconductor substrate 1 using the thick silicon oxide film 6a as a mask. Then, as shown in FIG. 9, the semiconductor substrate 1 is heat-treated to extend and diffuse the p-type impurities, thereby forming the p-type buried layers 12, 13, and 14.

Next, as shown in FIG. 10, the thick silicon oxide film 6a covering the respective surfaces of the n-type buried layers 9, 10 and 11 and the silicon oxide film 6 in other regions are removed by wet etching. . Since the silicon oxide film 6 and the silicon oxide film 6a have different film thicknesses, removal of these films causes a step on the surface of the semiconductor substrate 1.

At this time, paying attention to the boundary portion between the p-type buried layer 12 (memory array region) and the n-type buried layer 9 shown in FIG. 11 (enlarged view of the area circled in FIG. 10), n
Since the thick silicon oxide film 6a was formed on the upper part of the mold burying layer 9 and the silicon oxide film 6 thinner than this was formed on the upper part of the p-type burying layer 12, these films were removed by etching. Then, the p-type buried layer 12 (memory array region) side has a higher step than the n-type buried layer 9 side.

However, when the n-type isolation layer 5 is formed between the region where the n-type isolation layer 5 extends below the n-type buried layer 9 and the other region ( (See FIG. 5), steps are formed so that the former is lower than the latter, so these steps are eventually offset from each other, and the p-type buried layer 12 (memory array region) and
A small step as shown by an arrow in FIG. 11 is formed between the n-type buried layer 9 and a region below which the n-type isolation layer 5 does not extend.

Next, an epitaxial layer is grown on the semiconductor substrate 1, and as shown in FIG. 12, the p-type well 15 and the p-type buried layer 13 are formed on the epitaxial layer above the p-type buried layer 12 in the memory array region. The p-type well 15 is formed in the upper epitaxial layer, and the p-type well 17 is formed in the upper epitaxial layer of the p-type buried layer 14 in the peripheral circuit region. The epitaxial layer above the n-type buried layer 9 adjacent to the memory array region. The n-type well 18 and the epitaxial layer above the n-type buried layers 10 and 11 in the peripheral circuit region.
The mold wells 19 and 20 are formed respectively.

Then, according to a well-known bipolar-CMOS process, a memory cell including an n-channel type MISFET is formed on the main surface of the p-type well 15 in the memory array region, and the n-type well 19 in the peripheral circuit region is formed. A p-channel type MISFET is formed on the main surface, a p-type well 17 is formed on an n-channel type MISFET, and an n-type well 20 is formed on an npn-type bipolar transistor.

According to this embodiment having the above structure, the step between the p-type well 15 in the memory array region and the n-type well 18 adjacent thereto can be reduced.
The characteristic variation of the memory cells formed at the end of the memory array region (p-type well 15) is prevented, and the bipolar-C
The reliability and manufacturing yield of the MOS LSI can be improved.

In the process for realizing the semiconductor substrate structure of this embodiment, since the number of manufacturing steps is the same as the number of manufacturing steps of the conventional method described above, the above effect can be obtained without increasing the number of manufacturing steps. .

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say.

For example, in the above-mentioned embodiment, the n-type isolation layer 5 provided under the memory array region is
As shown in FIG. 13 (a), it may be formed so that the entire circumference thereof extends to the n-type buried layer 9, or as shown in FIG. 13 (b), a part thereof is n-type buried. It may be formed so as to extend to the layer 9. By doing so, the step difference at the end of the memory array region can be further reduced.

In the above-mentioned embodiment, the case where the invention is applied to the bipolar-CMOS memory has been described, but the invention is not limited to this, and the invention can be applied to a logic LSI using the bipolar-CMOS.

Further, the present invention is not limited to the bipolar-CMOS device, and for example, a triple well structure C is used.
It can also be applied to a method for manufacturing a MOS device.

[0049]

The effects obtained by the typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

According to the present invention, the step difference at the end of the region where the isolation layer is formed can be reduced.
The main surface of the semiconductor substrate can be flattened, and characteristic variations of the semiconductor device formed at the end of the region where the isolation layer is formed can be prevented.

Further, according to the present invention, the above effects can be obtained without increasing the number of manufacturing steps.

[Brief description of drawings]

FIG. 1 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 2 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 3 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 4 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 5 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 6 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 7 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 8 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 9 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 10 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device which is an embodiment of the present invention.

11 is an essential part cross-sectional view of a semiconductor substrate showing a part of FIG. 10 in an enlarged manner.

FIG. 12 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device which is an embodiment of the present invention.

13A and 13B are plan views showing an n-type isolation layer of a semiconductor integrated circuit device which is another embodiment of the present invention.

FIG. 14 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device examined by the present inventor.

FIG. 15 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device examined by the present inventor.

FIG. 16 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device examined by the present inventor.

FIG. 17 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device examined by the present inventor.

FIG. 18 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device examined by the present inventor.

FIG. 19 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device examined by the present inventor.

FIG. 20 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device examined by the present inventor.

FIG. 21 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device examined by the present inventor.

FIG. 22 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device examined by the present inventor.

FIG. 23 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device examined by the present inventor.

FIG. 24 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device examined by the present inventor.

[Explanation of symbols]

1 Semiconductor substrate 2 Silicon oxide film 2a Silicon oxide film 3 Silicon nitride film 4 photoresist 5 n-type isolation layer 6 Silicon oxide film 6a Silicon oxide film 7 Silicon nitride film 8 photoresist 9 n-type buried layer 10 n-type buried layer 11 n-type buried layer 12 p-type buried layer 13 p-type buried layer 14 p-type buried layer 15 p-type well 16 p-type well 17 p-type well 18 n-type well 19 n-type well 20 n-type well 100 semiconductor substrate 101 Silicon oxide film 102 n-type well 103 p-type well 104 n-type well 105 p-type buried layer 106 n-type buried layer 107 p-type buried layer 108 n-type buried layer 109 p-type isolation layer 110 n-type buried layer 111 n-type well 112 p-type buried layer 113 p-type buried well 114 Silicon oxide film 114a silicon oxide film 115 Silicon nitride film 116 photoresist 117 Silicon oxide film 118 silicon nitride film 119 photoresist

─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Kazushi Fukuda 5-20-1 Kamimizuhoncho, Kodaira-shi, Tokyo Hitachi, Ltd. Semiconductor Business Division (56) Reference JP-A-6-204417 (JP, A) ) JP 5-198666 (JP, A) JP 4-92466 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 27/06 H01L 21/8249 H01L 27 / 108 H01L 21/8244

Claims (5)

(57) [Claims] 1. A first conductivity type semiconductor layer is formed in a first conductivity type semiconductor substrate, and then a first conductivity type second semiconductor layer is formed on the second conductivity type first semiconductor layer. After forming
A third semiconductor layer of a second conductivity type is formed adjacent to the second semiconductor layer of the first conductivity type, and then a second semiconductor layer of the first conductivity type is formed.
A fourth semiconductor layer of the first conductivity type is formed on the semiconductor layer, and a fourth semiconductor layer of the second conductivity type is adjacent to the third semiconductor layer of the second conductivity type and adjacent to the fourth semiconductor layer of the first conductivity type. 5. A method of manufacturing a semiconductor integrated circuit device for forming a semiconductor layer, comprising:
A method of manufacturing a semiconductor integrated circuit device, comprising the following steps (a) to (g). (A) After forming a first silicon oxide film on the main surface of a first conductivity type semiconductor substrate, a first silicon nitride film is formed on the first silicon oxide film, and then a first silicon oxide film is formed. Patterning the first silicon nitride film by etching using a photoresist as a mask; (b) forming a second mask on the main surface of the semiconductor substrate using the first photoresist and the first silicon nitride film as a mask;
After the conductivity type impurities are introduced, the first photoresist is removed, and then the main surface of the semiconductor substrate is thermally oxidized to remove the first conductivity type impurities in the region where the second conductivity type impurities are introduced. Growing the silicon oxide film to thicken it, (c) after removing the first silicon nitride film, heat-treating the semiconductor substrate to spread and diffuse the impurities of the second conductivity type. And then forming a second conductive type first semiconductor layer, (d) after removing the first silicon oxide film, forming a second silicon oxide film on the main surface of the semiconductor substrate, and Forming a second silicon nitride film on the second silicon oxide film, and then patterning the second silicon nitride film by etching using a second photoresist as a mask, (e) the second Photoresist and And the serial second silicon nitride film as a mask the second to the main surface of said semiconductor body
After introducing the conductivity type impurity, the second photoresist is removed, and then the semiconductor substrate is heat-treated to extend and diffuse the second conductivity type impurity to form the second photoresist.
Forming a conductive type third semiconductor layer and growing the second silicon oxide film on the second conductive type third semiconductor layer to thicken the film; (f) the second silicon nitride After removing the film, impurities of the first conductivity type are introduced into the main surface of the first semiconductor layer of the second conductivity type by using the thickened second silicon oxide film as a mask, and then the semiconductor Heat-treating the substrate to elongate and diffuse the impurities of the first conductivity type to form a second semiconductor layer of the first conductivity type, (g) after removing the second silicon oxide film, A fourth semiconductor layer of the first conductivity type is formed on the second semiconductor layer of the first conductivity type, and a fifth semiconductor layer of the second conductivity type is formed on the third semiconductor layer of the second conductivity type. Process. 2. The epitaxial layer is grown on the semiconductor substrate after forming the second semiconductor layer of the first conductivity type and the third semiconductor layer of the second conductivity type. Of manufacturing a semiconductor integrated circuit device of. 3. The semiconductor integrated circuit device according to claim 1, wherein an end portion of the first semiconductor layer of the second conductivity type extends below the third semiconductor layer of the second conductivity type. Production method. 4. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein a memory cell is formed on the main surface of the fourth semiconductor layer of the first conductivity type. 5. The memory cell is a second conductivity type MISF.
ET is included, and the peripheral circuit is a MIS of the first conductivity type.
5. The method of manufacturing a semiconductor integrated circuit device according to claim 4, wherein the method includes a FET, a second conductivity type MISFET, and a bipolar transistor.