JP3386308B2 - 3-level power converter - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power conversion device (hereinafter, also referred to as a three-level power conversion device) that outputs three levels of voltage for each phase.

[0002]

2. Description of the Related Art FIG. 14 is a main circuit configuration diagram showing a conventional example of this type of three-level power converter. As is clear from the figure, one phase portion of the three-level power converter is a power semiconductor switch 1 (1a to 1d: hereinafter also simply referred to as a switch), a diode 2 (2a to 2f), a capacitor 3 (3).
a, 3b), a load 4, a DC power supply 5 (5a, 5b), and the like. Regarding the operation of FIG.
Description will be made with reference to 17, 18, 19 and 20. Figure 1
The main circuit of No. 4 can output a positive DC voltage by turning on the switch 1a and the switch 1b as shown in the switching pattern 1 of FIG. A zero voltage can be output by turning on 1c and 1c, and a negative voltage can be output by turning on switches 1c and 1d as in switching pattern 3. In addition, in such a switching pattern,
The ON switch is shown with a circle.

In the conventional example, the size judgment as shown in FIG.
By means 11 the carrier wave Vs and the two sets of signal waves Vac^*When
Vbd^*(Vac^*<Vbd^*) Compare the size relationship with
However, as shown in the waveform diagram of FIG. 17, the carrier wave Vs is Vac^*Since
When above, switch 1c is turned on, signal wave Vac^*Is transported
When it is larger than the wave Vs, the switch 1a is turned on, and the carrier wave
Vs is the signal wave Vbd^*Switch when larger than
1d on, signal wave Vbd^*Is above the carrier wave Vs
Signal P to turn on switch 1b_1a’, P_1b’,
P_1c’, P_1d′ Are generated respectively. These on signals
P_1a’, P_1b’, P_1c’, P_1dSwitch on
By switching on, the period of the above three switching patterns
Between the load and the signal wave Vac on the load side.^*And Vbd^*Sum of
Voltage V proportional to _LOutput (fundamental wave component).

By the way, since it takes more time when the switch shifts from the on state to the off state than when it shifts from the off state to the on state, when switching from switching pattern 1 to switching pattern 2, 1
When the ON command is given to the switch 1c at the same time as the OFF command is given to the switch 1a as in 7, there is a period in which both the switch 1a and the switch 1c are turned on. Similarly, when the switch 1c is turned off and the switch 1a is turned on at the same time as the switch 1c is turned off, the switch 1a and the switch 1c both turn on.

When the switch 1a and the switch 1c are turned on at the same time when shifting from the switching pattern 1 to the switching pattern 2 or from the switching pattern 2 to the switching pattern 1, the switch 1a, the switch 1b, the switch 1c and the diode 2f form the capacitor 3a. Is short-circuited, and the switch, diode and capacitor may be damaged by the excessive current flowing through this short-circuit path. Similarly, when the switch 1b and the switch 1d are turned on at the same time when transitioning from the switching pattern 2 to the switching pattern 3 or from the switching pattern 3 to the switching pattern 2,
The capacitor 3b is short-circuited by the switch 1b, the switch 1c, the switch 1d and the diode 2e, and there is a possibility that the switch, the diode and the capacitor are damaged by the excessive current flowing in the short circuit path.

Therefore, in the conventional example, the ON delay means 12 (12a to 12d) is provided as shown in FIG. 16, and as shown in FIG. 18, the ON signals P _1a , P _1b , P _1c and P _1d from 0 to 1 are provided. The timing of changing to is delayed by a certain period Td. That is, when transitioning from the switching pattern 1 to the switching pattern 2 and from the switching pattern 2 to the switching pattern 1, as shown in FIG. 19, the switching pattern 4 that turns off both the switch 1a and the switch 1c and the switching pattern 2 to the switching pattern 3 and switching pattern 3 to switching pattern 2,
As shown in 0, a switching pattern 5 for turning off both the switch 1b and the switch 1d is provided to prevent a short circuit.

[0007]

In the control method as described above, when the three-level power converter outputs a voltage including a DC component, the charging / discharging amounts of both capacitors for dividing the DC voltage into two are different. An imbalance occurs in both capacitor voltages that divide the DC voltage into two. Since the voltage on the DC side is kept constant by the DC voltage source, an overvoltage may occur in the capacitor due to the imbalance of the voltage of both capacitors dividing the DC voltage into two. Further, even switches of the same type have different time and voltage drop required for transition from on to off and from off to on, and capacitors of the same type have different capacities. Therefore, even if the three-level power converter does not include a DC component, an imbalance may occur in both capacitor voltages that divide the DC voltage into two, and the capacitor may become overvoltage. Therefore, an object of the present invention is to make it possible to keep the voltages of both capacitors that divide a DC voltage in two equal.

[0008]

In order to solve such a problem, according to the invention of claim 1, in a power converter which outputs a voltage of three levels for each phase, each of the two capacitors for dividing a DC voltage into two parts. A voltage detecting means for detecting the terminal voltage and a change amount calculating means for calculating the change amount of the short circuit prevention period at the time of switching the switching pattern of the power semiconductor switch are provided to make the short circuit prevention period variable. According to a second aspect of the present invention, in a power conversion device that outputs a voltage of three levels for each phase, a difference voltage detection unit that detects a difference between terminal voltages of both capacitors that divide a DC voltage into two, and a power semiconductor. A change amount calculating means for calculating the change amount of the short circuit prevention period when the switching pattern of the switch is switched is provided, and the short circuit prevention period is made variable.

According to a third aspect of the present invention, in a power converter that outputs three levels of voltage for each phase, voltage detecting means for detecting each terminal voltage of both capacitors dividing a DC voltage into two, and a power semiconductor. A change amount calculating means for calculating the change amount of the short circuit prevention period when the switching pattern of the switch is switched, and a switch selecting means for selecting the power semiconductor switch for extending the short circuit prevention period are provided. According to a fourth aspect of the present invention, in a power conversion device that outputs a voltage of three levels for each phase, a voltage detection unit that detects each terminal voltage of both capacitors that divide a DC voltage into two, and a switching of a power semiconductor switch. A change amount calculating means for calculating a change amount of the short circuit prevention period at the time of pattern switching and a switch selecting means for selecting a power semiconductor switch for shortening the short circuit prevention period are provided.

According to a fifth aspect of the present invention, in a power conversion device that outputs a voltage of three levels for each phase, a difference voltage detection means for detecting a difference between terminal voltages of both capacitors that divide the DC voltage into two. A change amount calculating means for calculating a change amount of the short circuit prevention period at the time of switching the switching pattern of the power semiconductor switch, and a switch selecting means for selecting a power semiconductor switch for extending the short circuit prevention period are provided. According to a sixth aspect of the present invention, in a power conversion device that outputs a voltage of three levels for each phase, a difference voltage detection unit that detects a difference between terminal voltages of both capacitors that divide a DC voltage into two, and a power semiconductor. A change amount calculating means for calculating a change amount of the short-circuit prevention period at the time of switching the switching pattern of the switch and a switch selecting means for selecting a power semiconductor switch for shortening the short-circuit prevention period are provided.

In the invention according to any one of claims 1 to 6, the amount of change in the short-circuit prevention period can be made proportional to the difference between the terminal voltages of the both capacitors (claim 7).
When the difference between the terminal voltages of both capacitors is equal to or less than a certain value, the change amount of the short-circuit prevention period can be zero (the invention of claim 8), or the short-circuit prevention period is It is possible to add lower limit value limiting means for limiting the value so as not to fall below a certain value (invention of claim 9), or add upper limit value limiting means for limiting the short-circuit prevention period not to exceed a reference value. It is possible (claim 10)
Invention).

A) In claims 1 to 3 and 5, when the current flows from the load side into the three-level power converter (hereinafter, the current is positive), and during the period when the positive voltage is output. , There is a period in which the commutation mode transitions as shown in FIG. In mode 1 and mode 2, current flows into the positive DC side via the diodes 2b and 2a. The difference between mode 1 and mode 2 is that the switches in FIG.
In mode 1, the switch 1a is on, whereas in mode 2, the switch 1a is off. On the other hand, in mode 3, the current flows into the neutral point on the DC side via the switch 1c and the diode 2f. Here, if the period of mode 2 is extended by ΔT from the preset time Td, the period of mode 3 is shortened by ΔT. Therefore, the amount of electric charge discharged from the capacitor 3a is smaller than that when the period of mode 2 is Td. , Can be reduced by ΔQ _3a shown in the following equation (1). ΔQ _3a = i × ΔT (1) (i: magnitude of current flowing into three-level power converter) That is, by extending the period of mode 2 by ΔT, the amount of decrease in the voltage of the capacitor 3a is ΔV _3a . It is possible to reduce the voltage of the capacitor 3a,
It can be relatively increased by ΔV _3a as compared with the voltage of b. ΔV _3a = ΔQ _3a / C = i × ΔT / C (2) (C is the capacitance of the capacitor 3a)

When the current is positive and the negative voltage is output, there is a period in which the commutation mode transitions as shown in FIG. In modes 3 and 4, current flows into the neutral point on the DC side via the switch 1c and the diode 2f. The only difference between Mode 3 and Mode 4 is whether or not the switch 1b is on.
The current paths and output voltage levels are the same. On the other hand, in mode 5, the current flows into the DC negative side via the switch 1c and the switch 1d. Here, if the period of mode 4 is extended by ΔT from the preset time Td, the period of mode 5 is shortened by ΔT. Therefore, the amount of electric charge discharged from the capacitor 3b is smaller than that when the period of mode 4 is set to Td. It can be reduced by ΔQ _3b shown in the equation (3). ΔQ _3b = i × ΔT (3) (i: magnitude of current flowing into the three-level power converter) That is, by extending the period of mode 4 by ΔT, the amount of decrease in the voltage of the capacitor 3b is ΔV _3b . It is possible to reduce the voltage of the capacitor 3b,
It can be relatively increased by ΔV _3b as compared with the voltage of a. ΔV _3b = ΔQ _3b / C = i × ΔT / C (4) (C is the capacitance of the capacitor 3b)

On the other hand, when the current flows from the three-level power converter to the load side (hereinafter, it is assumed that the current is negative) and during the period when the negative voltage is output, it is shown in FIG. There is a period during which the mode of such commutation is changed. In modes 6 and 7, current flows from the DC negative side to the load side via the diodes 2d and 2c. The difference between mode 6 and mode 7 is whether or not the switch 1d is on, and the current path and output voltage level are the same. On the other hand, in mode 8, the current flows from the neutral point on the DC side to the load side via the diode 2e and the switch 1b. Therefore, if the period of mode 7 is extended by ΔT from the preset time Td, the period of mode 8 is shortened by ΔT.
Compared with the case of d, the amount of electric charge discharged from the capacitor 3b can be reduced by ΔQ _3b shown in the equation (3).
That is, by extending the period of mode 7 by ΔT, the amount of decrease in the voltage of the capacitor 3b can be reduced by ΔV _3b shown in the equation (4), and the voltage of the capacitor 3b can be compared with the voltage of the capacitor 3a. Can be relatively increased by ΔV _3b .

In the period in which the current is negative and the positive voltage is output, there is a period in which the commutation mode transitions as shown in FIG. In mode 8 and mode 9, the current flows from the neutral point on the DC side to the diode 2e and the switch 1
It flows out to the load side via b. Mode 8 and Mode 9
The difference between and is whether or not the switch 1c is turned on, and the current path and the output voltage level are the same. On the other hand, in mode 10, the current flows from the positive DC side to the load side via the switches 1a and 1b. Here, if the period of mode 9 is extended by ΔT from the preset time Td, the period of mode 10 is shortened by ΔT. Therefore, the amount of electric charge discharged from the capacitor 3a is smaller than that when the period of mode 9 is Td. , And can be reduced by ΔQ _3a shown in the above equation (1).

That is, by extending the period of the mode 9 by ΔT, the amount of decrease in the voltage of the capacitor 3a can be reduced by ΔV _3a shown in the equation (2), and the voltage of the capacitor 3a can be reduced by that of the capacitor 3b. It can be relatively increased by ΔV _3a as compared with the voltage. From the above, it is understood that the period of mode 2 or 9 can be extended to increase the voltage of the capacitor 3a, and the period of mode 4 or 7 can be extended to increase the voltage of the capacitor 3b. This makes it possible to reduce the voltage difference between the capacitors 3a and 3b, whichever is higher.

B) In claims 1, 2, 4 and 6, when the current is positive and during the period in which a positive voltage is output,
There is a period in which the commutation mode transitions as shown in FIG. Since the operation in each mode is the same as the above, the description is omitted. Now, the time Td that is set in advance for the period of mode 2
If it is further reduced by ΔT, the period of mode 3 is extended by ΔT. Therefore, the amount of charge discharged by the capacitor 3a is equal to ΔQ _3a shown in the above equation (1) compared to when the period of mode 2 is Td. Can only increase. That is, by shortening the period of mode 2 by ΔT, the voltage of the capacitor 3a can be relatively reduced by ΔV _{3a as} compared with the voltage of the capacitor 3b. Similarly, in each case where the current is positive and the voltage is negative, the current is negative and the voltage is positive, the current is negative and the voltage is negative, the period of mode 2 or mode 9 is shortened to reduce the voltage of the capacitor 3a. Capacitor 3b
It is understood that the period of mode 4 or mode 7 can be shortened in order to reduce the voltage. That is, the capacitor 3a
It is possible to reduce the voltage difference between both capacitors regardless of whether the voltage is higher or the voltage of the capacitor 3b.

C) Invention of claim 7 In the inventions of claims 1 to 6, the change amount (increase amount, decrease amount) ΔT in the period of the short-circuit prevention mode is expressed by the upper and lower capacitor voltage V as shown in the following equation (5). _By making the amount proportional to the absolute value of the difference between _3a and V _3b , the upper and lower capacitor voltages V _3a and V _3b
There is an effect that can be even. ΔT = K × | V _3a −V _3b | (5) d) Regarding the invention of claim 8, in the inventions of claims 1 to 6, when the difference between the upper and lower capacitor voltages is a certain value or less, the short-circuit prevention period is fixed ( By setting the amount of change to 0), it is possible to suppress an increase in the error between the output voltage of the three-level power conversion device and the output voltage command that occur due to the change in the short-circuit prevention period.

E) By setting the minimum value of the short-circuit prevention period in the invention of claim 9, the short-circuit prevention period does not become a certain value or less regardless of the amount of change in the short-circuit prevention period including shortening or extension, thereby ensuring reliability. Improve sex. f) In the invention of claim 10, by defining the minimum value of the short-circuit prevention period, the short-circuit prevention period does not exceed a certain value regardless of the change amount of the short-circuit prevention period including shortening or extension, and reliability is improved. Let

[0020]

1 is a block diagram showing a first embodiment (corresponding to claims 1 and 3) of the present invention, and FIG. 2 is an operation explanatory diagram thereof. That is, in FIG. 1, the capacitor voltage detecting means 6 (6a, 6b) is added to the conventional main circuit shown in FIG.
16 is added to the conventional control device shown in FIG. 16, and a change amount calculating means 7, a short circuit prevention period extension switch selecting means 9, an adding means 13 (13a to 13d) and the like are added. Therefore, the operation of the same parts as those of the conventional example shown in FIGS. 14 and 16 has already been described, and hence the newly added parts will be mainly described below.

The change amount calculating means 7 is configured to detect the voltage V _3a of the capacitors 3a and 3b detected by the capacitor voltage detecting means 6,
V _3b is input and the amount of change ΔT proportional to the absolute value of the difference
Is output. The short circuit prevention period extension switch selection means 9 is
When the capacitor voltages V _3a , V _3b and the change amount ΔT which is the output of the change amount calculating means 7 are input and the capacitor voltage V _3a is larger than the capacitor voltage V _3b (V _3a > V _3b ),
When the capacitor voltage V _3a is smaller than the capacitor voltage V _3b (V _3a <V _3b ), the amount of change ΔT is output to the adders 13b and 13d, and the amount of change Δ is added to the adders 13a and 13c.
Output T. The short-circuit prevention period extension switch selection means can be replaced by software processing of a microcomputer (also referred to as a microcomputer).

That is, when the capacitor voltage V _3a is smaller than the capacitor voltage V _3b , as shown in FIG. 2, P _1a ,
The period in which P _1c becomes 0 is extended by ΔT, and the switch 1a,
The period in which both the switches 1c are turned off is extended by ΔT. On the contrary, if the capacitor voltage V _3a is equal to the capacitor voltage V
When it is larger than _{3b, the} period in which P _1b and P _1d are 0 is ΔT.
And the period in which both the switch 1b and the switch 1d are turned off is extended by ΔT. Thus, when the capacitor voltage V _3a is higher than the capacitor voltage V _3b , the capacitor voltage V _3b is increased, and when the capacitor voltage V _3a is lower than the capacitor voltage V _3b , the capacitor voltage V _3a is increased.

FIG. 3 is a block diagram showing a second embodiment (corresponding to claims 2 and 5) of the present invention. Instead of the capacitor voltage detecting means 6 shown in FIG.
(18a, 18b) and a voltage detector 19 are provided for the capacitor difference voltage detection means 20, a change amount calculation means 21 is provided instead of the change amount calculation means 7, and a short circuit prevention is provided instead of the short circuit prevention period extension switch selection means 9. The period extension switch selecting means 22 is provided.

The voltage detector 19 in the capacitor difference voltage detecting means 20 detects the voltage difference ΔV between the voltage at the connection point between the capacitors 3a and 3b and the voltage at the connection point between the resistors 18a and 18b. This voltage difference ΔV is represented by a value proportional to the difference between both capacitor voltages, as shown in the following equation. ΔV = V _3b −Ed / 2 = (V _3b −V _3a ) / 2 (6) where V _3a and V _3b are voltage values of the capacitors 3a and 3b,
Ed is the sum of the voltages of the resistors 18a and 18b.

The change amount calculation means 21 receives the ΔV detected by the capacitor difference voltage detection means 20 and outputs a change amount ΔT proportional to the absolute value of ΔV. The short circuit prevention period extension switch selection means 22 receives ΔV and the variation ΔT which is the output of the variation calculation means 21, and when ΔV is negative (when the voltage of the capacitor 3a is larger than the voltage of the capacitor 3b), Amount of change Δ on the adding means 13b and 13d side
When T is output and ΔV is positive (when the voltage of the capacitor 3a is smaller than the voltage of the capacitor 3b), the adding means 13
The change amount ΔT is output to the a and 13c sides. The short circuit prevention period extension switch selecting means can be dealt with by software processing of the microcomputer.

That is, when the voltage of the capacitor 3a is smaller than the voltage of the capacitor 3b, the period in which P _1a and P _1c are 0 is extended by ΔT as shown in FIG. The period in which both the switches 1c are turned off is extended by ΔT. On the contrary, when the capacitor voltage V _3a is larger than the capacitor voltage V _3b , P _1b , P
_The period in which _1d is 0 is extended by ΔT, and the period in which both the switch 1b and the switch 1d are turned off is extended by ΔT.
Thus, when the capacitor voltage V _3a is higher than the capacitor voltage V _3b , the capacitor voltage V _3b is increased, and when the capacitor voltage V _3a is lower than the capacitor voltage V _3b , the capacitor voltage V _3a is increased.

FIG. 4 is a block diagram showing a third embodiment (corresponding to claims 1 and 4) of the present invention, and FIG. 5 is an operation explanatory diagram thereof. This is provided with a short circuit prevention period shortening switch selecting means 10 in place of the short circuit preventing period extension switch selecting means 9 shown in FIG. 1, and a subtracting means 1 in place of the adding means 13.
It can be said that 4 (14a to 14d) is provided. The short circuit prevention period shortening switch selecting means 10 receives the capacitor voltages V _3a and V _3b and the variation ΔT which is the output of the variation calculating means 7, and when the capacitor voltage V _3a is larger than the capacitor voltage V _3b (V _3a > V _3b ), subtraction means 14
The amount of change ΔT is output to the a and 14c sides, and the capacitor voltage V
_{When 3a} is smaller than the capacitor voltage V _3b (V _3a <
V _3b ), and the amount of change ΔT is output to the subtracting means 14b and 14d side.

That is, when the capacitor voltage V _3a is higher than the capacitor voltage V _3b , as shown in FIG. 5, P _1a ,
The period in which P _1c becomes 0 is shortened by ΔT, and the switch 1a,
The period in which both the switches 1c are turned off is shortened by ΔT. On the contrary, if the capacitor voltage V _3a is equal to the capacitor voltage V
When it is smaller than _{3b, the} period in which P _1b and P _1d are 0 is ΔT.
And the period in which both the switch 1b and the switch 1d are turned off is shortened by ΔT. Thus, when the capacitor voltage V _3a is higher than the capacitor voltage V _3b , the capacitor voltage V _3a is reduced, and when the capacitor voltage V _3a is lower than the capacitor voltage V _3b , the capacitor voltage V _3b is reduced. From the above, it is possible to consider Claims 3 and 4 to Claims 1 to 4 by applying a change in the period including extension or reduction of the period for turning off the switch.

FIG. 6 is a block diagram showing a fourth embodiment (corresponding to claims 2 and 6) of the present invention. This is a resistor 18 instead of the capacitor voltage detecting means 6 shown in FIG.
And a capacitor difference voltage detection means 20 including a voltage detector 19 and a short circuit prevention period shortening switch selection means 10
Instead of this, a short circuit prevention period shortening switch selecting means 26 is provided, and instead of the change amount calculating means 7, a change amount calculating means 21 is provided.

The change amount calculation means 21 receives the ΔV detected by the capacitor difference voltage detection means 20 and outputs a change amount ΔT proportional to the absolute value of ΔV. The short-circuit prevention period shortening switch selection means 26 receives ΔV and the change amount ΔT which is the output of the change amount calculation means 21, and when ΔV is negative (when the voltage of the capacitor 3a is larger than the voltage of the capacitor 3b), Amount of change Δ on the subtraction means 14a, 14c side
When T is output and ΔV is positive (when the voltage of the capacitor 3a is smaller than the voltage of the capacitor 3b), the subtracting means 14
The change amount ΔT is output to the b and 14d sides. The short circuit prevention period shortening switch selecting means can be dealt with by software processing of the microcomputer. Thus, as in the case of FIG. 4, the capacitor voltage V _3a is reduced capacitor voltage V _3a during larger capacitor voltage V _3b, capacitor voltage V _3a is at the time smaller capacitor voltage V _3b so as to reduce the capacitor voltage V _3b There is. From the above, it is possible to consider Claims 5 and 6 by considering the change of the period including the extension or the reduction of the period of turning off the switch.

FIG. 7 is a block diagram showing a fifth embodiment of the present invention (corresponding to claims 7 and 8). This is configured by providing a minute period removing unit 15 between the change amount calculating unit 7 and the short circuit prevention period extension switch selecting unit 9 in contrast to, for example, that shown in FIG. Minute period removing means 15
, The change amount ΔT which is the output of the change amount calculating means 7 is input, and this change amount ΔT can be an amount proportional to the difference between the voltages of the upper and lower capacitors. In addition, the minute period removing means 15 responds to the variation ΔT, for example, by varying the variation ΔT.
Is less than or equal to the reference value, “0” is output, and when the change amount ΔT is greater than the reference value, ΔT is output. This allows
When the difference between the voltages of the upper and lower capacitors 3a and 3b is less than or equal to the reference value, the amount of change in the short circuit prevention period can be set to zero.

FIG. 8 is a block diagram showing a sixth embodiment (corresponding to claim 9) of the present invention. This differs from the one shown in FIG. 4, for example, in the subtracting means 14 and the ON delay means 1.
2 and a lower limit value limiting means 16 are provided between the two. The lower limit value limiting means 16 outputs the lower limit setting value when the output value of the subtracting means 14 is less than the lower limit setting value, and outputs the output value of the subtracting means 14 as it is when the output value is equal to or more than the lower limit setting value. As a result, the short-circuit prevention period is secured for a certain period at any time. In FIG. 8, the minute period removing means 15
Although not provided, the minute period removing means 1 is provided between the change amount calculating means 7 and the short circuit prevention period shortening switch selecting means 10.
Of course, 5 can be provided.

FIG. 9 shows a sixth embodiment of the present invention (claim 10).
(Corresponding to) is a configuration diagram showing a form. This is configured by providing an upper limit value limiting means 17 between the addition means 13 and the ON delay means 12 in contrast to the one shown in FIG.
The upper limit value limiting unit 17 outputs the upper limit setting value when the output value of the adding unit 13 is equal to or more than the upper limit setting value, and outputs the output value of the adding unit 13 as it is when the output value is less than the upper limit setting value. This prevents the short circuit prevention period from being exceeded at any time. In FIG. 9, the minute period removing means 15
Although not provided, the minute period removing means 15 is provided between the change amount calculating means 7 and the short circuit prevention period extension switch selecting means 9.
Of course, it is possible to provide. It is of course possible to provide the upper limit value limiting means 17 before or after the lower limit value limiting means 16 in FIG.

[0034]

According to the present invention, the period of the mode for preventing a short circuit is shortened or extended in accordance with the difference between the two capacitor voltages that divide the DC voltage into two, so that both capacitor voltages are kept equal. The advantage is that the overvoltage can be prevented. Further, when the difference between the two capacitor voltages is less than or equal to a certain value, the period of the short-circuit prevention mode is kept constant, or the maximum value of the period of the short-circuit prevention mode is stipulated. There is also an advantage that an increase in the error between the output voltage of the three-level power converter and the output voltage command can be suppressed. Furthermore, by defining the minimum value of the period of the short circuit prevention mode, there is an effect that the short circuit prevention period is secured for a certain period and the short circuit is prevented.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing a first embodiment of the present invention.

FIG. 2 is a time chart for explaining the operation of FIG.

FIG. 3 is a configuration diagram showing a second embodiment of the present invention.

FIG. 4 is a configuration diagram showing a third embodiment of the present invention.

FIG. 5 is a time chart for explaining the operation of FIG.

FIG. 6 is a configuration diagram showing a fourth embodiment of the present invention.

FIG. 7 is a configuration diagram showing a fifth embodiment of the present invention.

FIG. 8 is a configuration diagram showing a sixth embodiment of the present invention.

FIG. 9 is a configuration diagram showing a seventh embodiment of the present invention.

FIG. 10 is an explanatory diagram of operation modes 1 to 3 according to the present invention.

FIG. 11 is an explanatory diagram of operation modes 3 to 5 according to the present invention.

FIG. 12 is an explanatory diagram of operation modes 6 to 8 according to the present invention.

FIG. 13 is an explanatory diagram of operation modes 8 to 10 according to the present invention.

FIG. 14 is a circuit diagram showing a general example of a main circuit of a three-level power converter.

15 is an explanatory diagram of a switching pattern of FIG.

16 is a configuration diagram showing an example of the control device of FIG.

FIG. 17 is an operation explanatory diagram illustrating a control method of the three-level power conversion device.

[Fig. 18] Fig. 18 is an operation explanatory diagram for describing the short-circuit prevention method of the three-level power converter.

19 is an explanatory diagram of switching patterns 1, 4, and 2 of FIG.

20 is an explanatory diagram of switching patterns 2, 5, and 3 of FIG.

[Explanation of symbols]

1a, 1b, 1c, 1d ... Power semiconductor switches (switches) 2a, 2b, 2c, 2d, 2e, 2f ... Diodes, 3a, 3b ... Capacitors, 4 ... Loads, 5a, 5b
... DC voltage source, 6 ... Capacitor voltage detection means, 7, 21
Change amount detecting means, 9, 22 ... Short circuit preventing period extension switch selecting means, 10, 26 ... Short circuit preventing period shortening switch selecting means, 11 ... Large / small judging means, 12 ... ON delay means, 1
3 ... Addition means, 14 ... Subtraction means, 15 ... Minute period removal means, 16 ... Lower limit value limiting means, 17 ... Upper limit value limiting means, 1
8a, 18b ... Resistance, 19 ... Voltage detector, 20 ... Capacitor difference voltage detecting means.

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Claims (10)

(57) [Claims] 1. A power converter for outputting a voltage of three levels for each phase, a voltage detecting means for detecting each terminal voltage of both capacitors dividing a DC voltage into two, and a switching pattern switching of a power semiconductor switch. And a change amount calculating means for calculating a change amount of the short circuit prevention period at a time, and the short circuit prevention period is variable. 2. A power converter which outputs a voltage of three levels for each phase, a differential voltage detecting means for detecting a difference between terminal voltages of both capacitors dividing a DC voltage into two, and a power semiconductor switch. A three-level power conversion device comprising: a change amount calculating means for calculating a change amount of a short circuit prevention period at the time of switching a switching pattern, and changing the short circuit prevention period. 3. A power conversion device for outputting a voltage of three levels for each phase, a voltage detection means for detecting each terminal voltage of both capacitors dividing a DC voltage into two, and a switching pattern switching of a power semiconductor switch. A three-level power conversion device comprising: a change amount calculating means for calculating a change amount of the short-circuit prevention period at a time; and a switch selecting means for selecting a power semiconductor switch for extending the short-circuit prevention period. 4. A power conversion device for outputting a voltage of three levels for each phase, voltage detection means for detecting each terminal voltage of both capacitors dividing a DC voltage into two, and switching pattern switching of a power semiconductor switch. Change level calculating means for calculating the amount of change in the short-circuit prevention period at the time, and switch selecting means for selecting the power semiconductor switch for shortening the short-circuit prevention period are provided. Power converter. 5. A power converter for outputting a voltage of three levels for each phase, a differential voltage detecting means for detecting a difference between terminal voltages of both capacitors dividing a DC voltage into two, and a power semiconductor switch. Three-level power conversion, characterized in that a change amount calculating means for calculating a change amount of the short-circuit prevention period at the time of switching the switching pattern and a switch selecting means for selecting a power semiconductor switch for extending the short-circuit prevention period are provided. apparatus. 6. A power converter for outputting a voltage of three levels for each phase, a differential voltage detecting means for detecting a difference between terminal voltages of both capacitors dividing a direct current voltage into two, and a power semiconductor switch. A three-level power conversion device comprising: a change amount calculating means for calculating a change amount of the short-circuit prevention period at the time of switching a switching pattern; and a switch selecting means for selecting a power semiconductor switch for shortening the short-circuit prevention period. apparatus. 7. The three-level power converter according to claim 1, wherein the amount of change in the short-circuit prevention period is proportional to the difference between the terminal voltages of the both capacitors. 8. The method according to claim 1, wherein the amount of change in the short-circuit prevention period is set to zero when the difference between the terminal voltages of the two capacitors is equal to or less than a certain value. Level power converter. 9. The three-level power conversion device according to claim 1, further comprising a lower limit value limiting means for limiting the short-circuit prevention period so as not to become a predetermined value or less. 10. The three-level power converter according to claim 1, further comprising an upper limit value limiting means for limiting the short-circuit prevention period so as not to exceed a reference value.