JP3386592B2 - Semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a bidirectional 3-terminal thyristor having a Darlington connection structure.

[0002]

2. Description of the Related Art A bidirectional three-terminal thyristor is also called a triac (TRIAC; triode AC switch, trade name). It exhibits bidirectionally symmetric switching characteristics, and can trigger even if the gate signal is unacceptable, making it suitable for AC control. 12 and 13 are block diagrams of a conventional triac. FIG. 12 is composed of two resin-coated blocks. The left side of the figure is the input side block, and the right side is the output side block. Each block has individual semiconductor elements covered with resin such as epoxy resin, and these two semiconductor elements are connected to the circuit board by metal wiring and used as one semiconductor device (triac device). . The semiconductor element on the left side is the photocoupler 2, which includes the light emitting diode 22 and the phototriac 23.
And is covered with the resin sealing body 21.

The photocoupler 2 has input terminals T1 and T2.
And output terminals T3 and T4, the dV / dt ((dV / dt) c) withstanding capacity during commutation between the output terminals is 10 V / μ.
There are more than s. The semiconductor element on the right side is the power triac (TRIAC) 1 and the output terminal T of the photocoupler 2.
4 is connected to the input (gate) end T5 of the triac 1, and the output end T3 of the photocoupler 2 is connected to the output end T6 of the triac 1 by the metal wiring of the circuit board. Between the output terminals T6 and T7 of the triac 1 (dV
/ Dt) c tolerance is almost equal to that of the photocoupler 2, and 10
V / μs or more. The power triac 1 is covered with a resin sealing body 11 made of epoxy resin or the like.

In FIG. 13, two semiconductor elements are resin-sealed in one block. The input side semiconductor element is composed of a photocoupler 2 and is sealed in a transparent resin sealing body 24. The output-side semiconductor element is composed of the power triac 1. The photocoupler 2 has an input end T
1 and T2, the power triac 1 has an output terminal T
3, equipped with T4. Since the two semiconductor elements are sealed in one resin encapsulant 25, the external wiring connecting the output end of the photocoupler 2 and the gate end of the power triac 1 and the output end of the photocoupler 2 and the input end of the power triac 1 are connected. No external wiring is required to connect to. This triac device is a power photo coupler or an optically coupled AC.
It is called a switch. The photocoupler 2 is composed of a light emitting diode LED22 and a phototriac 23 which is a driving stage of the triac device, and the power triac 1 constitutes an output stage of the triac device. Also in this case, as in FIG. 12, the photodriv (dV
/ Dt) c Withstand capacity and power triac (dV / dt)
The c-withstanding capability is about 10 V / μs or more. The triac semiconductor devices of FIGS. 12 and 13 both have a Darlington connection structure in which the driving stage and the output stage are Darlington connected.

[0005]

In both the phototriac and the power triac, the lifetime of minority carriers in the base region is controlled to about 6 to 9 μs in order to guarantee a (dV / dt) c tolerance of about 10 V / μs. I am trying to do it. For this reason, the base ground current amplification factor αpnp of the phototriac is lowered, and as a result, the optical gate sensitivity (IFT) is deteriorated. Moreover, this optical gate sensitivity is significantly temperature dependent. FIG. 9 is a characteristic diagram showing the temperature dependence of the gate sensitivity (IGT) of the triac device of the optically driven or electrically driven Darlington connection structure. The lifetimes of the minority carriers in the base region of the drive stage triac and the output stage triac of the conventional triac device are almost the same. Curve B in this figure shows the characteristics of a conventional triac device. As shown by the curve B, the gate sensitivity has a large temperature dependency, and the tendency is particularly remarkable in the low temperature region. For example, optical gate sensitivity of -40 ℃ and 25 ℃
It can be seen that the ratio with the optical gate sensitivity of is changed by about 3 times (IFT (-40 ° C) / IFT (25 ° C) ~
3).

As a result, the current flowing to the LED is, for example, 10 mA.
With a very small LED current (IF), stable operation at a low temperature of -40 ° C cannot be achieved. Therefore, conventionally, when operating the phototriac at a low temperature, it is necessary to flow an LED current of, for example, about 8 mA, which is 3 to 4 times as high as the normal temperature IFT standard. Therefore, the output current from the control side logic circuit is not enough and an LED drive circuit is required separately. Further, FIG. 8 shows (dV / dt) c of the triac device having an electrically driven Darlington connection structure.
The relationship (trade-off) between the withstand capacity and the gate sensitivity (IGT) is shown. As shown by the solid line B in the figure, the gate sensitivity (IG
The smaller (T) is, the smaller (dV / dt) c tolerance is. The lifetimes of minority carriers in the base regions of the drive stage triac and the output stage triac of this triac device are almost the same. The present invention has been made under such circumstances, and it is possible to improve the optical gate sensitivity or the gate sensitivity by a large amount.
It is an object of the present invention to provide a semiconductor device having a triac that reduces an ED drive current or a gate drive current and does not require a special drive circuit.

[0007]

According to the present invention, in a semiconductor device in which a drive stage triac and an output stage triac have a Darlington connection structure, a minority carrier lifetime in a base region of the output stage triac is set to a predetermined value. The lifetime of minority carriers in the base region of the drive stage triac is set to be larger than the predetermined value. That is, the semiconductor device of the present invention has a first triac having an input terminal, an output terminal and a gate terminal and used as a drive stage, and a first triac having an input terminal, an output terminal and a gate terminal and used as an output stage. 2 triacs, and has a Darlington connection structure in which the output terminal of the first triac is connected to the gate terminal of the second triac, and the life of minority carriers in the base region of the second triac. The time has a predetermined length, and the lifetime in the base region of the first triac is longer than the predetermined length.

The output terminal of the first triac and the second terminal
A resistance component may be further connected to the gate terminal of the triac. The first triac may be gate triggered by an optical signal. The minority carrier lifetime in the base region of the first triac is greater than 7 μs and 12 μs.
The predetermined length of the minority carrier lifetime in the base region of the second triac may be selected from values in the range of 4 μs to 10 μs. The base regions of the first and second triacs are irradiated with an electron beam for lifetime control, and the base regions of the second triac are irradiated with a predetermined amount of electron beams. 2 x 10 ¹²
When the number of electrons / cm ² or more, the amount of the electron beam applied to the base region of the first triac is 5 ×.
It may be 10 ¹¹ electrons / cm ² or less.

[0009]

In the semiconductor device in which the drive stage triac and the output stage triac have the Darlington connection structure, the lifetime of the minority carriers in the base region of the output stage triac is set to a predetermined value which is the same as the conventional value, and the drive stage By making the lifetime of the triac larger than the predetermined value, the gate sensitivity can be improved even if the (dV / dt) c withstand capability is increased, and the gate sensitivity is sufficiently high to withstand use even in a low temperature region. It is characterized by the improvement.

[0010]

Embodiments of the present invention will be described below with reference to the drawings. First, a first embodiment will be described with reference to FIGS. The semiconductor device of FIG. 1 is a cross-sectional view of a light-driven triac device, and three semiconductor elements forming the device are resin-sealed in one block. 2 is shown in FIG.
3 is a cross-sectional view of a photo coupler 2 portion of FIG. The input side semiconductor element is composed of a photocoupler 2 and is sealed in a translucent resin sealing body 24 such as a silicone resin. The output semiconductor element is composed of the power triac 1 made of, for example, a silicon chip. Photo coupler 2
Is the drive stage of the triac device and the light emitting diode LED22 made of, for example, gallium arsenide semiconductor,
For example, the power triac 1 is composed of a phototriac 23 composed of a silicon chip, and the power triac 1 constitutes an output stage of the triac device. These resin-sealed semiconductor elements are mounted on a die pad formed from the lead frame 5.

The power triac 1 at the output stage is adhered to the die pad 51 to which the output terminal T4 is continuously connected with an adhesive or the like. The other output terminal T3 is independent of the other parts of the lead frame 5. The drive-stage phototriac 23 constituting the photocoupler 2 is adhered to the die pad 52 to which the external terminals T5 are continuously connected by an adhesive agent or the like. Further, the LED 22 is adhered with an adhesive to the die pad 53 to which the input terminals T1 are continuously connected. The input terminal T2 is independent of the other parts of the lead frame 5. Between the terminals, between the chips, or between the chips / terminals, etc. are connected by a thin metal wire 3 such as Au. The power triac 1 and the output terminal T3 are connected by an aluminum wire 4. Phototriac 23
The output terminal and the gate electrode of the power triac 1 are A
It is connected by a u thin wire 3. As shown in FIG. 2, the die pads 52 and 53 are arranged flat on the same plane, and the light emitting surface of the LED 22 and the light receiving surface of the phototriac 23 mounted on the die pads 52 and 53 have a predetermined distance. Looking up. The LED 22 and the phototriac 23 including the die pads 52 and 53 are covered with a translucent resin encapsulant 24 such as a silicone resin, and the encapsulant 24 is used as an optical path.

The transparent resin encapsulant 24 is covered with a resin encapsulant 25 such as an epoxy resin. LED2
The light emitted from the second light emitting surface is reflected on the interface of the light-transmitting resin encapsulant 24 and enters the light receiving surface of the phototriac 23 from above. Therefore, the translucent resin encapsulant 24 plays the role of a reflecting mirror, and it is advantageous that the reflecting surface has a curvature that allows efficient reflection. The photo triac 23 is a lateral type, and the power triac 1 is
It is a vertical type, and both are connected to Darlington. The photocoupler 2 includes input terminals T1 and T2,
The power triac 1 has output terminals T3 and T4. Since the two semiconductor elements are sealed in one resin encapsulant 25 such as an epoxy resin, the external wiring connecting the output end of the phototriac 23 and the gate end of the power triac 1 and the output end of the photocoupler 2 and the power triac are connected. No external wiring is required to connect to the input terminal of 1. This triac device is called a power photo coupler or an optical coupling ACS switch. Also in this case,
Similar to Fig. 12, the phototriac (dV / dt)
Both the c withstand capability and the (dV / dt) c withstand capability of the power triac are about 10 V / μs or more.

The triac semiconductor devices of FIGS. 12 and 13 both have a Darlington connection structure in which the driving stage and the output stage are Darlington connected. These conventional triac devices of the Darlington connection structure are (dV / dt).
The c withstand amount is guaranteed to be about 10 V / μs.
Therefore, the lifetimes of the minority carriers in the base regions of the drive stage phototriac and the output stage power triac were both about 7 μsec. On the other hand, in the case of this embodiment shown in FIG. 1, the lifetime of minority carriers in the base region of the power triac is 7 μsec as in the conventional case, but the lifetime of the phototriac is increased to about 12 μsec. ing. By increasing the lifetime in this way, αpnp is increased and high sensitivity is realized. In the present invention, in order to control the lifetime of minority carriers in the base region of these triacs, for example, electron beam irradiation (EBI;
Electron Beam Irradiation) technology is used. As other control methods, various techniques such as proton irradiation, injection of heavy metals such as Au and Pt, and He-ray irradiation can be used.

The internal structure of the triac and the method of irradiating the electron beam with which the triac is irradiated will be described with reference to FIGS. 3 to 5. FIG. 3 is a cross-sectional view of the vertical type triac and corresponds to the power triac 1 of the output stage shown in FIG. FIG. 4 is a plan view of the lateral type triac, which corresponds to the phototriac 23 of the drive stage shown in FIG. FIG. 5 is a sectional view of a portion taken along the line AA ′ in FIG. The vertical type triac shown in FIG. 3 includes an n base region NB of a silicon semiconductor substrate, a first p base region PB1 and a second p base region PB1 formed above and below the n base region NB.
The base region PB2 is provided. First of this semiconductor substrate
An n gate region NG and a first n emitter region NE1 are formed in the first p base region PB1 formed on the main surface of the first p base region PB1, and a second p base region P formed on the second main surface thereof.
A second n emitter region NE2 is formed in B2. A gate terminal (G terminal) is provided to the gate region NG via an electrode, a first terminal (T1 terminal) is provided to the first n emitter region NE1 via an electrode, and a second n emitter region NE2 is provided via an electrode. The second terminals (T2 terminals) are attached respectively. When the power triac shown in FIG. 1 is compared, the first terminal corresponds to the T3 terminal and the second terminal corresponds to the T4 terminal.

The phototriac shown in FIGS. 3 and 4 is of a lateral type, and the n ⁻ silicon semiconductor substrate 10 is composed of an n ⁻ base region NB ⁻ . A first anode region PA1 and a second anode region PA2 are formed on the main surface of the semiconductor substrate, and a first p base region PB1 and a second p base region PB2 are formed adjacent to them. There is. In addition, the first and second p base regions PB
First and second n-emitter regions NE1 and NE2 are formed in the first and second PB2, respectively. An Al wiring is formed on these regions to connect each region to the outside through an insulating film 20. The Al wiring 30 is connected to the first p base region PB1, the Al wiring 31 is wired so as to electrically connect the second anode region PA2 and the first n emitter region NE1, and the Al wiring 32. Is wired so as to electrically connect the first anode region PA1 and the second n emitter region NE2, and the Al wiring 32 is connected to the second p region.
It is connected to the base region PB2. Al wiring 30, 3
For example, 1 is connected by a resistor 40 such as polysilicon, and Al wirings 32 and 33 are connected by a resistor 41 such as polysilicon.

When this phototriac is applied to the triac device having the Darlington connection structure of FIG. 1, it is used for a triac of a driving stage, and one of its first terminal (T1 terminal) and second terminal (T2 terminal) is an output stage. Is connected to the gate of the triac, and the other is connected to the output terminal T4. In the photo triac having such a configuration, the high voltage to the terminal T1, when the low voltage is applied to the terminal T2, the light from the LED enters the semiconductor substrate, ^{current, T1 → PA1 → NB - →} PB1 → It flows in the route of NE1 → T2. When a low voltage is applied to the T1 terminal and a high voltage is applied to the T2 terminal, the current is T2 → PA2 → N.
B ^- → flows PB2 → NE2 → T1. Electron beam irradiation,
This is done to control the lifetime of minority carriers in the base region of the semiconductor substrate, but since the electron beam has a strong penetrating power to silicon, the lifetime of minority carriers in the base region is irradiated by irradiating the entire semiconductor substrate with an electron beam. Are controlling. Therefore, in the case of the semiconductor substrate shown in FIG. 3 and the case of the semiconductor substrate shown in FIGS. 4 and 5, the electron beam is applied to the entire surface.

FIG. 12 shows the current flowing through each triac at turn-on in the Darlington connection circuit of the conventional triac device, and FIG. 14 shows the state of each current at that time. FIG. 14 is a current waveform diagram from the time when the ON signal is input to the time t in the triac device having the Darlington connection structure shown in FIG. The vertical axis shows the current (i) flowing in the triac device, and the horizontal axis shows the time after the signal is input. The currents shown are the current IF supplied to the LED 22, the current i1 flowing from the drive stage phototriac 23 to the power triac 1, that is, the current flowing from the output terminal T4 of the phototriac 23 to the gate terminal T5 of the power triac 1. i1 and current i2 flowing from the output terminal T7 of the power triac 1 to the outside. In order to turn on the light-driven triac device, the light emitting diode LED22 is supplied with a current I of, for example, 10 mA.
Flow F. When this current IF flows through the LED 22, the phototriac 23 turns on and a current i1 flows. This current i1 is the drive current I of the power triac 1.
When the GT is reached, the power triac 1 is turned on,
The current i2 starts to flow. At this time, the current i1 flows from the output end T4 of the phototriac 23 to the input end T5 of the power triac 1.

The current i1 is output from the output end T6 of the power triac 1 to the output end T3 of the phototriac 23 to the output end T4 of the phototriac 23 to the power triac 1.
Since the potential drop is smaller when flowing from the gate end T5 of the power triac 1 to the output end T7 of the power triac 1 than from the output end T7 of the power triac 1, the current i2
At the same time that the flow started, the flow stopped (see FIG. 14).
This is because the latter flow has 1 emitter-base junction.
In addition, the forward voltage drop VF of the power triac 1 is the forward voltage drop VF of the phototriac 23.
Because it is smaller than. Therefore, when the power triac enters the commutation operation, no current has already flowed in the phototriac of the driving stage, and (dV / d
t) c Accumulation of minority carriers in the base region, which is a problem in terms of withstanding capability, does not occur in the phototriac 23 in the driving stage. That is, the (dV / dt) c withstand capability of the Darlington connection triac device is normally determined by the (dV / dt) c withstand capability of the power triac 1. Therefore, in the Darlington connection structure, (dV of the drive stage triac is
Even if the lifetime of minority carriers in the base region is lowered to increase the / dt) c withstand capability, IGT or IFT only increases, and the (dV / dt) c withstand capability of the triac device having the Darlington connection structure does not change.

Next, a second embodiment will be described with reference to FIGS. FIG. 6 is a plan view of the electrically driven triac device, and FIG. 7 is an equivalent circuit diagram thereof. Two semiconductor elements 1 and 6 that constitute the electrically driven triac device
Is resin-sealed in one block. The input-side semiconductor element 6 is composed of a drive stage triac chip. The output side semiconductor element 1 is composed of, for example, a power triac chip made of a silicon chip or the like. These semiconductor elements 1 and 6 are attached to the lead frame 5. The power triac 1 at the output stage has an input terminal T
2 are adhered to the die pad 54, which is continuously connected, with an adhesive or the like. The output terminal T1 and the gate terminal are independent of the other parts of the lead frame 5. The drive stage triac 6 is bonded to the die pad 54 with an adhesive or the like. Between terminals, between semiconductor elements or semiconductor element /
The terminals and the like are connected by a thin metal wire 3 such as Au. The power triac 1 and the output terminal T1 are connected by an aluminum wire 4. The output terminal of the drive stage triac 6 and the gate electrode of the power triac 1 are connected by an Au thin wire 3.

Semiconductor elements 1 and 6, Au wire 3, Al wire 4,
The die pad 54 and the terminals T1, T2, T3, etc. are covered with a resin encapsulant 25 such as an epoxy resin. As a triac mounted on such a die pad 54, a small triac 6 having a rated current of about several hundred mA is used as a drive stage, and 3A to 16A as an output stage.
A triac 1 having a large rated current is used. The drive stage triac 6 and the power triac 1 are Darlington connected (see FIG. 7). Even if two triacs are used, one triac device is functionally configured. T1 terminal, T2 of this triac device
The terminal and the G terminal are the output terminal T1 and the input terminal T, respectively.
2. The gate terminal T3 corresponds to them. In order to maintain high (dV / dt) c tolerance between the terminals T1 and T2 of this triac device while maintaining high sensitivity, the lifetime τ2 of minority carriers in the base region of the power triac 1 at the output stage is set to the conventional triac. 7 μsec, which is the same as
And the lifetime τ1 of minority carriers in the base region of the triac 6 in the drive stage is set to 12 μsec, which is larger than that of the conventional one.
It is about. As a result, the αpnp of the triac 6 is increased and high sensitivity is realized.

However, in the Darlington-connected triac device, when the lifetime of the drive stage triac is lengthened, the forward voltage drop VF of the drive stage triac gradually decreases, and a slight amount of current flows to the drive stage side. It remains flowing, and (d
The V / dt) c tolerance falls into the region determined by the (dV / dt) c tolerance on the drive stage side. Life time τ in Figure 8
1 = 13 μsec is an operation mode corresponding to this. FIG. 8 is a characteristic diagram illustrating the gate sensitivity (IGT) dependence of the (dV / dt) c tolerance in explaining the above-mentioned tendency, and the vertical axis represents (dV / dt) c tolerance (V / μsec). The gate sensitivity (IGT) (μA) is shown on the axis. In this figure, the dotted line A is the (dV / dt) c tolerance-IGT curve of the Darlington-connected triac device of this embodiment, and the solid line B is the (dV / dt) c tolerance of the conventional Darlington-connected triac device. -IGT curve. As shown in this figure, in the conventional triac device, when the (dV / dt) c withstand capability is set to 30 V / μs or more, the gate sensitivity (IGT) becomes 250 μA or more (solid line B).

However, for example, the lifetime τ1 of the power triac 1 in the output stage as in this embodiment is set to 7 μs.
To a constant value, and the drive stage triac 6 has a lifetime τ
When 2 is increased from 7 μs → 8 μs → 10 μs → 12 μs, when the gate sensitivity (IGT) is 250 μA, (dV
/ Dt) c withstand is 30V / μs and IGT is 250.
μA → 200 μA → 150 μA → 80 μA, and high sensitivity is realized. When the lifetime τ2 is 13 μs, the characteristics match those of the conventional triac device (dotted line A). The present invention is characterized in that the minority carrier lifetime τ1 in the drive stage triac base region is longer than the minority carrier lifetime τ2 in the output stage triac base region. Minority carrier lifetime τ2 is
4 μs to 10 μs is suitable, and the lifetime τ1 of minority carriers in the base region of the triac of the driving stage
Is suitably about 8 μs to 12 μs.

The dotted line A shown in this figure is the characteristic obtained when the lifetime τ1 of the minority carriers in the base region of the power triac 1 in the output stage is kept constant at 7 μs. When the constant value of the lifetime τ1 is changed to another value, its characteristic changes, but there is a region where the (dV / dt) c withstand capability does not change even if the gate sensitivity, which is a feature of the present invention, is increased. For example, this lifetime τ1 is 5 μs
Then, the characteristic line showing the gate sensitivity (IGT) dependence of the (dV / dt) c withstand capability of the triac device of this embodiment shown in FIG. In order to control the lifetime of minority carriers in the base region of the triac, methods such as proton irradiation to the base region, implantation of heavy metals such as Au and Pt, and He beam irradiation are used. In this embodiment, electron beam irradiation is used. . For example, the electron beam irradiation when the lifetime is 7 μs is 2 × 10 ¹² electrons / cm ² . The electron beam irradiation when the lifetime is 8 μs is 5 × 10 ¹¹ electrons / cm ² . The electron beam irradiation when the lifetime is 12 μs is 1.1 × 10 ¹¹ electrons / cm ² . When the lifetime is 13 μs, it is not necessary to irradiate the base region of the silicon semiconductor substrate with the electron beam. Therefore, the electron beam irradiation for controlling the lifetime τ1 of the present invention is appropriately 5 × 10 ¹¹ electrons / cm ² or less.

Next, the temperature dependence of the gate sensitivity (IGT) of the present invention will be described with reference to FIG. The figure shows the characteristics of this embodiment and the conventional Darlington-connected triac device. The lifetimes of the minority carriers in the base region of the drive stage triac and the output stage triac of the conventional Darlington connection structure triac device are almost the same (7 μs), and the curve B shows the characteristics of the triac device. ing. As shown by the curve B, the gate sensitivity has a large temperature dependency, and the tendency is particularly remarkable in the low temperature region. For example, a gate sensitivity of -40 ° C and 25
It can be seen that the ratio of the gate sensitivity to ℃ changes about 3 times (IGT (-40 ℃) / IGT (25 ℃) ~
3). As a result, when this triac device is an optical drive type, it flows into the LED, for example, a small LE of about 10 mA.
With the D current (IF), stable operation cannot be performed at a low temperature of -40 ° C. This increase in gate sensitivity at low temperatures is reduced by reducing the lifetime τ1 in order to guarantee the (dV / dt) c withstand capability of the drive stage triac device.
This is because pnp is extremely small.

Therefore, conventionally, when operating the phototriac at a low temperature, the LED current is, for example, 8 mA.
It is necessary to pass a current three to four times as high as the normal temperature IFT standard. Therefore, the output current from the control side logic circuit is not enough, and an LED drive circuit is needed separately. The gate sensitivity (IGT) itself at 25 ° C is also large.
On the other hand, in the Darlington connection triac device of this embodiment, the lifetime .tau.1 of the minority carrier in the base region of the triac of the driving stage is lengthened to 10 .mu.s to increase .alpha.pnp. Almost no increase in sensitivity (IGT) occurs. As shown in the figure, the ratio of IGT at Tc = -40 ° C and Tc = 25 ° C is as low as 1.3 times, and the IGT at 25 ° C is much lower than before, so no special drive circuit is required. Become.
Such an effect is particularly remarkable in the case of the Darlington connection of the phototriac of the drive stage and the power triac of the output stage of the first embodiment shown in FIG.
Almost no increase in FT is observed.

Next, a third embodiment will be described with reference to FIGS. Each of the figures is a circuit diagram of a resin-sealed Darlington connection triac device. Figure 10
6 uses the drive stage triac and the output stage power triac shown in FIG. 6, and FIG. 11 uses the photocoupler and the output stage power triac shown in FIG. In the Darlington connection triac device, if the lifetime of the minority carriers in the base region of the drive stage triac is lengthened, the VF of the drive stage triac gradually decreases,
A small amount of current remains flowing to the drive stage side, and the (dV / dt) c withstand capability of the entire triac device enters the region determined by the (dV / dt) c withstand capability of the drive stage side. The lifetime τ1 = 13 μsec in FIG. 8 is an operation mode corresponding to this. In order to prevent such operation, in this embodiment, a resistor is inserted between the drive stage output and the output stage gate of the triac device.

The electric drive type Darlington connection triac device of FIG. 10 comprises a drive stage triac 6 and an output stage power triac 1, and has an output terminal T1, an input terminal T2 and a gate terminal T3 (G). There is. A resistor R1 is connected between the output of the drive stage triac 6 and the gate of the output stage power triac 1.
The output terminal T1 is connected to the output of the output stage, and the input terminal T1
2 is connected to the inputs of the driving stage and the output stage, and the gate terminal (G) T3 is connected to the gate of the driving stage. This triac device is sealed in a resin sealing body 26 such as an epoxy resin together with the resistor 1. Further, the optically driven Darlington connection triac device of FIG. 11 is provided with a drive stage phototriac 23 having an LED 22 and an output stage power triac 1, and has input terminals T1 and T2 and output terminals T3 and T4. ing. A resistor R2 is connected between the output of the drive stage phototriac 23 and the gate of the output stage power triac 1. This triac device is sealed in a resin sealing body 25 such as an epoxy resin together with the resistor R2.

The resistors R1 and R2 may be polysilicon resistors formed on the semiconductor chip, or may be diffusion resistors formed on the semiconductor chip of the power triac of the output stage. When a resistor is inserted between the output of the drive stage and the gate of the output stage as in this embodiment, no current flows through the drive stage triac due to the potential drop of this resistor,
The (dV / dt) c tolerance is again determined by the (dV / dt) c tolerance of the output stage power triac.

[0029]

The present invention has the above-mentioned structure.
The optical gate sensitivity (IFT) or gate sensitivity (IGT) of the conventional Darlington connection triac device is maintained at about 10 V / μs or more while maintaining the (dV / dt) c withstand capability of about 1
It can be set to / 2. Further, for example, by providing a Darlington-connected triac device in which an increase in the optical gate sensitivity or the gate sensitivity at a low temperature of −40 ° C. is significantly reduced, the LED drive current or the gate drive current is significantly reduced, and a drive circuit is provided. Can be simplified or omitted.

[Brief description of drawings]

FIG. 1 is a plan view of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a sectional view of a photocoupler portion of FIG.

FIG. 3 is a cross-sectional view of the vertical type triac used in the first embodiment.

FIG. 4 is a plan view of a lateral phototriac used in the first embodiment.

5 is a cross-sectional view of a portion taken along the line AA ′ in FIG.

FIG. 6 is a plan view of a semiconductor device according to a second embodiment.

FIG. 7 is a circuit diagram of a semiconductor device according to a second embodiment.

FIG. 8 shows (dV / of the second embodiment and the conventional semiconductor device).
dt) c is a characteristic diagram illustrating the gate sensitivity dependence of the withstand capability.

FIG. 9 is a characteristic diagram illustrating temperature dependence of gate sensitivity of the second embodiment and the conventional semiconductor device.

FIG. 10 is a circuit diagram of a semiconductor device according to a third embodiment.

FIG. 11 is a circuit diagram of a semiconductor device according to a third embodiment.

FIG. 12 is a schematic plan view of a conventional semiconductor device.

FIG. 13 is a schematic plan view of a conventional semiconductor device.

FIG. 14 is an operation explanatory view of the present invention and the conventional Darlington connection triac device.

[Explanation of symbols]

1 power triac 2 Photo coupler 3 Au line 4 Al wire 5 lead frame 6 drive stage triac 10 Semiconductor substrate 11, 21, 25, 26 Resin sealing body 20 insulating film 22 LED 23 Phototriac 24 Translucent resin encapsulant 30, 31, 32, 33 Al wiring 40, 41 resistance 50 contacts 51, 52, 53, 54 Die pad

─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-6-151947 (JP, A) JP-A-6-5846 (JP, A) JP-A-4-302214 (JP, A) JP-A-2- 253665 (JP, A) JP 63-190382 (JP, A) JP 58-140161 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 31/10-31 / 119 H01L 29/74-29/747

Claims (5)

(57) [Claims] 1. A first bidirectional three-terminal thyristor which has an input terminal, an output terminal and a gate terminal and is used as a driving stage, and an input terminal, an output terminal and a gate terminal which are used as an output stage. And a Darlington connection structure in which an output terminal of the first bidirectional 3-terminal thyristor is connected to a gate terminal of the second bidirectional 3-terminal thyristor. 2 bidirectional 3
The minority carrier lifetime in the base region of the terminal thyristor has a predetermined length, and the first bidirectional 3
A semiconductor device, wherein a lifetime of the terminal thyristor in the base region is longer than the predetermined length. 2. The resistance component is further connected between the output terminal of the first bidirectional three-terminal thyristor and the gate terminal of the second bidirectional three-terminal thyristor. Semiconductor device. 3. The first bidirectional three-terminal thyristor,
The semiconductor device according to claim 1, wherein the semiconductor device is gate-triggered by an optical signal. 4. The minority carrier lifetime in the base region of the first bidirectional 3-terminal thyristor is 7
It is larger than μs and smaller than 12 μs, and the predetermined length of the minority carrier lifetime in the base region of the second bidirectional three-terminal thyristor is 4 μs to 10 μs.
4. The semiconductor device according to claim 1, wherein the semiconductor device is selected from values in the range of μs. 5. The base regions of the first and second bidirectional three-terminal thyristors are irradiated with an electron beam for lifetime control, and the base regions of the second bidirectional three-terminal thyristors are irradiated. When a predetermined amount of electron beam is irradiated and the predetermined amount is 2 × 10 ¹² electrons / cm ² or more,
The amount of the electron beam with which the base region of the first bidirectional three-terminal thyristor is irradiated is 5 × 10 ¹¹ electrons / cm ² or less, and the amount of the electron beam is 5 × 10 ¹¹ electrons / cm ² or less. Semiconductor device.