JP3386967B2 - Substrate inspection method - Google Patents
Substrate inspection methodInfo
- Publication number
- JP3386967B2 JP3386967B2 JP34346296A JP34346296A JP3386967B2 JP 3386967 B2 JP3386967 B2 JP 3386967B2 JP 34346296 A JP34346296 A JP 34346296A JP 34346296 A JP34346296 A JP 34346296A JP 3386967 B2 JP3386967 B2 JP 3386967B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- support substrate
- insulating film
- wiring
- insulating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/01—Manufacture or treatment
- H10W72/0198—Manufacture or treatment batch processes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
- H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
- H10W70/68—Shapes or dispositions thereof
- H10W70/681—Shapes or dispositions thereof comprising holes not having chips therein, e.g. for outgassing, underfilling or bond wire passage
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/073—Connecting or disconnecting of die-attach connectors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/075—Connecting or disconnecting of bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/851—Dispositions of multiple connectors or interconnections
- H10W72/874—On different surfaces
- H10W72/884—Die-attach connectors and bond wires
Landscapes
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Die Bonding (AREA)
Description
【0001】[0001]
【発明の属する技術分野】本発明は、基板の検査法に関
する。TECHNICAL FIELD The present invention relates to a method for inspecting a substrate.
【0002】[0002]
【従来の技術】半導体の集積度が向上するに従い、入出
力端子数が増加している。従って、多くの入出力端子数
を有する半導体パッケージが必要になった。一般に、入
出力端子はパッケージの周辺に一列配置するタイプと、
周辺だけでなく内部まで多列に配置するタイプがある。
前者は、QFP(Quad Flat Packag
e)が代表的である。これを多端子化する場合は、端子
ピッチを縮小することが必要であるが、0.5mmピッ
チ以下の領域では、配線板との接続に高度な技術が必要
になる。後者のアレイタイプは比較的大きなピッチで端
子配列が可能なため、多ピン化に適している。従来、ア
レイタイプは接続ピンを有するPGA(Pin Gri
d Array)が一般的であるが、配線板との接続は
挿入型となり、表面実装には適していない。このため、
表面実装可能なBGA(Ball Grid Arra
y)と称するパッケージが開発されている。2. Description of the Related Art The number of input / output terminals has increased as the degree of integration of semiconductors has improved. Therefore, a semiconductor package having a large number of input / output terminals has been required. Generally, I / O terminals are arranged in a row around the package,
There is a type that arranges not only the periphery but also the interior in multiple rows.
The former is QFP (Quad Flat Packag)
e) is typical. When the number of terminals is increased, it is necessary to reduce the terminal pitch, but in the area of 0.5 mm pitch or less, a high level technique is required for connection with the wiring board. The latter array type is suitable for increasing the number of pins because the terminals can be arranged at a relatively large pitch. Conventionally, the array type has a PGA (Pin Gri) having connection pins.
d Array) is generally used, but the connection with the wiring board is an insertion type and is not suitable for surface mounting. For this reason,
Surface mountable BGA (Ball Grid Arra)
A package called y) has been developed.
【0003】一方、電子機器の小型化に伴って、パッケ
ージサイズの更なる小型化の要求が強くなってきた。こ
の小型化に対応するものとして、半導体チップとほぼ同
等サイズの、いわゆるチップサイズパッケージ(CS
P; Chip Size Package)が提案さ
れている。これは、半導体チップの周辺部でなく、実装
領域内に外部配線基板との接続部を有するパッケージで
ある。具体例としては、バンプ付きポリイミドフィルム
を半導体チップの表面に接着し、チップと金リード線に
より電気的接続を図った後、エポキシ樹脂などをポッテ
ィングして封止したもの(NIKKEI MATERI
ALS & TECHNOLOGY 94.4,No.
140,p18−19)や、仮基板上に半導体チップ及
び外部配線基板との接続部に相当する位置に金属バンプ
を形成し、半導体チップをフェースダウンボンディング
後、仮基板上でトランスファーモールドしたもの(Sm
allest Flip−Chip−Like Pac
kage CSP; TheSecond VLSI
Packaging Workshop of Jap
an,p46−50,1994)などがある。On the other hand, with the miniaturization of electronic equipment, there is an increasing demand for further miniaturization of the package size. To cope with this miniaturization, a so-called chip size package (CS
P; Chip Size Package) has been proposed. This is a package having a connection portion with an external wiring board in the mounting area, not in the peripheral portion of the semiconductor chip. As a specific example, a polyimide film with bumps is adhered to the surface of a semiconductor chip, an electrical connection is made between the chip and a gold lead wire, and then epoxy resin or the like is potted and sealed (NIKKEI MATERI).
ALS & TECHNOLOGY 94.4, No.
140, p18-19), or metal bumps are formed on the temporary substrate at positions corresponding to the connection portions of the semiconductor chip and the external wiring substrate, the semiconductor chip is face-down bonded, and then transfer molded on the temporary substrate ( Sm
allest Flip-Chip-Like Pac
case CSP; TheSecond VLSI
Packing Workshop of Japan
an, p. 46-50, 1994).
【0004】[0004]
【発明が解決しようとする課題】しかしながら、従来提
案されている半導体パッケージの多くは、小型で高集積
度化に対応できかつパッケージクラックを防止し信頼性
に優れ、しかも生産性に優れるものではない。本発明
は、パッケージクラックを防止し信頼性に優れる小型の
半導体パッケ−ジが製造可能なパッケ−ジ用チップ支持
基板の、パッケージクラック防止を検査する方法を提供
するものである。本発明は、短時間で容易に絶縁性フィ
ルム状接着材全体の貼付状態を観察できる半導体パッケ
ージ用チップ支持基板の検査法を提供するものである。However, most of the conventionally proposed semiconductor packages are not compact and capable of accommodating a high degree of integration, preventing package cracks, and being excellent in reliability and productivity. . The present invention provides a method of inspecting a package chip support substrate for preventing package cracks and capable of manufacturing a small semiconductor package having excellent reliability. The present invention provides a method for inspecting a chip support substrate for a semiconductor package, which allows the adhered state of the entire insulating film adhesive to be easily observed in a short time.
【0005】[0005]
【課題を解決するための手段】本発明の基板の検査法
は、
A.絶縁性支持基板の一表面に半導体チップ搭載領域を
有する配線が2以上形成されており、前記配線は前記半
導体チップ搭載領域に半導体チップを絶縁性フィルム状
接着材を介して搭載した時前記絶縁性フィルム状接着材
の絶縁性支持基板対向面と前記2の配線端面と絶縁性支
持基板の前記表面とで空隙が形成されるように配置され
ており、
B.前記絶縁性支持基板には、前記空隙に面する箇所に
少なくとも1つの貫通孔が形成されており、
C.半導体チップ搭載領域の前記配線上を含めて半導体
チップが搭載される箇所に、絶縁性フィルム状接着材が
形成されている半導体パッケージ用支持基板の検査法で
あって、
D.前記空隙の開口部の一部から空隙内に液体を注入さ
せ、 E.液体が毛細管現象により前記貫通孔に達成する時間
を計測することにより、当該時間と、絶縁性フィルム状
接着材の貼付状態に応じてあらかじめ計測してカテゴリ
ー分けしてあった当該時間とを比較することで、当該半
導体パッケージ支持基板における絶縁性フィルム状接着
材の貼付状態の善し悪しを検査する
ことを特徴とする。A method of inspecting a substrate according to the present invention comprises: Wiring that Yusuke <br/> the semiconductor chip mounting area on one surface of the insulating support substrate is formed of two or more, the wiring of the semiconductor chip to the semiconductor chip mounting region through the insulating film adhesive material B. When mounted, a space is formed between the surface of the insulating film adhesive facing the insulating support substrate, the end surface of the second wiring, and the surface of the insulating support substrate, B. Wherein the insulating support substrate is at least one through hole is formed at a position that menses in the gap, C. A method for inspecting a supporting substrate for a semiconductor package, wherein an insulating film adhesive is formed on a portion where a semiconductor chip is mounted, including on the wiring in the semiconductor chip mounting region, and D. Liquid is injected into the void from a part of the opening of the void.
Then, E. Time for liquid to reach the through hole by capillary action
By measuring the time and the insulating film
Pre-measured according to the attachment status of the adhesive
-By comparing the time that was divided,
Insulating film-like bonding on conductor package support substrate
It is characterized by inspecting the adhering condition of the material .
【0006】パッケージクラックを防止し信頼性に優れ
る小型の半導体パッケ−ジが製造可能な、パッケ−ジ用
チップ支持基板として、
A.絶縁性支持基板の一表面に半導体チップ搭載領域を
有す配線が2以上形成されており、前記配線は前記半導
体チップ搭載領域に半導体チップを絶縁性フィルム状接
着材を介して搭載した時前記絶縁性フィルム状接着材の
絶縁性支持基板対向面と前記2の配線端面と絶縁性支持
基板の前記表面とで空隙が形成されるように配置されて
おり、
B.前記絶縁性支持基板には、前記空隙に面す箇所に少
なくとも1つの貫通孔が形成されており、
C.半導体チップ搭載領域の前記配線上を含めて半導体
チップが搭載される箇所に、絶縁性フィルム状接着材が
形成されている半導体パッケ−ジ用チップ支持基板があ
る。As a package chip support substrate capable of preventing a package crack and manufacturing a small semiconductor package having excellent reliability, A. Two or more wirings having a semiconductor chip mounting area are formed on one surface of the insulating support substrate, and the wiring is insulated when the semiconductor chip is mounted on the semiconductor chip mounting area via an insulating film adhesive. A surface of the adhesive film adhesive facing the insulative support substrate, the wiring end face of the second wiring, and the surface of the insulative support substrate are arranged to form a space, and B. At least one through hole is formed in the insulating support substrate at a position facing the void, and C.I. There is a chip support substrate for a semiconductor package, in which an insulating film adhesive is formed, at a position where the semiconductor chip is mounted, including on the wiring in the semiconductor chip mounting region.
【0007】この半導体パッケ−ジ用チップ支持基板
は、半導体チップ搭載部に接着する絶縁性フィルム状接
着材の貼付状態(配線間にテント状に貼付けて貫通穴と
連結した空隙を形成する)が重要であるが、絶縁性フィ
ルム状接着材を貼付けた上からでは、その状態を充分に
観察するのは不可能である。半導体パッケージ用チップ
支持基板をエポキシ樹脂等を用いて注型し、断面を切断
して観察するのでは、観察するのに多くの時間と手間が
必要であり、また観察できるのは1断面だけであり、全
体の貼付状態を観察することは非常に困難であるが、本
発明の検査法は短時間で容易に絶縁性フィルム状接着材
全体の貼付状態を観察できる。本発明で、空隙の開口部
は貫通孔及び前記配線間の間隙が該当する。In this semiconductor package chip support substrate, when the insulating film adhesive material adhered to the semiconductor chip mounting portion is adhered (it is adhered in a tent shape between wirings to form a void connected to the through hole). It is important to note that it is impossible to fully observe the state of the insulating film adhesive after it has been attached. It takes a lot of time and labor to observe a chip supporting substrate for a semiconductor package by casting it with epoxy resin or the like, cutting the cross section, and observing only one cross section. However, it is very difficult to observe the entire pasted state, but the inspection method of the present invention can easily observe the entire pasted state of the insulating film adhesive. In the present invention, the opening of the void corresponds to a gap between the through hole and the wiring.
【0008】[0008]
【発明の実施の形態】絶縁性支持基板としては、ポリイ
ミド、エポキシ樹脂、ポリイミド等のプラスチックフィ
ルム、ポリイミド、エポキシ樹脂、ポリイミド等のプラ
スチックをガラス不織布等基材に含浸・硬化したもの等
が使用できる。絶縁性支持基板の一表面に複数組の配線
を形成すには、銅箔をエッチングする方法、所定の箇所
に銅めっきをする方法、それらを併用する方法等が使用
できる。絶縁性支持基板に貫通穴を設けるには、ドリル
加工やパンチングなどの機械加工、エキシマレーザや炭
酸ガスレーザなどのレーザ加工等により行うことができ
る。また、接着性のある絶縁基材等に開口部をあらかじ
め設け、それを銅箔等の配線形成用金属箔と張り合わせ
る方法、銅箔付きまたはあらかじめ配線が形成された絶
縁基材に開口部を設ける方法、それらを併用する等が可
能である。BEST MODE FOR CARRYING OUT THE INVENTION As the insulating support substrate, a plastic film of polyimide, epoxy resin, polyimide or the like, or a material such as glass nonwoven fabric impregnated and cured with a plastic of polyimide, epoxy resin, polyimide or the like can be used. . In order to form a plurality of sets of wiring on one surface of the insulative support substrate, a method of etching a copper foil, a method of plating copper at a predetermined place, a method of using them in combination, and the like can be used. The through holes can be formed in the insulating support substrate by mechanical processing such as drilling or punching, laser processing such as excimer laser or carbon dioxide laser, and the like. Also, an opening is provided in advance on an adhesive insulating base material and the like, and it is attached to a metal foil for forming a wiring such as copper foil, or an opening is provided on an insulating base material with a copper foil or in which wiring is formed in advance. It is possible to provide them and to use them together.
【0009】半導体チップ搭載領域は、できるだけ均一
に配線パターンが配置されていることが好ましい。具体
的には、半導体チップ搭載領域の絶縁性支持基板には、
任意の点からその任意の点を含む半径1ミリメートルの
範囲に少なくとも1つ以上の配線が形成されているよう
に配線が配置されていることが好ましい。しかし、配線
だけでこのような条件が満足できな場合は、別に独立の
ダミーパターン、位置合わせ用マーク、文字・符号等な
どの金属パターンを設けても良い。In the semiconductor chip mounting area, it is preferable that the wiring patterns are arranged as uniformly as possible. Specifically, the insulating support substrate in the semiconductor chip mounting area,
It is preferable that the wirings are arranged so that at least one wiring is formed in a range of a radius of 1 millimeter including the arbitrary point. However, if such a condition cannot be satisfied only by wiring, an independent dummy pattern, a positioning mark, a metal pattern such as characters / codes may be separately provided.
【0010】絶縁性フィルム状接着材には、ポリイミ
ド、エポキシ樹脂、ポリイミド等のプラスチックフィル
ムに接着材を片面もしくは両面に塗布したもの、または
単層の絶縁性フィルム状接着材が使用できる。単層の絶
縁性フィルム状接着材としては、例えば化1As the insulating film adhesive, a plastic film made of polyimide, epoxy resin, polyimide or the like coated with an adhesive on one or both sides, or a single-layer insulating film adhesive can be used. As a single-layer insulating film adhesive, for example,
【化1】
(ただし、n=2〜20の整数を示す。)で表されるテ
トラカルボン酸二無水物(1)の含量が全テトラカルボ
ン酸二無水物の70モル%以上であるテトラカルボン酸
二無水物と、ジアミンを反応させて得られるポリイミド
樹脂、更にエポキシ樹脂等の熱硬化性樹脂からなるフィ
ルム状接着材がある。更にこれにシリカ、アルミナ、等
の無機物質フィラーを含有させることもできる。[Chemical 1] (However, the integer of n = 2-20 is shown.) The tetracarboxylic dianhydride whose content of the tetracarboxylic dianhydride (1) is 70 mol% or more of all the tetracarboxylic dianhydrides. And a polyimide resin obtained by reacting a diamine, and a film adhesive made of a thermosetting resin such as an epoxy resin. Further, an inorganic substance filler such as silica or alumina may be contained therein.
【0011】単層の絶縁性フィルム状接着材を使用する
場合の厚みについては、半導体チップと配線間の絶縁性
を確保できる限り、薄くしたほうがテント状に貼付けや
すい。具体的には、0.005mm以上かつ0.030
mm以下が好ましく、さらには0.010mm以上かつ
0.020mm以下の範囲がより好ましい。また、絶縁
性フィルムに接着材を塗布したものを使用する場合は、
同様に接着材層の厚みは薄いほうが好ましい。貫通穴
は、絶縁性フィルム状接着材搭載領域に少なくとも1個
以上形成される。穴径は特に問わないが、例えば、0.
05mm以上かつ1.000mm以下が好ましい。配置
も特に問わないが、なるべく均等に複数個配置されてい
ることが好ましく、これらの穴径および配置は、配線パ
ターンに応じて選択される。Regarding the thickness of the single-layer insulating film-like adhesive material, the thinner it is, the easier it is to attach in a tent shape, as long as the insulation between the semiconductor chip and the wiring can be secured. Specifically, 0.005 mm or more and 0.030
mm or less, and more preferably 0.010 mm or more and 0.020 mm or less. When using an insulating film coated with adhesive,
Similarly, the thickness of the adhesive layer is preferably thin. At least one through hole is formed in the insulating film adhesive mounting region. The hole diameter is not particularly limited, but for example, 0.
It is preferably at least 05 mm and at most 1.000 mm. The arrangement is not particularly limited, but it is preferable that a plurality of them are arranged as evenly as possible, and the hole diameter and the arrangement thereof are selected according to the wiring pattern.
【0012】検査に使用される液体は特に限定されるも
のではないが、絶縁性支持基板と絶縁性フィルム状接着
材の材質、及び空隙の間隔等を考慮し、適正な粘度及び
表面張力のものを選択する必要がある。粘度としては
0.003〜1Pが好ましく、さらに0.01〜0.1
Pがより好ましい。また、空隙部への液体の注入状態を
より観察しやすくするために、液体に着色物や蛍光物質
等を添加してもよい。The liquid used for the inspection is not particularly limited, but it has an appropriate viscosity and surface tension in consideration of the materials of the insulating support substrate and the insulating film-like adhesive, and the space between voids. Must be selected. The viscosity is preferably 0.003 to 1 P, more preferably 0.01 to 0.1
P is more preferred. Further, in order to make the injection state of the liquid into the voids easier to observe, a coloring matter, a fluorescent substance or the like may be added to the liquid.
【0013】半導体パッケ−ジ用チップ支持基板を使用
して半導体パッケ−ジを製造する一例としては、まず、
半導体パッケ−ジ用チップ支持基板の絶縁性フィルム状
接着材面に半導体チップを搭載する。このとき、絶縁性
フィルム状接着材のチップ搭載面に接着機能がある場合
は、そのまま搭載することも可能であるが、ペースト状
のダイボンド接着材を併用することもできる。次に半導
体チップ電極を支持基板のインナ−接続部とワイヤーボ
ンディング等により接続する。さらに半導体チップの少
なくとも半導体チップ電極面を樹脂封止し、アウター接
続部にはんだボールを搭載することにより半導体パッケ
−ジを製造することができる。As an example of manufacturing a semiconductor package using a semiconductor package chip support substrate, first,
A semiconductor chip is mounted on the surface of the insulating film-like adhesive material of the semiconductor package chip support substrate. At this time, if the chip mounting surface of the insulating film adhesive has an adhesive function, it can be mounted as it is, but a paste die-bonding adhesive can also be used together. Next, the semiconductor chip electrode is connected to the inner connecting portion of the supporting substrate by wire bonding or the like. Further, at least the semiconductor chip electrode surface of the semiconductor chip is resin-sealed, and solder balls are mounted on the outer connecting portions, whereby a semiconductor package can be manufactured.
【0014】[0014]
【実施例】図1及び図2により、本発明の一実施例につ
いて説明する。ポリイミド接着材をポリイミドフィルム
の両面に塗布した、厚さ0.07mmのポリイミドボン
ディングシート1に、アウター接続部3及び貫通穴(ベ
ントホール)9をドリル加工で形成する。次に厚さ0.
018mmの銅箔(日本電解製、商品名:SLPー1
8)を接着後、インナー接続部及び展開配線2を通常の
エッチング法で形成する。さらに、露出している配線に
無電解ニッケルめっき(膜厚:5μm)、無電解金めっ
き(膜厚:0.8μm)を順次施す(不図示)。ここで
は、無電解めっきを使用したが、電解めっきを用いても
よい。次に打ち抜き金型を用いてフレーム状に打ち抜
き、複数組のインナー接続部、展開配線、アウター接続
部を形成した支持基板を準備する(図2a)。支持基板
の作製方法として市販の2層(銅/ポリイミド)フレキ
シブル基板のポリイミドを、レーザ加工によりアウター
接続部穴等を形成する方法でもよい。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to FIGS. An outer connecting portion 3 and a through hole (vent hole) 9 are formed by drilling in a polyimide bonding sheet 1 having a thickness of 0.07 mm in which both sides of a polyimide film are coated with a polyimide adhesive material. Next, thickness 0.
018mm copper foil (Nippon Electrolytics, trade name: SLP-1)
After 8) is adhered, the inner connection portion and the developed wiring 2 are formed by a usual etching method. Further, the exposed wiring is sequentially subjected to electroless nickel plating (film thickness: 5 μm) and electroless gold plating (film thickness: 0.8 μm) (not shown). Although electroless plating is used here, electrolytic plating may be used. Next, using a punching die, it is punched into a frame shape to prepare a support substrate on which a plurality of sets of inner connecting portions, developed wirings, and outer connecting portions are formed (Fig. 2a). As a method of manufacturing the support substrate, a commercially available two-layer (copper / polyimide) flexible substrate of polyimide may be used to form the outer connection hole and the like by laser processing.
【0015】次に支持基板の半導体チップ搭載領域に、
ダイボンドフィルム4(日立化成工業株式会社製、商品
名:DF−335、厚み0.015mm)を接着する
(図2b)。このようにして得られた支持基板のダイボ
ンドフィルム4の端面周辺部にオイル12(粘度0.0
5ポイズ)を垂らし、空隙の開口部よりオイル12を毛
細管現象を利用して注入する(図1)。オイル12が支
持基板の貫通穴9までに達する時間を測定し、3分以内
のものをAグループ(テント状態良好なもの)、5分以
内のものをBグループ(テント状態やや悪いもの)、そ
れ以上のものをCグループ(テント状態悪いもの)と
し、貼付条件等を変えて3種類の貼付状態のサンプルを
用意する。次に各グループのサンプルに対し、接着した
ダイボンドフィルム上に無銀ペースト(日立化成工業株
式会社製、商品名:EN−4322)を用いて、半導体
チップ6を支持基板の所定の位置に接着し、180℃、
1時間のアフターキュアを行い、ダイボンドフィルムと
無銀ペーストを硬化させる。さらに、半導体チップ電極
とインナー接続部を、金ワイヤ5をボンディングして電
気的に接続する(図2c)。このようにして形成したも
のをトランスファモールド金型に装填し、半導体封止用
エポキシ樹脂7(日立化成工業(株)製、商品名:CL
−7700)を用いて各々封止する(図2d)。その
後、アウター接続部にはんだボール8を配置し溶融させ
(図2e)、パンチにより個々のパッケージに分離し半
導体パッケージが得られる(図2f)。以上のように製
造された3種類の半導体パッケージに対し、4日間吸湿
後(30℃/75%RH)にIRリフロー(230℃、
5秒)を行う試験を2サイクル行った。その結果を次表
に示す。Next, in the semiconductor chip mounting area of the support substrate,
Die bond film 4 (manufactured by Hitachi Chemical Co., Ltd., trade name: DF-335, thickness 0.015 mm) is adhered (Fig. 2b). The oil 12 (with a viscosity of 0.0
5 poises) and oil 12 is injected from the opening of the void by utilizing the capillary phenomenon (FIG. 1). The time taken for the oil 12 to reach the through hole 9 of the support substrate was measured, and those within 3 minutes were group A (those in good tent condition) and those within 5 minutes were group B (somewhat bad tent condition). The above is set as C group (the tent is in a bad state), and three kinds of samples in the attached state are prepared by changing the attaching conditions. Next, with respect to the samples of each group, the semiconductor chip 6 was adhered to a predetermined position of the supporting substrate using a silver-free paste (manufactured by Hitachi Chemical Co., Ltd., trade name: EN-4322) on the adhered die bond film. , 180 ℃,
After-curing for 1 hour, the die bond film and the silver-free paste are cured. Further, the semiconductor chip electrode and the inner connecting portion are electrically connected by bonding the gold wire 5 (FIG. 2c). The thus-formed product is loaded into a transfer mold die, and epoxy resin 7 for semiconductor encapsulation (manufactured by Hitachi Chemical Co., Ltd., trade name: CL
-7700) for sealing (FIG. 2d). After that, the solder balls 8 are placed on the outer connection portion and melted (FIG. 2e), and separated into individual packages by punching to obtain semiconductor packages (FIG. 2f). After three days of moisture absorption (30 ° C / 75% RH), IR reflow (230 ° C,
The test which performs 5 seconds) was performed for 2 cycles. The results are shown in the table below.
【0016】リフロークラック発生数
グル−プ 1回目リフロ− 2回目リフロ−
───────────────────────
A 0/7 0/7
B 2/7 3/7
C 3/3 3/3
───────────────────────
このように、本発明の検査法によって、ダイボンドフィ
ルムの貼付状態が良好と判断されたAグループのサンプ
ルが、良好な信頼性を確保しており、本検査法が有効な
手段であることが確認できた。Number of occurrences of reflow cracks Group 1st reflow 2nd reflow ─────────────────────── A 0/7 0/7 B 2 / 7 3/7 C 3/3 3/3 ─────────────────────── In this way, according to the inspection method of the present invention, the die bond film is attached. It was confirmed that the sample of group A, which was judged to be in good condition, had good reliability and that this test method was an effective means.
【0017】[0017]
a.絶縁性支持基板の一表面に複数組の配線(少なくと
も半導体チップ電極と接続するインナ−接続部及び半導
体チップ搭載領域部を有す)を形成し、
b.絶縁性支持基板の、絶縁性支持基板の配線が形成さ
れている箇所であってインナ−接続部と導通するアウタ
−接続部が設けらる箇所に開口を設け、
c.絶縁性支持基板の配線のない半導体チップ搭載領域
に、1個以上の貫通穴を設け、
d.配線の半導体チップ搭載領域部を含めて半導体チッ
プが搭載される箇所に絶縁性フィルムを形成し、
e.半導体チップを、支持基板のインナ−接続部が設け
られている面に接着し、
f.半導体チップ電極を基板のインナ−接続部とワイヤ
ーボンディングにより接続し、
g.半導体チップの少なくとも半導体チップ電極面を樹
脂封止して製造する半導体パッケージでは、高い信頼性
を確保するためには、絶縁性フィルム状接着材を支持基
板に貼付けた状態が重要であり、貫通穴(ベントホー
ル)の機能を充分に活用するために、絶縁性フィルム状
接着材を配線間にテント状に貼付け、絶縁性フィルム状
接着材と支持基板間に空隙を形成する必要がある。本発
明によって、絶縁性フィルム状接着材の貼付状態の善し
悪しを、短時間でかつ容易に判断でき、信頼性の高い小
型半導体パッケ−ジを製造するための支持基板の検査
が、大幅にスピードアップされた。a. Forming a plurality of sets of wirings (having at least an inner connecting portion for connecting to a semiconductor chip electrode and a semiconductor chip mounting region portion) on one surface of the insulating support substrate; b. An opening is provided in a portion of the insulating support substrate where the wiring of the insulating support substrate is formed and where an outer connecting portion that is electrically connected to the inner connecting portion is provided, c. Providing one or more through holes in the non-wiring semiconductor chip mounting area of the insulating support substrate, d. Forming an insulative film in a place where a semiconductor chip is mounted, including a semiconductor chip mounting area part of wiring; e. Adhering the semiconductor chip to the surface of the support substrate on which the inner connection portion is provided, f. Connecting the semiconductor chip electrode to the inner connection portion of the substrate by wire bonding, g. In a semiconductor package manufactured by sealing at least the semiconductor chip electrode surface of a semiconductor chip with a resin, it is important to attach an insulating film adhesive to the support substrate to ensure high reliability. In order to fully utilize the function of the (vent hole), it is necessary to attach the insulating film adhesive material in a tent shape between the wirings to form a gap between the insulating film adhesive material and the supporting substrate. According to the present invention, the adhering state of the insulating film adhesive can be easily judged in a short time, and the inspection of the supporting substrate for manufacturing a highly reliable small semiconductor package is significantly speeded up. Was done.
【図1】本発明の1実施例を示す平面図である。FIG. 1 is a plan view showing an embodiment of the present invention.
【図2】本発明の対象となる、半導体パッケージ製造工
程を示す断面図である。FIG. 2 is a cross-sectional view showing a semiconductor package manufacturing process which is an object of the present invention.
1 ポリイミドボンディングシート 2 インナー接続部及び展開配線 3 アウター接続部 4 ダイボンドフィルム 5 金ワイヤ 6 半導体チップ 7 半導体封止用エポキシ樹脂 8 はんだボール 9 貫通穴(ベントホール) 10 無銀ペースト 11 半導体パッケージ領域 12 オイル 1 Polyimide bonding sheet 2 Inner connection part and development wiring 3 Outer connection part 4 die bond film 5 gold wire 6 semiconductor chips 7 Epoxy resin for semiconductor encapsulation 8 solder balls 9 Through holes (vent holes) 10 Silver-free paste 11 Semiconductor package area 12 oil
───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 平10−135247(JP,A) 特開 平10−163256(JP,A) 特開 平10−189820(JP,A) 特開 平9−148475(JP,A) 特開 平10−223795(JP,A) 国際公開98/19338(WO,A1) (58)調査した分野(Int.Cl.7,DB名) H01L 21/52 H01L 21/66 H01L 23/12 501 H01L 21/60 301 H01L 21/60 311 ─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-10-135247 (JP, A) JP-A-10-163256 (JP, A) JP-A-10-189820 (JP, A) JP-A-9- 148475 (JP, A) JP-A-10-223795 (JP, A) International Publication 98/19338 (WO, A1) (58) Fields investigated (Int.Cl. 7 , DB name) H01L 21/52 H01L 21 / 66 H01L 23/12 501 H01L 21/60 301 H01L 21/60 311
Claims (2)
プ搭載領域を有する配線が2以上形成されており、前記
配線は前記半導体チップ搭載領域に半導体チップを絶縁
性フィルム状接着材を介して搭載した時前記絶縁性フィ
ルム状接着材の絶縁性支持基板対向面と前記2の配線端
面と絶縁性支持基板の前記表面とで空隙が形成されるよ
うに配置されており、 B.前記絶縁性支持基板には、前記空隙に面する箇所に
少なくとも1つの貫通孔が形成されており、 C.半導体チップ搭載領域の前記配線上を含めて半導体
チップが搭載される箇所に、絶縁性フィルム状接着材が
形成されている半導体パッケージ用支持基板の検査法で
あって、 D.前記空隙の開口部の一部から空隙内に液体を注入さ
せ、 E.液体が毛細管現象により前記貫通孔に達成する時間
を計測することにより、当該時間と、絶縁性フィルム状
接着材の貼付状態に応じてあらかじめ計測してカテゴリ
ー分けしてあった当該時間とを比較することで、当該半
導体パッケージ支持基板における絶縁性フィルム状接着
材の貼付状態の善し悪しを検査する ことを特徴とする基
板の検査方法。1. A. Wiring that having a semiconductor chip mounting area on one surface of the insulating support substrate is formed of two or more, the time the wire in which a semiconductor chip is mounted on the semiconductor chip mounting region through the insulating film adhesive material The insulating film adhesive is arranged so that a gap is formed between the surface of the insulating film adhesive facing the insulating support substrate, the wiring end surface of the second wiring, and the surface of the insulating support substrate. Wherein the insulating support substrate is at least one through hole is formed at a position that menses in the gap, C. A method for inspecting a supporting substrate for a semiconductor package, wherein an insulating film adhesive is formed on a portion where a semiconductor chip is mounted, including on the wiring in the semiconductor chip mounting region, and D. Liquid is injected into the void from a part of the opening of the void.
Then, E. Time for liquid to reach the through hole by capillary action
By measuring the time and the insulating film
Pre-measured according to the attachment status of the adhesive
-By comparing the time that was divided,
Insulating film-like bonding on conductor package support substrate
A board inspection method characterized by inspecting the adhering condition of materials .
求項1記載の基板の検査方法。2. The method for inspecting a substrate according to claim 1, wherein the viscosity of the liquid is 0.003 to 1P.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP34346296A JP3386967B2 (en) | 1996-12-24 | 1996-12-24 | Substrate inspection method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP34346296A JP3386967B2 (en) | 1996-12-24 | 1996-12-24 | Substrate inspection method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH10189790A JPH10189790A (en) | 1998-07-21 |
| JP3386967B2 true JP3386967B2 (en) | 2003-03-17 |
Family
ID=18361721
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP34346296A Expired - Fee Related JP3386967B2 (en) | 1996-12-24 | 1996-12-24 | Substrate inspection method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3386967B2 (en) |
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|---|---|---|---|---|
| CN112687629B (en) * | 2020-12-25 | 2024-02-23 | 上海易卜半导体有限公司 | Semiconductor packaging method, semiconductor component and electronic device containing same |
| CN112992699B (en) * | 2021-02-01 | 2024-03-22 | 上海易卜半导体有限公司 | Semiconductor packaging method, semiconductor assembly and electronic device comprising semiconductor assembly |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1998019338A1 (en) | 1996-10-30 | 1998-05-07 | Hitachi Chemical Company, Ltd. | Chip supporting substrate for semiconductor package, semiconductor device, and method for manufacturing them |
-
1996
- 1996-12-24 JP JP34346296A patent/JP3386967B2/en not_active Expired - Fee Related
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1998019338A1 (en) | 1996-10-30 | 1998-05-07 | Hitachi Chemical Company, Ltd. | Chip supporting substrate for semiconductor package, semiconductor device, and method for manufacturing them |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH10189790A (en) | 1998-07-21 |
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