JP3388916B2 - Recording device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a recording apparatus for recording an image on a recording medium using a line type print head.

[0002]

2. Description of the Related Art A conventional inkjet printer is mainly a serial printer which sequentially prints on a recording paper while moving a print head left and right. Also, as a printer using a line head having a heating element for one line, a thermal transfer method using a thermal head is well known.

Such a printer apparatus includes a formatter section for receiving PDL data sent from a host computer and developing it into an image to be actually printed, a mechanical section of the printer apparatus, and an engine section for controlling the mechanical section. It is divided into two parts.

[0004]

Generally, in the above-mentioned formatter section, when image data is read from an image memory for storing a print image and sent to the engine section for printing, the image data is increased in order to improve the printing efficiency. Read control is important.

Particularly in the case of a color printer having a plurality of line heads, the image memory is divided into a plurality of areas corresponding to each head, and the read address of the print data to be transferred to the head is switched page by page. It is outputting. The timing of such address switching is
Although it must be changed according to the length of the recording paper, the interval between the plurality of recording heads, etc., it is very difficult to perform the read control in consideration of all such conditions.

The present invention has been made in view of the above conventional example, and an object of the present invention is to provide a recording apparatus capable of efficiently reading and recording image data from a memory storing print image data.

Another object of the present invention is to read print image data from a memory corresponding to a recording medium of any size, and to print the print image data according to recording timings of a plurality of recording heads. It is an object of the present invention to provide a recording device that can transfer and record to a recording head.

[0008]

In order to achieve the above object, the recording apparatus of the present invention has the following constitution. That is,
A recording device for inputting print data from an external device and recording an image on a recording medium using a plurality of recording heads,
The print data is expanded into print image data and is associated with each of the plurality of recording heads , and a plurality of subordinate print jobs are recorded.
Storage means for storing at different addresses of a common memory, and a read start address and a read end address of print image data stored in association with each of the plurality of recording heads. The print image data is read from the address storage means corresponding to each of the recording heads and the address of the memory corresponding to the read start address to the read end address stored in the address storage means. Transfer means for transferring to the recording head, recording means for recording on the recording medium by the plurality of recording heads based on the print image data transferred by the transfer means, and recording is performed first among the plurality of recording heads. The address stored in the address storage means corresponding to the recording head Start address and a read end address out
And a means for sequentially transferring each of the lower-order plurality of bits to the address storage means of a recording head for subsequent recording in synchronization with the recording timing of the recording head. To do.

[0009]

In the above structure, the print data is expanded into the print image data and is associated with each of the plurality of recording heads so that the lower bits of the memory are common.
The read start address and the read end address of each of the print image data stored in different addresses are stored in association with each of the plurality of print heads. , The print image data is read from the memory addresses corresponding to the respective read start addresses to the read end addresses, and is transferred to each corresponding print head, and a plurality of print image data are transferred based on the transferred print image data. While recording on the recording medium by the recording head, the plurality of lower bits of the read start address and the read end address stored in the address storage means corresponding to the recording head to be recorded first among the plurality of recording heads.
In synchronism with the recording timing of the recording head, and sequentially transfers to the address storage means of the recording head for subsequent recording.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will now be described in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram showing a circuit configuration of a color printer apparatus having a full line recording head according to an ink jet system which is a typical embodiment of the present invention.
As shown in FIG. 1, a circuit of this printer device includes a formatter unit 1 for controlling communication with a host computer (hereinafter, referred to as a host), expansion into a bitmap RAM, and the like.
10 and an engine unit 150 that controls the recording head, various controls, a conveyance motor, and various sensors.

This is because the formatter section 110 has a circuit configuration corresponding to various applications (for example, a normal printer, a facsimile machine or a copying machine) in consideration of a difference in the interface with the host and a difference in the image processing method. This is because the engine section 150 aims at reducing the difference depending on the application and reducing the cost by standardizing it so that any application can be supported.

In the present embodiment, the functional division of the formatter unit 110 and the engine unit 150 is determined as follows. (1) Function of formatter unit-Interface with host-Analysis of command (command) sent from host-Bitmap RA of recording data based on the above command
Expansion to M, control of operation panel, control of control box (described later), interface with engine unit 150, optional control: control of recording paper supply unit (option IN), control of recording paper discharge unit (option OUT) ( 2) Engine function, interface with formatter 110, ink supply system control, recording paper transport system control, data transfer control to print head, heater energization control to print head, temperature management, clock function, backup memory Function / Recording paper width detection function To realize these functions, the following circuit configuration is required.

In FIG. 1, a formatter unit 110 includes a CPU-F111 for executing a control program, a ROM 112 for storing the control program, a system RAM 113 required for executing the program, an IFCNT 114 required for communication with the host, and a host. Bitmap RAM for recording the bit map data of the transmitted recording contents
115, a dedicated circuit GAF 116 that controls the bitmap RAM 115 and communicates with the engine unit 150, an emulation RO for analyzing print data from the host
M (E-ROM) 117, character generator (CG-ROM) 118 for converting character code data into bitmap data, memory card 119 used as an external storage device, IO port to interface with the above-mentioned optional function 120, an operation panel 1 including a user interface and keys for performing various operations and an LCD for displaying messages from the device
21.

Further, reference numeral 122 is a control box which serves as a user interface for performing various instruction operations when image recording is performed standalone using image data stored in the memory card 119 without connecting the printer device to a host. Is. Further, 123 and 124 are input / output interfaces (option (input) IN, option (output) OUT) of various additional devices which are optionally connected to the printer device.
In this embodiment, the option IN 123 is connected to a recording paper supply unit described later, and the option OUT 124 is connected to a recording paper discharge unit described later.

Next, the engine section 150 will be described.

As shown in FIG. 1, the engine section 150 is composed of an engine circuit 160 whose main purpose is to convey recording paper, and an engine circuit 180 whose main purpose is to control drive of the recording head.

The engine section 150 is a ROM for storing a control program and an R used as a work area for executing the ROM.
A CPU-E161 including an AM and a port (PORT) for inputting a sensor to be described later and an A / D converter for converting an analog input from the port into digital data, and executing a control program to perform various control processes. CP
RAM 16 used for program execution of U-E161
2. EEPR for recording unevenness correction data of recording head
An OM 163, a clock (RTC) 164, and a dedicated circuit GAE 165 for creating test record data and communicating with the formatter unit 110 are included. Further, 171 is a sensor that detects the position of the recording sheet, and 172 is a conveyance motor that conveys the recording sheet.

The engine circuit 180 is used for the recording head 1.
90 drive control, control of the motor 191 for moving the recording head and the cap (not shown) to cap the ink ejection nozzles of the recording head 190 when the recording operation is not performed, and position detection and recording of the cap. A dedicated circuit GAE181 for controlling the sensor 192 for detecting the position of the head is included.

FIG. 2 shows the printer device 10 described with reference to FIG.
It is a structure sectional view showing a schematic structure of 0. FIG. 2 shows a configuration in which a control box 122, a recording paper supply unit 130 that uses roll paper as recording paper, and a recording paper discharge unit 131 that includes a cutter that cuts the rolled paper after recording are incorporated in the printer device 100. Shows. Further, the engine circuit 160 is mounted on the apparatus as shown in FIG.
Divided into 160 and 180 parts.

Further, 190Y is a full line recording head (Y head) for recording using yellow (Y) ink, and 190M is a full line recording head (M for recording with magenta (M) ink. Head), 190
C is a full line recording head (C head) for recording using cyan (C) ink, and 190K is black (K).
Is a full-line recording head (K head) that performs recording using the above ink, and is arranged along the conveyance direction of the recording paper.

Further, 171a is a recording paper supply unit 130.
A signal (TOF1) by detecting the leading edge of the recording paper from the black lines added at regular intervals to the roll paper supplied from
The sensor 171b detects the leading edge of the recording paper from the black line of the roll paper after the recording is finished, and outputs a signal (TOF
A sensor 173 for generating 2) is a conveyor belt, which is rotationally driven by the rotation of the conveyor motor 172, and the movement of the conveyor belt 173 conveys the recording paper (recording medium) placed on the belt 173. .

[Explanation of the operation of the formatter unit 110] The operation of the formatter unit 110 is as follows: capture of print data from the host computer, analysis, bitmap RAM
The main functions are expansion of print image data to 115 and communication with the engine unit 150.

There are many technical data on the acquisition of print data from the host computer, analysis, and expansion to the bit map RAM, which is a known technique. The description will focus on the dedicated circuit GAF116 that controls the map RAM.

FIG. 3 shows the formatter unit 110 of this embodiment.
3 shows an internal block diagram of the GAF 116 of FIG.

The function of the GAF 116 is the system RAM 1
13 control (system controller 1403), DRA
M refresh control (refresh circuit 1404),
The engine control (engine control unit 1405) is the main function. Among these, the engine control unit 1405, which is a characteristic part of this embodiment, will be described.

FIG. 4 is a block diagram showing the structure of the engine control unit 1405.

As shown in FIG. 4, the engine control unit 140
Reference numeral 4 is composed of three circuit blocks. The first is the timing for generating the reference timing for data transfer (TI
MING) block 1500, the second is engine section 15
An ADRS block 1501 for generating an address for accessing the data to be transferred to 0 in the bitmap RAM 115 and reading the data is a DMA block 1502 for interfacing with the bitmap RAM 115.

First, the operation of the timing block 1500 will be described.

FIG. 5 shows a timing block circuit 1500.
FIG. 6 is a block diagram showing the configuration of FIG. 6, and FIG. 6 is a timing diagram showing its operation sequence.

The timing block 1500 is composed of a vertical synchronizing circuit 1600, a horizontal synchronizing circuit 1601, and a DMA request circuit 1602. (A) Vertical synchronization circuit 1600 In the vertical synchronization circuit 1600, the data transfer request signal a-TRG * signal sent from the engine circuit 160 to a
-ENB * signal and Aa-ENB * signal are generated.
The Aa-ENB * signal becomes active (low level) at the fall of the a-TRG * signal, and becomes inactive (high level) by the a-END * signal output from the ADRS block 1501. Also, the a-ENB * signal is
HSY after Aa-ENB * signal becomes inactive
It becomes inactive (high level) in synchronization with the NC signal (print sync signal for one line). This is Aa-EN
This is because the B * signal is a signal requesting data for DMA and operates independently of the horizontal synchronization, whereas the a-ENB * signal indicates the print page length and it is necessary to perform horizontal synchronization. . Here, here, a-TRG * signal, a-E
The a- in the NB * signal indicates each color signal of K, C, M, and Y. (B) Horizontal synchronization circuit 1601 The horizontal synchronization circuit 1601 controls NBL and NWD to put "0" data on the left and right unprinted areas. Specifically, the NBL register value (NBL0 to NBL0
7) minutes of the DATACK signal (input from the engine circuit 160) is counted, and after the count is completed, HAEN which is a DMA request signal to the bitmap RAM 115.
B * signal is active. This HAENB * signal becomes active only during 16 clocks (16 bits) of the DATACK signal, and the NWD register value (N
This is repeated for WD0 to 7) minutes. At that time, a HALD * signal indicating that the data for four colors has been read from the bitmap RAM 115 is also output.

Here, when the value of NBL is "0", that is, when printing is performed from the nozzle at the right end of the head,
When the a-TRG * signal becomes active, DATAC
Data is read from the bitmap RAM 115 regardless of the K signal. This is because the timing of fetching data in the engine unit 150 is performed at the rising edge of the DATACK signal, while the data transfer is DA
It is changed at the falling edge of the TACK signal. Therefore, when the first DATACK signal comes, bit 15
This is because the data in (b15) must have already been output. (C) DMA request circuit 1602 In the DMA request circuit 1602, the Aa-ENB described above is used.
The logical product of the * signal and the HAENB * signal is calculated, and the print data request signal a-HAS * signal for each color is output.
The IHDEND * signal is a signal indicating that one word (16 bits) worth of data has been read. As mentioned earlier, the HAENB * signal is active only for 16 clocks of DATACK,
The reading of the print data must be completed within this time.

Next, the address (ADRS) block 15
01 will be described.

The ADRS block 1501 is an address generator for DMA. Addresses for four colors are sequentially output based on the HAENB * signal from the timing block 1500. When the DMA transfer for one page is completed, the a-END * signal is sent to the timing block 1500.
Output to.

Next, the DMA block 1502 will be described.

The DMA block 1502 has a bus arbitration function D which controls access to the bitmap RAM 115.
It is a circuit that realizes a RAM control function and a data transfer function that performs parallel-to-serial conversion of data from the bitmap RAM 115 read by the DRAM control unit and transfers the data in synchronization with the DATACK signal sent from the engine unit 150.

With the above operation, the print head 190
The print data is transferred to and the high quality color image can be printed.

Next, the structure of the address block 1501 of the engine control unit 1404 of the formatter unit 110 will be described. Before describing the operation here in detail, the outline of the present embodiment will be briefly described below.

In this embodiment, in order to support the double buffer print method while performing color printing,
The number of latch circuits for storing the data transfer start address (TOPA) and the data transfer end address (ENDA) of the bit map RAM 115 is equal to the number of recording heads (here, 4). Then, when printing is started, TOF1 which is the absolute position detection signal at the beginning of the recording paper
The signal becomes active. The start address and the end address for the first print data are latched in the K latch circuits 720 and 721 in synchronization with the signal from this sensor.

Next, the recording paper is conveyed, and K-ENB showing the data transfer timing of the first head (K head).
* The signal becomes active. At this time, address data is transferred from the first latch circuit 720 to the address generation circuit 728, and at the same time, the start address and end address for the second head are latched in the C-latch circuits 722 and 723.

Next, the recording paper is conveyed, and C-EN showing the data transfer timing of the second head (C-head).
The B * signal becomes active. At this time, address data is transferred from the second latch circuit 722 to the address generation circuit 731, and at the same time, the start address and end address for the third head are M-latch circuits 724, 72.
Latched to 5. Hereinafter, the same operation is repeated.

By this operation, the change in the start address and the end address is the distance between the signal from the TOF 171a and the first head, or the distance between the heads, whichever is longer, whichever is the longer, and the minimum print length in the double buffer printing method is recorded. If the paper is longer than that, you can print correctly.

FIG. 7 shows the address block 15 of this embodiment.
It is a circuit diagram which shows the structure of 01.

Reference numeral 720 is a K-latch circuit for setting the final address (ENDA1 to 19) of black data in the bit map RAM 115, which is set by the CPU-F.
Reference numeral 721 is a K-latch circuit for storing the top address (TOPA1 to 19) of black data which is also set by the CPU-F. Similarly, the C-latch circuit 722 stores the final address of cyan data, and the C-latch circuit 723 stores the start address of cyan data. Below, M-
Latch circuits 724, 725, Y-latch circuits 726, 7
The same applies to 27. 728, 731, 734
Each of 737 is an a-address generation circuit that generates a read address of each color in the bitmap RAM 115. Each of 729, 732, 735, and 738 is an a-latch circuit for storing the head address (TOPA1 to 19) of each color. 730,733,7
36 and 739 are a-address comparison circuits that compare the 19-bit read address output from the a-address generation circuit with the holding values of the a-latch circuits 729, 732, 735, and 738, respectively. When these comparison results are in agreement, a coincidence signal a-corresponding to each color
END * is output. An address selection circuit 740 sequentially outputs four addresses corresponding to each color. Here, HA1 to 20 indicate addresses for accessing the bit map RAM 115 by DMA, and AB1 to
Reference numeral 20 denotes an address for the CPU-F to access the bitmap RAM 115, and HA1 to 20 are a-HAS * input from the timing block 1500.
According to the signal, aHA1 to 19 input from the a-address generation circuit are selected, and high-order bits corresponding to each color are added to this to output a 20-bit address.

Here, print data and bitmap RAM
The relationship with the address of 115 will be described.

FIG. 8 is a diagram for explaining a data transfer sequence for reading data from the bit map RAM 115 and transferring the data.

In order to print, the start address (TOPA) for data transfer and the end address (END
A) and transfer data amount (word number: NWD) need to be specified.

First, the case of designating the last address will be described.

In the case of the printer of this embodiment, since the bottom line of the recording paper is set to be printed and output first, the print data is transferred as shown in (END) in FIG.
It is necessary to start from the address (A-1) ($ 4xxxxx). Thereafter, the a-address generation circuit counts the last address by -1, and when the output of the address generation circuit becomes equal to the top address (TOPA), the a-address comparison circuit transfers the data for one page. The a-END * signal indicating that the process is completed is output.
The a-END * signal is input to the timing block 1500, and the a-ENB * signal becomes inactive (high level) at this timing.

Due to the circuit configuration of the bit map RAM 115, it is generally not configured to use completely different addresses for each color, but only the upper few bits of the address of the bit map RAM 115 are changed and the lower bit is configured to have the same address. Target. Therefore, the latch circuits 720, 722, 724,
The start address (TOP
A) and the latch circuits 721, 723, 725, 727.
The lowermost common address (A1 to A1) of the bitmap RAM 115 is set as the final address (ENDA) set in
9) is set.

The printer of this embodiment is compatible with the double buffer print system. This double-buffer printing method means that the first page has a 1st buffer (for example, black data is $ 400000 to 4FFFF).
If stored by address F, start from $ 400000
43FFFF address: $ indicates hexadecimal number) is transferred as print data, and the second page is a 2nd buffer ($ 440000-4 for black data described above).
The contents of up to 7FFFF address) are transferred as print data, and thereafter, the third page is a 1st buffer, the fourth page is a 2nd buffer, and so on. The feature of this method is that the CPU-F can rewrite the contents of the 2nd buffer while transferring the contents of the 1st buffer. Therefore, the print contents can be changed page by page, and the added value of the printer can be greatly increased.

In order to realize this function, the CPU-F rewrites the contents of the bitmap RAM 115 during printing, and after this rewriting is completed, the GAF is rewritten.
The contents of the 116 TOPA and ENDA registers must be rewritten. Further, page management in the CPU-F is performed based on a signal from the TOF sensor 171a.

As shown in FIG. 6, the TOPA and ENDA are taken in when the TOF 171a becomes active. That is, this is performed by the K-latch circuit 720 and the K-latch circuit 721 of the GAF 116 shown in FIG. After this, GAF 116 activates K-ENB *,
ENDA and TOPA are loaded into each of the K-address generation circuit 728 and the K-latch circuit 729. In addition, K-EN
When B * becomes active, C-latch circuit 722 and C
-To each of the latch circuits 723, TOPA and ENDA
Capture each of. By this operation, the K-latch circuit 720 and the K-latch circuit 721 form the bitmap RAM.
The read operation of 115 is released, and the next TOF 171 is released.
When the values of TOPA and ENDA arrive at the timing of a, their contents are rewritten.

Next, when C-ENB * becomes active, the contents of the C-latch circuit 722 are taken into the C-address generation circuit 731 and the M-latch circuit 724. Furthermore, the contents of the C-latch circuit 723 are
32 and the M-latch circuit 725. As a result, cyan data is sequentially read from the bitmap RAM 115 from ENDA to TOPA. Next, ME
When NB * becomes active, the contents of the M-latch circuit 724 change the contents of the M-address generation circuit 734 and the Y-latch circuit 7.
26, and the content of the M-latch circuit 725 is further captured by the M-latch circuit 735 and the Y-latch circuit 727. Then, when the Y-ENB * signal becomes active, the contents of the Y-latch circuit 726 are taken into the Y-address generation circuit 737 and the contents of the Y-latch circuit 727 are taken into the Y-latch circuit 738.

Here, the storage address of the black (K) data in the bit map RAM 115 is from $ 400000.
$ 4FFFFF address, cyan data storage address is $
500000-5FFFFF address, magenta data storage address $ 600000-6FFFFF address, and yellow data storage address $ 700000-7
The address is FFFFF.

By the above operation, the TOF171a (TOF171a
From the input timing of F1) to the first print head (K
The double buffer operation can be correctly performed as long as the recording paper has a length greater than the distance to the head or the gap between the heads, whichever is longer. If printing is performed without performing the double buffer operation, the minimum printable length of one page is the distance from the TOF 171a to the final print head (Y head). If it is less than that, bitmap RAM1 for each color
The address setting of 15 is misaligned and the double buffer operation cannot be performed.

In this way, TOPA and ENDA of each color are
After fetching the value of R, the a-address generation circuits 728, 731, 734, and 737 output the address of the bit map RAM 115 based on the HAENB * signal transferred from the timing block 1500.
The print data is read from the AM 115.

The above is the basic operation of the double buffer printing, but when this method is actually adopted, the bitmap RAM 115 requires a storage capacity of three pages of the recording medium.

FIG. 9 is a diagram showing an operation example of double buffer printing.

In the case of a color printer, print heads for four colors (KCMY) are required, so that a gap occurs between each head. Depending on the size of the recording paper, two pages of recording paper may fit in the gap between the heads. Therefore, two pages of buffer during data transfer and one page of buffer for preparation for next printing are required. Therefore, the bitmap RAM 115 having a storage capacity for three pages of recording paper is required. Furthermore, if the length of the recording paper is short, it will be 4 pages, 5 pages, and bitmap R
The capacity of the AM 115 is required, but in this case, there is no problem because the required capacity per page of the bitmap RAM 115 is also small.

Therefore, in order to smoothly operate the above-mentioned double buffer printing, the bitmap RAM 115
Storage capacity of (the distance from the sensor of the TOF 171a to the final print head (Y head)) × 3 or more.

Next, the configuration of each circuit in FIG. 7 will be described. (A) a-Address generation circuit The a-address generation circuit is a circuit that generates an address of the bitmap RAM 115 in which print data for each color is stored. During the printing operation, the HAENB * signal generated by the timing block 1500 and the a-EN
The B * signal is input, the logical product of the signals is calculated, the count value of the a-address generation circuit is counted by -1, and the read address of the print data for each color is generated. (B) a-address comparison circuit The a-address comparison circuit compares the output value (read address) of the a-address generation circuit with the a-latch circuit (729,
732, 735, 738) is compared with the data (TOPA) to check whether or not they match. If these address data match, a-END
* The signal becomes active, indicating that the data transfer for one page of that color is completed. (C) Address selection circuit 740 The address selection circuit 740 is the timing block 150.
It is a circuit that selects any of four address signals (KHA, CHA, MHA, YHA1 to 19) by the a-HAS * signal generated by 0.

Next, the DMA block will be described.

FIG. 10 is a block diagram showing the structure of the DMA circuit 1502.

As shown in FIG. 10, the DMA circuit 1502
Is composed of a bus arbitration circuit 710, a DRAM control circuit 711 and a data transfer circuit 712.

<Bus Arbitration Circuit 710> Bitmap RA
For access to M115, CP of the formatter unit 110
U / F read / write access, DMA operation read access, and bit map RAM 115
There are three types of access for performing the refresh operation. Each operation is independent, and these three accesses may occur to the bitmap RAM 115 at the same time. The bus arbitration circuit 710 is a circuit that makes these arbitrations and sequentially gives access rights to the bit map RAM 115.

<DRAM Control Circuit 711> The DRAM control circuit 711 is a bitmap RAM 115 (DRAM).
Is a circuit for generating a control signal for.

<Data Transfer Circuit 712> The data transfer circuit 712 of this embodiment is cleared by the INT * signal output in synchronization with the horizontal synchronizing signal (HSYNC).
The a-HAS * signal becomes a low level while 16-bit data of each color is read from the bitmap RAM 115 by DMA and transferred, and the DFET * signal is DRA.
It is a 16-bit data latch signal output from the M control circuit 711.

Here, the timing of transferring 16-bit data from the formatter unit 110 to the engine unit 150 is from the HALD * signal output after counting the value of NBL, as described above with reference to FIG. . Therefore, before this HALD * signal is output, a-DA
"0" is transferred as the TA signal.

At the timing when the HALD * signal is output and the print data is transferred, the DRAM control circuit 71
The print data is output from 1 to HD0 to 15 signals, and HD0 to 15 are stored in the data transfer circuit 712 by the DFET * signal for each color signal. When the print data for four colors is stored in the data transfer circuit 712 in this way, the HALD * signal becomes active, the 16-bit data is converted into serial data, and synchronized with the DATACK signal transferred from the engine unit 150. And outputs the serial data as an a-DATA signal. By this operation, the print data is transferred to the engine unit 150.

The above is the operation of the DMA block.

The present invention is provided with a means (for example, an electrothermal converter or a laser beam) for generating thermal energy as energy used for ejecting ink, particularly in the ink jet recording system, and the thermal energy The printing apparatus of the type that causes a change in the state of ink has been described. According to such a method, the recording density is increased,
High definition can be achieved.

With regard to its typical structure and principle, see, for example, US Pat. Nos. 4,723,129 and 4740.
What is done using the basic principles disclosed in 796 is preferred. This method can be applied to both the so-called on-demand type and the continuous type. In particular, in the case of the on-demand type, heat energy is generated in the electrothermal converter, and the heat acting surface of the recording head is This is effective because it causes film boiling, and as a result, bubbles in the liquid (ink) corresponding to this drive signal in a one-to-one correspondence can be formed. The liquid (ink) is ejected through the ejection openings by the growth and contraction of the bubbles to form at least one droplet. It is more preferable to make this drive signal in a pulse shape, because bubbles can be grown and contracted immediately and appropriately, and thus a liquid (ink) with excellent responsiveness can be achieved.

As the pulse-shaped drive signal, those described in US Pat. Nos. 4,463,359 and 4,345,262 are suitable. If the conditions described in US Pat. No. 4,313,124 of the invention relating to the rate of temperature rise on the heat acting surface are adopted, more excellent recording can be performed.

As the constitution of the recording head, in addition to the combination constitution of the ejection port, the liquid passage, and the electrothermal converter (the linear liquid passage or the right-angled liquid passage) as disclosed in the above-mentioned specifications, The present invention also includes configurations using US Pat. No. 4,558,333 and US Pat. No. 4,459,600, which disclose configurations in which the heat-acting surface is arranged in a bending region. In addition, for multiple electrothermal converters,
Japanese Unexamined Patent Publication No. 59-123670, which discloses a configuration in which a common slot is used as a discharge portion of the electrothermal converter, and Japanese Patent Laid-Open No. 59-63, which discloses a configuration in which an opening for absorbing a pressure wave of thermal energy is associated with the discharge portion. A configuration based on Japanese Patent No. 138461 may be used.

Further, as a full line type recording head having a length corresponding to the width of the maximum recording medium that can be recorded by the recording apparatus, the length can be increased by combining a plurality of recording heads as disclosed in the above-mentioned specification. Either of the structure satisfying the requirement or the structure as one recording head integrally formed may be used.

In addition, by being attached to the apparatus main body, it can be electrically connected to the apparatus main body and can be supplied with ink from the apparatus main body by a replaceable chip type recording head or the recording head itself. Alternatively, a cartridge type recording head provided with an ink tank may be used.

Further, it is preferable to add recovery means for the recording head, preliminary auxiliary means, etc., which are provided as a configuration of the recording apparatus of the present invention, because the effect of the present invention can be further stabilized. . Specific examples thereof include capping means, cleaning means, pressurizing or suctioning means for the recording head, preheating means using an electrothermal converter or another heating element or a combination thereof, and recording. It is also effective to perform a stable recording by performing a preliminary discharge mode in which another discharge is performed.

Further, the recording mode of the recording apparatus is not limited to the recording mode of only the mainstream color such as black, but the recording head may be integrally configured or a plurality of combinations may be used. Alternatively, the device may be provided with at least one of full-color mixed colors.

In the embodiments of the present invention described above, the ink is described as a liquid, but an ink that solidifies at room temperature or lower, or one that softens or liquefies at room temperature may be used, or In the inkjet method, it is common to control the temperature of the ink itself within a range of 30 ° C to 70 ° C to control the temperature of the ink so that the viscosity of the ink is within a stable ejection range. It is sufficient that the ink is liquid.

In addition, in order to positively prevent the temperature rise due to the thermal energy from being used as the energy for changing the state of the ink from the solid state to the liquid state,
Alternatively, in order to prevent the ink from evaporating, an ink that solidifies in a standing state and liquefies by heating may be used. In any case, by applying heat energy, such as ink that is liquefied by applying heat energy according to the recording signal and liquid ink is ejected, or that begins to solidify when it reaches the recording medium. The present invention can be applied to the case where an ink having a property of being liquefied for the first time is used. In such a case, the ink is retained as a liquid or solid in the recesses or through holes of the porous sheet as described in JP-A-54-56847 or JP-A-60-71260. It may be configured to face the electrothermal converter. In the present invention, the most effective one for each of the above-mentioned inks is to execute the above-mentioned film boiling method.

In addition, as a form of the recording apparatus according to the present invention, in addition to one provided integrally or separately as an image output terminal of information processing equipment such as a computer, a copying apparatus combined with a reader or the like, and further transmission / reception It may take the form of a facsimile machine having a function.

The present invention may be applied to a system composed of a plurality of devices or an apparatus composed of a single device. The present invention can also be achieved by supplying a program for implementing the present invention to a system or an apparatus.

As described above, according to the present embodiment, in the color printer using the line head, by adopting the double buffer printing method, the distance from the head of the recording paper (TOF171a) to the first print head, Alternatively, if the recording paper is longer than the gap distance between the heads, whichever is longer, printing can be efficiently performed.

[0085]

As described above, according to the present invention, there is an effect that the image data can be read out and recorded more efficiently than the memory storing the print image data.

Further, according to the present invention, the print image data can be read from the memory corresponding to the recording medium of any size, and the print image data is recorded according to the recording timing of the plurality of recording heads. The effect is that it can be transferred to the head for recording.

[0087]

[Brief description of drawings]

FIG. 1 is a block diagram showing a circuit configuration of a color printer apparatus having a full-line recording head according to an inkjet method, which is a typical embodiment of the present invention.

FIG. 2 is a side sectional view showing a schematic configuration of the printer device described in FIG.

FIG. 3 is a block diagram showing a configuration of a GAF 113 of a formatter unit of this embodiment.

FIG. 4 is a block diagram showing a configuration of an engine control unit 1404 of GAF 113.

FIG. 5 is a block diagram showing a configuration of a timing unit of an engine control unit.

FIG. 6 is a timing diagram showing an operation sequence of a timing section.

FIG. 7 is a block diagram showing a configuration of an address block of an engine control unit.

FIG. 8 is a diagram illustrating a data transfer sequence from a bitmap RAM in the present embodiment.

FIG. 9 is a diagram showing a positional relationship between heads of respective colors and recording paper when the double buffer printing method is carried out.

FIG. 10 is a block diagram showing a configuration of a DMA block of an engine control unit of the embodiment.

[Explanation of symbols]

110 Formatter part 113 system RAM 115 Bitmap RAM 116 GAF 150 engine 160,180 engine circuit 165,181 GAE 163 EEPROM 171a, 171b TOF sensor 172 Conveyor motor 190 inkjet head 710 bus arbitration circuit 711 DRAM control circuit 712 data transfer circuit

─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hideaki Kishida 5540-11 Sakate-cho, Mizukaido-shi, Ibaraki Canon Aptex Co., Ltd. (56) Reference JP-A-4-344271 (JP, A) JP-A-7-152505 (JP, A) (58) Fields surveyed (Int.Cl. ⁷ , DB name) B41J 5/30 B41J 2/21 G06F 3/12

Claims (5)

(57) [Claims] 1. A recording apparatus for inputting print data from an external device and recording an image on a recording medium using a plurality of recording heads, wherein the print data is expanded into print image data, and the plurality of recording data are recorded. in association with each of the heads, several underlying bi
Storage means for storing different addresses in a common memory, and a read start address and a read end address for each of the print image data stored in association with each of the plurality of recording heads. The print image data is read from the address storage unit corresponding to each of the recording heads and the address of the memory corresponding to the read start address to the read end address stored in the address storage unit. Transfer means for transferring to the recording head; recording means for recording on the recording medium by the plurality of recording heads based on the print image data transferred by the transfer means; Before being stored in the address storage means corresponding to the recording head to be made Each of the read start address and read end address
A recording device comprising: a plurality of lower bits that are sequentially transferred to the address storage means of a recording head for subsequent recording in synchronization with the recording timing of the recording head. 2. A sensor for detecting the head of the recording medium, further comprising: a sensor for detecting the head of the recording medium; The recording apparatus according to claim 1, wherein the read start address and the read end address of the print image data to be printed are set. The method according to claim 3, wherein each of said plurality of recording heads, the recording apparatus according to claim 1 or 2, characterized in that a recording head for color recording which records a print image corresponding to each color. Wherein said plurality of recording heads, a recording apparatus according to any one of claims 1 to 3, characterized in that an ink jet recording head for recording by discharging ink. 5. The recording head is a recording head which ejects ink by utilizing thermal energy, and is provided with a thermal energy converter for generating thermal energy applied to the ink. Item 5. The recording device according to item 4 .