JP3389177B2 - Library and wiring method for placement and routing of integrated circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a placement and routing library for an integrated circuit and a wiring method, and more particularly to a placement and routing library for an integrated circuit for improving the wiring performance when automatically passing through wiring on a cell. And a wiring method.

[0002]

2. Description of the Related Art In the automatic design of a semiconductor integrated circuit device, when automatic wiring is performed for a chip including macros and standard cells, external macro wirings or standard wirings that pass through the wirings vulnerable to noise inside the macros or standard cells If the cell external wiring is laid, the macro or standard cell may malfunction. The operation of the macro or standard cell will be described below.

FIG. 18A shows an SRAM (Static Random).
Access Memory) Plan view showing automatic wiring of macro, Fig. 1
8B is an enlarged plan view of the memory cell portion of the SRAM macro. As shown in FIGS. 18A and 18B, S
Inside the RAM macro 104, there is a memory cell section 103 in which memory cells 103a are arranged in an array. Inside the memory cell section 103, the sources of the MOS transistors of the memory cell 103a are respectively connected in the Y-axis direction. A plurality of digit lines 102 extending in parallel with each other. An external macro wiring 105 is laid on the digit line 102 of the memory cell portion 103 in the same direction as the digit line 102. In order to read the data of the memory cell 103a, a minute potential difference on the digit line 102 is detected by a sense amplifier.
The RAM macro 104 may malfunction. here,
As shown in FIG. 18B, when the macro outer wiring 105 is laid on the digit line 102 in the same direction as the digit line 102, a large coupling capacitance is parasitic between the digit line 102 and the macro outer wiring 105. Therefore, noise occurs in the digit line 102 due to the influence of crosstalk, and S
The RAM macro 104 malfunctions.

As a countermeasure against this, conventionally, there is a method of automatically performing wiring by using a placement and routing library provided with a wiring prohibited area for prohibiting the wiring from passing through an area vulnerable to noise (for example, Japanese Patent Laid-Open No. Hei 4- No. 113652: Conventional example 1, JP-A-5-326706: Conventional example 2, JP-A-5-343523: Conventional example 3). Conventional Example 1
Wiring prohibited areas of the basic cells are arranged in accordance with the arrangement of the basic cells, and a rectangular area penetrating on the basic cells in one direction is generated as a wiring prohibited area of the cell, and wiring is performed. The generation time of the prohibited area and the amount of data are reduced. In the conventional example 2, a wiring pattern that does not violate the wiring prohibited area is manually designed and formed on a block having a wiring prohibited area in advance, and a wiring pattern is selected from this library and connected to a specific block. . In addition, in the conventional example 3, a dynamic circuit that holds an electric signal in a capacitor (for example, a DRAM (Dynami
In a macro cell including a cRandom Access Memory), an automatic wiring prohibited area is formed on the pattern of the dynamic circuit so that the wiring outside the cell is not automatically wired on the capacitor formed in the wiring aluminum of the dynamic circuit. As described above, in Conventional Examples 1 to 3, the area outside the cell wiring cannot pass by the automatic wiring,
The wiring prohibited area is set.

As an example of providing such a wiring prohibited area, an example in which a wiring prohibited area is provided in the SRAM macro is shown (prior art example 4). FIG. 19 is a plan view showing an SRAM macro having a wiring prohibited area. As shown in FIG.
The macro 104 has a memory cell section 103 having a plurality of digit lines 102 arranged in parallel with each other.
Then, the memory cell portion 10 including the digit line 102
By registering the entire upper part 3 as the wiring prohibited area 101 in the placement and routing library, the external macro wiring 105 is not laid in the wiring prohibited area 101 during automatic wiring. Therefore, it is prohibited to lay the external macro wiring on the digit line 102 in the same direction as the digit line, and the SRAM macro 1
Prevent the malfunction of 04.

FIG. 20 is a flow chart showing a method of automatically arranging a placement / wiring library including a wiring prohibited area. First, the layout of the SRAM macro is selected (step (hereinafter referred to as S) 101) and the coordinates for setting the wiring prohibited area are determined (S102). Then, the coordinate information of the determined wiring prohibited area is added (S1
03), a layout / wiring library for the SRAM macro is generated (S104). FIG. 19 shows an example of the placement and routing library including the wiring prohibited area generated here. next,
The placement and routing library including the wiring prohibited area created in step 104 and the placement and routing library of other standard cells or macros are selected (S105, S10).
6) Execute automatic placement and routing of chips. First, the placement position of a macro or standard cell is determined by automatic placement processing (S107). Then, the wiring is laid by avoiding the wiring prohibited area by the automatic wiring processing (S108), and the chip layout is obtained (S109).

The automatic wiring process performed in step 108 will be described below. FIG. 21 is a flowchart showing a program in the automatic wiring process. First,
The net to be routed first is selected (S111), and the route of the wiring to the end point is searched (S112). Next, it is confirmed whether or not there is a wiring prohibited area on the searched route (S1).
13). If there is a wiring prohibited area, step 11
In step 3, YES is selected, and a wiring that bypasses the wiring prohibited area is laid (S114). And step S again
At 112, the wiring route from the detoured position to the end point is searched for. On the other hand, if there is no wiring prohibited area in the searched route, NO is selected in step 113 and the wiring to the end point is laid (S115). Then step 1
Proceed to step 16 and confirm whether all nets are completely routed here. If there is an unrouted net, N
When O is selected, the process proceeds to step 117 to select the next net, and step 11 is performed until wiring of all nets is completed.
The process from 2 to step 116 is repeated. After confirming that the wiring has been completed for all nets, step 11
YES is selected in 6, and the automatic wiring process is completed.

As described above, in the wiring design of the conventional example 4, the outside macro area wiring is laid by bypassing the wiring prohibited area by automatically wiring using the placement and routing library including the wiring prohibited area. macro outer wires is prevented Rukoto laid in the same direction as the weak digit line noise.

Further, Japanese Patent Publication No. 2859195 discloses a technique of passing an external macro wiring over a memory cell portion without causing the SRAM macro to malfunction (conventional example 5). FIG. 23 is a diagram showing the layout of the memory cell portion of the semiconductor integrated circuit described in Conventional Example 5. A transfer gate 115, a latch 118, and a transfer gate 11 are provided between the digit line 111 of the layout wiring library and the digit line bar 112 of the inverted signal of the digit line.
6 is connected to the transfer gates 115 and 116.
A word line 113 is connected to the gate of the. Then, the wiring prohibited area 120 is provided only on the digit line 111 and the digit line bar 112, and a wiring area through which the automatic wiring can pass is formed between the digit line 111 and the digit line bar 112 forming a pair. Outer macro wiring 1
Passing 17. The outer macro wiring 117 passing between the digit lines intentionally gives the influence of the crosstalk from the outer macro wiring 117 to the digit line 111 and the digit line bar 112, so that the signal line which is the outer macro wiring 117 passes. Is possible. Also,
The wiring prohibited area 12 is formed so that the outside macro wiring 117 can pass also in the direction orthogonal to the digit line 111.
The outer macro wiring 1
A wiring area for passing 17 is secured.

FIG. 24 shows an example of the structure of a library to which the technique of Conventional Example 5 is applied. In the SRAM macro 104, Y
The memory cell unit 103 has a memory cell unit 103 in which a plurality of digit lines 102 extending in the axial direction and parallel to each other are laid.
A plurality of wiring prohibited areas 101 are respectively provided on the paired digit lines in 03. Then, in the wiring prohibited area 101, a slit having a constant gap in the X-axis direction is formed. In this SRAM macro 104,
When passing the macro outside wiring 105 on the memory cell portion 103 in the Y-axis direction which is the same direction as the digit line 102, the digit line 102 forming a pair and the digit line 1 forming a pair adjacent to the digit line 102.
It is laid in the wiring region of the gap 02. Further, the wiring prohibited area 101 has slits in the X-axis direction, and since the slits are wiring areas, the wiring is passed over the memory cell portion 103 also in the X-axis direction orthogonal to the digit line 102. be able to.

[0011]

However, when the wiring prohibited area is provided as in the conventional examples 1 to 4, there is a problem that the outside macro wiring is also prohibited from passing in the direction orthogonal to the digit line. . When the macro outer wiring passes in the direction orthogonal to the digit line, the coupling capacitance parasitic between the digit line and the macro outer wiring becomes small, so that the influence of crosstalk also becomes small. Therefore, in the direction orthogonal to the digit line, it may be desired to pass the outside macro wiring, but if it is set in the wiring prohibited area, the passage in the direction orthogonal to the digit line is also prohibited. 22 is a wiring prohibited area 1 shown in FIG.
FIG. 10 is a plan view showing a state in which a macro outer wire 105 is laid on 01. Even when it is desired to pass the macro outside wiring 105 over the memory cell portion 103 in the direction orthogonal to the digit line 102, the macro outside wiring 105 cannot pass through the wiring prohibited area 101 as shown in FIG. Since the memory cell portion 103 set to 101 is bypassed, there is a problem that the wiring property of the outside macro wiring 105 is deteriorated.

Further, in the conventional example 5, the external macro wiring 105 is used.
However, there is a problem that the wiring property is deteriorated when is locally concentrated. FIG. 25 is a plan view showing a state in which external macro wiring is concentrated in the SRAM macro of Conventional Example 5 shown in FIG. For the memory cell portion 103 of the SRAM macro 104 having a plurality of wiring prohibited areas 101 formed by forming slits on the digit lines 102 that form a pair in the X-axis direction,
The macro outer wiring 105 is formed in the direction orthogonal to the digit line 102.
When laying the cable, as shown in FIG.
If 05 is locally concentrated, the non-macro wiring 105 is diverted to the position of the fixed wiring area, which deteriorates the wiring performance.

Further, in order to eliminate the deterioration of the wiring property when the wiring is concentrated, FIG. 26 shows a case where a large number of slits are formed in the wiring prohibited region 101 in the direction orthogonal to the digit line 102 to form the wiring region. Show. As described above, when many external macro wirings 105 can pass over the memory cell portion 103 of the SRAM macro 104, the digit line 10
There is a problem in that the total amount of noise received by 2 becomes large and the SRAM macro 104 malfunctions.

The present invention has been made in view of the above problems, and an integrated circuit for improving the wiring property of the macro outside wiring by limiting and permitting the direction in which the macro outside wiring passes on the macro. An object is to provide a placement and routing library and a wiring method.

[0015]

The integrated circuit layout / wiring library according to the present invention is provided in a macro cell in an integrated circuit layout / wiring library used for automatic design of a semiconductor integrated circuit device . Passing through
If the wiring direction is weak,
It is characterized in that a wiring restricted area which is permitted only in the direction orthogonal to the line is provided.

A layout wiring for another integrated circuit according to the present invention.
Ibrari is used for automatic design of semiconductor integrated circuit devices
Stander in integrated circuit placement and routing library
Wiring that is provided in the cell and that passes through the inside
Wiring whose direction is weak to the noise inside the standard cell
Set a wiring restriction area that is allowed only in the direction orthogonal to
It is characterized by kicking .

[0017]

[0018]

[0019]

Further, in the wiring restricted area, the number of wires passing through the wiring restricted area may be restricted.

The integrated circuit wiring method according to the present invention comprises the steps of generating a placement / routing library having a wiring restricted area which is permitted only when the outside-cell wiring passes through in the direction orthogonal to the inside-cell wiring. An automatic placement step of deciding and arranging the placement position of the placement and routing library, and a step of checking whether or not the wiring direction permitted in the wiring restricted area and the direction of the out-of-cell wiring to be laid match. When the confirmation step matches, a wiring passing through the wiring restriction area is laid, and when the confirmation step does not match, a wiring bypassing the wiring restriction area is laid.

In the present invention, by providing the wiring restricted area in which the wiring is permitted in the direction orthogonal to the wiring direction vulnerable to noise in the cell, outside the cell in the direction orthogonal to the digit line which is less likely to be affected by noise. The wiring can be passed, and the wiring performance can be improved without causing the cell to malfunction.

Further, in the case where the number of wirings passing through the wiring restriction area is limited, when the wiring direction permitted in the wiring restriction area and the direction of the out-cell wiring to be laid coincide with each other. The number of wires outside the cell that have already passed through the wiring restricted area and the number of wires that can pass through the wiring restricted area are checked, and the number of wires that can pass through the wiring restricted area has already passed through the wiring restricted area. When the number of wirings is greater than the number of wirings, the cell outside wirings that pass through the wiring restriction area are laid, and the number of wirings that have already passed through the wiring restriction area matches the number of wirings that can pass through the wiring restriction area. When this is done, it is possible to lay out the cell outside wiring that bypasses the wiring restricted area.

[0024]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be specifically described below with reference to the accompanying drawings. Figure 3 shows SRA
It is a top view which shows the library for the automatic placement and routing of M macro. As shown in FIG. 3, the SRAM macro 4 includes a memory cell unit 3 in which memory cells (not shown) are arranged in an array.
In the memory cell portion 3, a plurality of digit lines 2 extending in the Y-axis direction are laid in parallel with each other. When the macro external wiring passing over the SRAM macro 4 is laid in the Y-axis direction which is the same direction as the digit line 2 on the digit line 2 vulnerable to noise of the memory cell portion 3, the SRAM macro 4 is affected by crosstalk. Malfunctions. Therefore, the memory cell unit 3 is permitted only in the X-axis direction, which is the direction of the wiring passing over the memory cell unit 3 and orthogonal to the digit line 2.
A wiring restriction area 1 is set which prohibits the laying of the macro outside wiring 5 in the Y-axis direction which is the same direction as the digit line 2. If the digit line 2 is laid in the X-axis direction,
In the wiring restricted area 1, the direction in which the passing wiring is permitted is the Y-axis direction, and passing through the wiring restricted area in the X-axis direction is prohibited.

FIG. 1 is a flow chart showing a wiring method for an integrated circuit according to the first embodiment of the present invention. First,
The layout of the SRAM macro in which the wiring is laid is selected (S1), and the coordinates of the area set as the wiring restricted area are determined (S2). The area set as the wiring restriction area is an area in which the direction of the wiring to be passed is desired to be restricted, such as a memory cell portion of SRAM. When the memory cell portion is set in the wiring restricted area, the wiring direction of the digit line in the SRAM macro which is the wiring restricted area is detected in order to determine the wiring direction limited to this wiring restricted area (S3).
When the digit line is wired in the X-axis direction, the wiring direction in the wiring restricted area is set to the Y-axis direction (S4). When the digit line is wired in the Y-axis direction, the wiring direction in the wiring restricted area is set to the X-axis direction (S5).

As described above, the coordinates of the wiring restricted area in which the direction of the wiring that can pass through and the information of the restricted wiring direction are taken into consideration (S6) to generate a placement / routing library of the SRAM macro including the wiring restricted area. (S7). From this, one example created is the placement and routing library shown in FIG.

Next, the layout / wiring library of the SRAM macro including the wiring restricted area and the layout / wiring library of other macros or standard cells are used (S8,
S9), automatic placement and routing of chips is executed. First, the automatic placement process is executed to determine the placement position of the macro or standard cell (S10), the automatic wiring process is executed,
Wiring is laid in consideration of the wiring direction restriction set in the wiring restriction area (S11), and a chip layout is obtained (S1).
2).

FIG. 4 is a plan view showing a state in which external macro wiring is laid using the SRAM macro placement and routing library shown in FIG. As shown in FIG. 4, the SRAM macro placement and routing library includes steps S1 to S7.
As a result, the memory cell section 3 in the SRAM macro 4 is set in the wiring restriction area 1, and the digit line 2 is wired in the Y-axis direction in the memory cell section 3 in the wiring restriction area 1. The wiring direction is limited to the X-axis direction which is the direction orthogonal to the digit line 2. In this way, the wiring restriction area 1 through which the wiring can pass only in the X-axis direction
A placement and routing library having is generated. When automatic placement and routing is executed using this placement and routing library and the macro outside wiring 5 is laid, the macro outside wiring 5 is only allowed to pass through the wiring restricted area 1 in the X-axis direction. The external macro wiring 5 can pass over the memory cell portion 3 in the X-axis direction. As a result, the memory cell unit 3
Is used as a wiring prohibited area, and when the macro external wiring passes through the memory cell portion 3 having the digit line 2 in the Y-axis direction in the X-axis direction, it is necessary to bypass the macro external wiring in comparison with the conventional example 4 which has a wiring property. Is improved.

The automatic wiring process of the first embodiment will be described in more detail below. FIG. 2 is a flowchart showing a program for performing the automatic wiring process of the first embodiment. First, select the net to be wired first (S21),
The wiring route to the end point is searched (S22). And
It is confirmed whether or not there is a wiring restricted area to be passed on the searched wiring route (S23). Then, if the wiring restricted area is confirmed, YES is selected in step 23, the process proceeds to step 24, and it is confirmed whether or not the direction in which the wiring is desired to pass and the wiring direction in the wiring restricted area match. If they match, YES is selected in step 24,
Proceeding to step 25, the wiring passing through the wiring restricted area is laid. On the other hand, if they do not match, NO is selected in step 24, and the process proceeds to step 26 to lay a wiring that bypasses the wiring restricted area. Step 25 or Step 2
After proceeding to step 6, the process returns to step 22 and the wiring route from the position where the wiring is laid to the end point is searched again. Also,
If there is no wiring restricted area to be passed on the wiring route in step 23, NO is selected in step 23 and the process proceeds to step 27 to confirm whether or not there is a wiring prohibited area in the wiring route. Then, if the wiring prohibited area exists, YES is selected in step 27, and the process proceeds to step 28 to lay a wiring that bypasses the wiring prohibited area. After step 28, the process returns to step 22 and this process is repeated until the wiring is laid up to the end point. On the other hand, if the wiring prohibited area does not exist, NO is selected in step 27 and the wiring is laid from the position where the wiring route is searched to the end point. After the wiring is laid up to the end point in step 29, the process proceeds to step 30, and it is searched whether or not all the nets are routed. If there is an unrouted net, NO is selected in step 30, Go to step 31, select the next net,
In steps 22 to 29, the wiring from the start point to the end point of the selected net is laid. Then, these steps are repeated until it is confirmed in step 30 that the wiring is completed for all the nets. Then, if it is confirmed that the wiring is completed for all the nets, YES is selected in step 30,
Complete the automatic wiring process.

FIG. 5 shows the result of the automatic wiring process of this embodiment.
It is a top view which shows the laid wiring. As shown in FIG. 5, a case where the wiring of the net from the start point 201 to the end point 202 is laid will be described. In the net 200 selected in step 21, when a wiring route from the start point 201 to the end point 202 is searched in step 22,
Wiring restricted area 2 from the start point 201 to the end point 202
03 exists (S23). Therefore, in step 23, Y
ES is selected and step 24 is proceeded to. Then, if it is confirmed whether the direction in which the wiring is to pass in the wiring restricted area 203 and the wiring direction limited in the wiring restricted area 203 match (S24), the direction in which the wiring restricted area 203 is to be passed is determined. The X-axis direction and the wiring direction limited by the wiring restriction region 203 are also the X-axis direction and coincide with each other. Therefore, YES is selected in step 24, and the wiring passing from the starting point 201 through the wiring restricted area 203 is the first passing point 204.
Is laid up (S25).

Next, returning to step 22, the wiring route from the position of the first passage point 204 to the end point 202 is searched again. When searching from the position of the first passage point 204 to the end point 202, the wiring restricted area 205 exists. Therefore, YES is selected in step 23, and if it is confirmed in step 24 whether or not the wiring passing direction in the wiring restricted area 205 matches the limited wiring direction, the wiring restricted area 205 is desired to pass. Although the direction is the X-axis direction, the wiring direction limited by the wiring restriction region 205 is the Y-axis direction and does not match. Therefore, step 2
In step 4, NO is selected, and a wiring that bypasses the wiring restriction area 205 is laid from the first passage point 204 to the second passage point 206 (S26).

Then, returning to step 22, the wiring route from the position of the second passage point 206 to the end point 202 is searched again. When searching from the position of the second passage point 206 to the end point 202, the wiring restricted area does not exist, but the wiring prohibited area 207 exists. Therefore, since there is no wiring restricted area, NO is selected in step 23 for confirming whether or not there is a wiring restricted area to be passed in the wiring path, and there is a wiring prohibited area 207, so wiring is prohibited in the wiring path. Step 2 to check if the region exists
7, YES is selected, and the wiring that bypasses the wiring prohibited area 207 is changed from the second passage point 206 to the third passage point 20.
Up to 8 are laid (S28).

Then, the process returns to step 22, and the wiring route from the position of the third passage point 208 to the end point 202 is searched again. When searching from the position of the third passage point 208 to the end point 202, there is no wiring restriction area and wiring prohibition area up to the end point 202, so NO is selected in step 23 and step 27, and step 29 is selected.
Proceed to. In step 29, the wiring from the third passage point 208 to the end point 202 is laid and the net wiring is completed.

After that, the process proceeds to step 30 as described above, and it is confirmed whether or not the wiring of all nets is completed.
If there is an unrouted net, step 31
Then, the next net is selected, and the same steps are repeated until the wiring of all nets is completed.

By performing the automatic wiring process in this way,
The wiring can be laid in consideration of the restriction of the wiring direction set in the wiring restricted area.

By providing a wiring restricted area in which the wiring direction is limited in the library for placement and wiring of the macro or standard cell and performing the automatic wiring processing, the internal wiring of the macro or standard cell receives less noise, that is, the internal wiring. Since it is possible to allow the wiring to pass over the macro only in the direction orthogonal to the wiring, it is possible to reduce the wiring detour as compared with the case where the wiring is detoured using the conventional technique of setting the wiring prohibited area. Improve the wiring.

By eliminating the detour of the wiring, the wiring area secured for the detour can be reduced, so that the chip area can be reduced. Further, since the passing wiring can be laid in a straight line on the macro or standard cell without detouring, the wiring length can be reduced. If the wiring length is reduced, the wiring delay is reduced and the operation performance of the circuit can be improved.

FIG. 6 is a plan view showing a state in which the outside-macro wiring is laid in the wiring prohibited area or the wiring restricted area. Figure 6
As described above, in the square macro 301 having a side of 1000 μm, consider the case of laying out the macro outside wiring that connects the midpoints 302 and 303 of the sides in the Y-axis direction of the area where the macro is formed. Since it is necessary to secure a wiring area having a width of 1 μm in order to pass one macro outside wire, if the entire macro 301 is set as a wiring prohibited area, the outside macro wire bypasses the wiring prohibited area. The wiring route is the route 304 bypassing the macro 301. At this time, the wiring length becomes 2000 μm, and the wiring area is 2
It is necessary to secure 000 μm ² .

On the other hand, if the entire macro 301 is set as the wiring restriction area, the wiring outside the macro can pass through the wiring restriction area if the wiring direction permitted in the wiring restriction area is the X-axis direction. The wiring path of the macro outer wire passes through the path 305 that passes through the inside of the macro. Since the wiring length at this time does not require a wiring area for detouring, the required wiring length is 1000 μm. Compared with the case where the wiring outside the macro is laid with the wiring restricted area set, the wiring prohibited area is set. The external macro wiring 1 laid on the macro 301
It is possible to reduce the wiring of 1000 μm per wire and the wiring area of 2000 μm ² . Therefore, when 10 macro outside wirings are passed, the effect is increased 10 times, and the wiring length of 10000 μm and the wiring area of 20000 μm ² can be reduced.

In the first embodiment, in the automatic wiring processing, noise given to the digit line is generated by laying the outside-macro wiring in consideration of the wiring direction of the wiring restricted area provided in the placement and wiring library of the SRAM macro. The external macro wiring is prohibited from passing in the same direction as the digit line, which is the direction in which the noise increases, and only the external macro wiring in the direction orthogonal to the digit line, which is the direction in which noise applied to the digit line is small, is allowed. Automatic wiring is possible. In the conventional technique in which the wiring prohibited area is provided, it is prohibited that the macro outside wiring also passes in the direction orthogonal to the digit line, but in the present embodiment, the wiring restricted area in which the wiring direction is limited is provided. As a result, of the wirings passing over the macro, if the direction is limited to the direction orthogonal to the digit line, it is possible to permit the non-macro wiring to pass over the macro without bypassing the macro. Therefore, by reducing the wiring region and the wiring length, it is possible to improve the wiring property in the integrated circuit and improve the integration degree and the high speed.

Next, a second embodiment of the present invention will be described. This embodiment avoids the problem that the macro or standard cell malfunctions when the number of wirings passing over the macro or standard cell occurs frequently by limiting the number of maximum passing wirings in the wiring restriction area, and It is intended to improve quality.

FIG. 7 is a flow chart showing a wiring method for an integrated circuit according to the second embodiment of the present invention. In this embodiment, steps 1 to 5 are the same as those in the first embodiment. First, the layout of the SRAM macro is selected (S1) and the coordinates of the area set as the wiring restricted area are determined ( S2). Next, the wiring direction of the digit line inside the SRAM macro is detected in order to determine the wiring direction limited in the wiring restricted area (S3). Digit line is X
If the wires are wired in the axial direction, the wiring direction in the wiring restricted area is set to the Y-axis direction (S4). When the digit line is wired in the Y-axis direction, the wiring direction in the wiring restricted area is set to the X-axis direction (S5).

Then, in this embodiment, the maximum number of passing wirings set in the wiring restriction area is extracted (S41).
Then, the coordinates of the wiring restricted area determined as described above, the direction of the restricted wiring, and the information about the maximum number of passing wirings are taken into consideration (S42), and the layout macro for the SRAM macro is generated (S43). After that, the placement and routing library of the SRAM macro including the routing restricted area generated in step 43 and the placement and routing library of other macros or standard cells are used (S44, S4).
5) Execute automatic placement and routing of chips. First, the automatic placement process is executed to determine the placement position of the macro or standard cell (S46). Next, the wiring is laid by the automatic wiring process in consideration of the restriction of the wiring direction set in the wiring restricted area and the restriction of the maximum passing wiring number (S47), and the chip layout is obtained (S48).

FIG. 10 is a plan view showing a placement / routing library of an SRAM macro including a wiring restricted area. Step 1 to Step 5 and Step 41 and Step 4
2, the layout macro for the SRAM macro is generated as shown in FIG. SRAM macro 404
Has a memory cell portion 403 in which memory cells (not shown) are arranged in an array, and a plurality of digit lines 402 extending in the Y-axis direction are wired in parallel to each other in the memory cell portion 403, The memory cell portion 403 is set in the wiring restricted area 401 (S2). Since the direction of permitting the wiring passing therethrough is the X-axis direction orthogonal to the digit line 402, it is prohibited to lay the external macro wiring in the Y-axis direction which is the same direction as the digit line 402 ( S
5). When the digit line 402 is wired in the X-axis direction, the direction in which the passage wiring is permitted in the wiring restriction area 401 is the Y-axis direction, and it is prohibited to pass through the wiring restriction area in the X-axis direction ( S4). Further, in the wiring restriction area 401, the maximum number of wirings through which the macro outside wiring can pass in step 41 is limited to eight, and the macro outside wirings after the ninth macro wiring are restricted even in the X-axis direction orthogonal to the digit line 402. Passing through the area is prohibited. Then, the layout and wiring library of the SRAM macro is generated from the coordinates of the memory cell portion 403, which is the determined wiring restricted area, and the information that the wiring laying direction is the X-axis direction and the maximum passing wiring is 8 (step 42). (S43).

A method of extracting the number of passing wirings set in the wiring restriction area in step 41 will be described below.
FIG. 9A is a plan view showing the maximum passing wiring laid in the wiring restricted area, and FIG. 9B shows the result of simulation of the passing wiring set in the wiring restricted area. As shown in FIG. 9A, in the RAM macro 404, a plurality of digit lines 402 extending in the Y-axis direction are wired in parallel to each other in the memory cell section 403. In order to extract the maximum number of passing wirings, for example, a circuit simulator SPICE (Simulation Program w) for a state in which a temporary wiring passing through the memory cell portion 403 is laid in a direction orthogonal to the digit line 402.
Simulation can be carried out with ith Integrated Circuit Emphasis). The temporary wiring is laid at the minimum wiring pitch so as to maximize the number of passages. When temporary wiring is laid in the memory cell portion 403 so that the number of passing wirings is maximized at the minimum wiring pitch, one of the temporary wirings N1 to N12 can be obtained.
Two can be laid. In the simulation, among the temporary wirings N1 to N12, when only the signal of one temporary wiring is changed, when the signal of two temporary wirings is changed, 3
This is performed for each case where the number of temporary wirings for changing the signal is increased by one, such as when the signal for the temporary wirings for a book is changed.

The SRAM macro 404 detects a minute potential difference between the digit lines 402 forming a pair in the sense amplifier 406 provided in each digit line 402 pair adjacent to the memory cell portion 403 and reads the data. To do. Therefore, the temporary wirings N1 to N12 are connected to the sense amplifier 40.
When twelve N1 to N12 are laid from a position closer to 6, the temporary wiring laid closer to the sense amplifier 406 has a greater influence on the operation of the SRAM macro.
Therefore, if the signal of the temporary wiring N1 closest to the sense amplifier 406 is changed, or if the signals of the temporary wiring N1 and the second closest temporary wiring N2 are changed, the temporary wiring N1 and the temporary wiring N are changed.
In the worst case, the maximum number of passing wirings that does not cause a malfunction in the SRAM macro 404 is obtained by sequentially performing simulations such as when the signals of the tentative wiring N3 closest to the second and third are changed. Can be extracted. For example, as shown in FIG.
The SRAM macro 404 operates normally when the signals of the eight temporary wirings 1 to N8 are changed, but the temporary wiring N1
If the SRAM macro 404 malfunctions when the signals of the nine tentative wirings up to N9 are changed, SR
The maximum number of passing wires of the AM macro 404 is eight.
In this way, by performing the simulation in the worst case and extracting the maximum number of passing wires, even if the wiring is laid at any position within the maximum number of passing wires, the SR
The normal operation of the AM macro can be guaranteed.

FIG. 11 shows S including the wiring restricted area of FIG.
FIG. 6 is a plan view showing a state in which wiring is laid by using a placement / routing library of a RAM macro. SRAM macro 4
Digit line 4 in the Y-axis direction
Since 02 is wired, the wiring that can be laid in the wiring restricted area 401 is limited to the X-axis direction, and the maximum number of passing wirings is limited to 8 in step 41. By passing the external macro wiring in the direction orthogonal to the digit line 402, the noise given to the digit line 402 can be suppressed. However, if the number of wirings passing through increases, the total noise received by the digit line 402 may increase, and the SRAM macro 404 may malfunction. In this embodiment, however, the wiring passes over the wiring restriction area 401 by simulation as described above. Since the maximum number of passing wirings that can be made is limited to eight, the SRAM macro 404
Can be prevented from malfunctioning. Therefore, for example, when ten macro outer wirings are laid here, eight macro outer wirings 405a pass through the wiring restriction area 401, and due to the limitation of the maximum passage wiring, the macro outer wirings 405 are no longer provided.
Since the SRAM macro 404 malfunctions when a is passed through, the remaining two outside macro wirings 405b bypass the wiring restricted area 401 and are automatically wired (S47).

The program for the automatic wiring process shown in FIG. 7 will be described in more detail below. FIG. 8 shows a second embodiment of the present invention.
It is a flowchart figure which shows the program of the automatic wiring process of the Example. First, variables for storing the number of passed wirings are secured for the wiring restricted area, and the value is initialized to 0 (S51). Next, the net to be routed first is selected (S52), and the route is searched (S5).
3). Then, it is confirmed whether or not there is a wiring restricted area to be passed on the searched wiring route (S54). If there is a wiring restriction area you want to pass in the wiring route,
YES is selected in step 54 and step 55
Proceed to. In step 55, it is confirmed whether or not the direction in which the wiring outside the macro is desired to pass and the wiring direction restricted in the wiring restriction region match. If they match, step 5
YES is selected in step 5, and the process proceeds to step 56. In step 56, it is confirmed whether the passing wiring can be laid. If the number of already-passed wires, which is the number of wires that have already passed through the wire-restricted area, is compared with the maximum number of passed wires given to the placement and routing library in the wire-restricted area, and the number of already-passed wires is smaller Since it is possible to lay a passing wiring, YES is selected in step 56 and a wiring passing through the wiring restricted area is laid (S).
57). After passing through the wiring restriction area in step 57, the process proceeds to step 58, in which the number of already-passed wires in this wiring restriction area is increased by one. On the other hand, step 5
If the maximum number of passing wirings is the same as the number of passing wirings in 6 and if the direction to pass the non-macro wiring does not match the wiring direction restricted in the wiring restriction area in step 55, NO in step 56 and step 55, respectively.
Is selected, and the process proceeds to step 59 to lay a wiring that bypasses the wiring restriction area. If there is no wiring restricted area to be passed on the wiring path, NO is selected in step 54 and the process proceeds to step 60. Step 6
At 0, it is confirmed whether or not there is a wiring prohibited area in the wiring route. If the wiring prohibited area exists, YES is selected in step 60, and the process proceeds to step 61 to lay a wiring that bypasses the wiring prohibited area. After the wiring is laid in steps 58, 59 and 61 respectively, in any case, the process returns to step 53 of searching the wiring route from the position where the wiring is laid to the end point, and step 5
These steps are repeated from 3 to step 62. On the other hand, when it is confirmed in step 60 that the wiring prohibited area does not exist in the wiring route, NO is selected in step 60, the process proceeds to step 62, and the wiring is laid up to the end point. Then, the process proceeds to step 63, and it is confirmed whether or not the wiring is completed for all nets. If not completed, NO is selected in step 63, the process proceeds to step 64, the next net is selected, and step 53 is performed. Through step 62 are repeated. If it is confirmed in step 63 that the wiring has been completed for all nets, YES is selected and the automatic wiring process is completed.

FIG. 12 is a plan view showing a state in which wiring is laid on the net 500 by the automatic wiring processing of the second embodiment. In FIG. 12, the wiring of some nets has already been completed, and three passing wirings 509 are laid in the wiring restricted area 505. Net 500 here
A case of laying the wiring from the start point 501 to the end point 502 will be described. First, when the wiring route from the start point 501 to the end point 502 is searched (S53), the wiring restriction area 503 exists between the start point 501 and the end point 502.
Therefore, YES is selected in step 54 and the process proceeds to step 55. If it is confirmed whether the direction in which the macro outside wiring is to pass on the wiring restriction area 503 matches the wiring direction permitted in the wiring restriction area 503 (S55), the direction to pass the wiring restriction area 503 is the X-axis direction. The wiring direction permitted in the wiring restricted area 503 is also the X-axis direction and coincides. Therefore, YES is selected in step 55 and the process proceeds to step 56. Wiring restricted area 503
Then, the number of already-passed wirings, which is the number of already-passed wirings, is compared with the maximum number of passing wirings given to the placement and routing library in the wiring restriction area 503 (S56).
The number of passed wirings in the wiring restricted area 503 is 0, and the maximum number of passed wirings in the wiring restricted area 503 is 5. Since the number of passed wirings is smaller, passing wirings can be laid. Therefore, YES is selected in step 56, and the wiring is laid from the starting point 501 to the first passing point 504 through the wiring restricted area 503 (S5).
7).

Here, since the number of wirings that have passed through the wiring restriction area 503 is increased by one, the variable for storing the number of already passed wirings for the wiring restriction area 503 is increased by one (S).
58).

Next, in step 53, the wiring route from the first passing point 504 to the end point 502 is searched again. When searching from the first passage point 504 to the end point 502, the wiring restricted area 505 exists. Therefore, YES is selected in step 54 and the process proceeds to step 55. The direction in which the wiring outside the macro is allowed to pass through the wiring restriction region 505 is the X-axis direction, and the wiring direction permitted in the wiring restriction region 505 is the X-axis direction, which coincides with each other. Therefore, YES is selected in step 55 and the process proceeds to step 56.

In step 56, the number of already-passed wires, which is the number of wires that have already passed through the wire restriction area 505,
The maximum number of passing wirings given to the placement and wiring library in the wiring restriction area 505 is compared. Here, since the number of passed wirings in the wiring restriction area 505 is three and the maximum number of passing wirings is three, the number of passed wirings and the maximum number of passing wirings are the same, and no more passing wirings are set. Cannot be laid. Therefore, in step 56, N
O is selected and the first pass point 504 to the wiring restriction area 50
Wiring is laid around the second pass point 506 by bypassing 5 (S59).

Next, the process proceeds to step 53 again to search for a wiring route from the second passing point 506 to the end point 502.
When searching from the second passing point 506 to the end point 502, the wiring restricted area does not exist, but the wiring prohibited area 507 exists. Therefore, NO is selected in step 54 because there is no wiring restricted area, and YES is selected in step 60 because there is a wiring prohibited area 507.
Go to step 61. Then, the wiring that bypasses the wiring prohibited area 507 from the second passage point 506 is the third passage point 50.
Up to 8 are laid (S61).

Then, the process proceeds to step 53 again to search for the wiring route from the third passing point 508 to the end point 502. When searching from the third passing point 508, there is no wiring restricted area and wiring prohibited area up to the end point 502, so NO is selected in each of step 54 and step 60, and the wiring from the third passing point 508 to the end point 502 is selected. Is laid (S62), and the wiring of the net is completed.

After that, in step 63, it is confirmed whether or not the wiring of all nets is completed. If there is an unwired net, the next net is selected (S64) and the wiring of all nets is completed. Repeat similar steps until complete.

Next, an application example of the second embodiment will be shown. This application example solves the problem of the conventional example 5, and the wiring restriction area is partially provided in the memory cell portion of the SRAM macro. In Conventional Example 5, in order to pass the wiring in the direction orthogonal to the digit line, the wiring area in which slits are provided at regular intervals in the wiring prohibited area is secured, but in this application example, instead of the wiring prohibited area. A strip-shaped wiring restriction area is provided.

FIG. 13 is a plan view showing the structure of the SRAM macro automatic placement and routing library. In Conventional Example 5, slits are provided at regular intervals for the wiring that passes in the direction orthogonal to the digit line, and a wiring prohibited area in which a wiring area through which the wiring can pass is secured is provided. A band-shaped wiring restriction area is provided in the digit line pair instead of the wiring prohibited area. As shown in FIG.
The AM macro 604 has a memory cell portion 603 in which a plurality of digit lines 602 are arranged in parallel with each other and extending in the Y-axis direction.
And the wiring direction is limited to the X-axis direction and the maximum number of passing wirings is limited to five, each wiring restriction area 601 is formed in a pair of digit lines 602, and between each wiring restriction area 601. A gap is provided.

[0058] In the conventional example 5, macro outside wiring the local concentration, because that was necessary to bypass the macro out wiring to the position of the fixed wiring region, the problem of wiring deteriorates had occurred. FIG. 14 is a plan view showing a state where wiring is laid by performing the automatic wiring processing of the second embodiment on the placement and wiring library of the SRAM macro shown in FIG.
Since the wiring restricted area 601 can be laid down by passing the macro outside wiring at an arbitrary position, as shown in FIG. 14, the passing macro outside wiring 605a is formed in the memory cell section 60.
It is possible to lay it in a straight line without making a detour with respect to 3. Therefore, the wiring property is improved as compared with the conventional example 5 shown in FIG. 25, which requires the detour.

By limiting the maximum number of passing wirings in the wiring limitation area, the problem that the SRAM macro malfunctions due to the frequent occurrence of passing wirings can be solved as shown in FIG. In FIG. 14, since the maximum number of passing wirings in the wiring restricted area 601 is limited to 5, the five macro outside wirings 605a pass over the memory cell 603, and when the outside macro outside wiring 605a passes therethrough. Since the SRAM macro 604 malfunctions, the remaining two outside macro wirings 605b are routed around the memory cell portion 603. Therefore, the conventional example 5 shown in FIG. 26 in which the number of external macro wirings could not be limited
Compared with, the malfunction of the SRAM macro can be prevented and the quality thereof can be improved.

FIG. 15 is a plan view showing a state in which external macro wiring is laid in parallel with the digit lines of the SRAM macro.
When the SRAM macro placement and routing library shown in FIG. 13 is used to pass the external macro wiring 605c in the same direction as the digit line 602, the technique of Conventional Example 5 shown in FIG. 24 is applied to form a pair. It can be laid at a position between the digit lines 602.

According to the wiring method of the second embodiment, the SRA
When the wiring restriction area is provided in the memory cell portion of the M macro and the wiring outside the macro is automatically processed, the wiring is laid in consideration of the restriction of the wiring direction set in the wiring restriction area and the restriction of the maximum passing wiring number. Therefore, it is possible to improve the wiring property laid in the memory cell part, and the macro external wiring more than the maximum number of passing wires bypasses the memory cell part, and the macro in the direction orthogonal to the digit line that does not affect the digit line easily. Even in the case of the external wiring, if the SRAM malfunctions as the number of external wirings increases, this can be prevented.

Further, the present invention can be applied not only to a macro but also to a standard cell constituting a basic circuit.
As a first modification of the first and second embodiments of the present invention, a wiring restricted area is provided in the standard cell. Figure 16 (a)
16A is a plan view showing a standard cell, FIG. 16B is a plan view showing a state where wiring is laid by providing a conventional wiring prohibited area in FIG. 16A, and FIG. 16C is a first modification in FIG. FIG. 7 is a plan view showing a state in which wiring is laid by providing an example wiring restricted area. Intra-cell wiring 703 of the standard cell 705
Is the output of the clocked inverter 701 and the inverter 7
02 is connected to the input of the clocked inverter 70
When 1 is turned off, a dynamic operation of holding a value by the wiring capacitance of the in-cell wiring 703 is performed.

Here, as shown in FIG. 16A, the outside-cell wiring 704 is formed on the inside-cell wiring 703 and the inside-cell wiring 70.
3 is laid in the same X-axis direction as that of No. 3, a large coupling capacitance is parasitic between the outside-cell wiring 704 and the inside-cell wiring 703, and the inside-cell wiring 7 is affected by crosstalk.
There is a problem that noise is generated in 03 and the held value is destroyed.

In order to avoid this, conventionally, (for example, Conventional Example 3 or the like), a wiring prohibited area is provided in the placement and routing library of the standard cell 705. As shown in FIG. 16B, the wiring prohibited area 706 is provided on the intracell wiring 703, which is weak against noise between the clocked inverter 701 and the inverter 702, so that the intracell wiring 703 and the intracell wiring 703 are provided. Outside cell wiring 7 in the same X-axis direction as
04 is prohibited from being laid. However, if the wiring prohibited area 706 is set in this manner, the influence of noise is reduced, and the Y in the direction orthogonal to the in-cell wiring 703 is reduced.
The cell outside wiring 704 cannot be laid also in the axial direction. Therefore, the standard cell 705 is connected to the in-cell wiring 7
Even when laying in the Y-axis direction orthogonal to 03, the out-of-cell wiring 704 bypasses the wiring prohibited area 706, deteriorating the wiring performance.

On the other hand, as shown in FIG. 16C, in the first modified example, a wiring restricted area is formed on the intracell wiring 703 between the clocked inverter 701 and the inverter 702 in the standard cell 705, which is weak against noise. 707 is provided.
The wiring restricted area 707 is allowed to pass through the wiring only in the Y-axis direction which is a direction orthogonal to the in-cell wiring 703. As a result, the extra-cell wiring 704 can be laid so as to pass over the wiring restricted area 707 without detouring, and the wiring performance is not deteriorated. Also in the first modification, the cell external wiring 7 orthogonal to the cell internal wiring 703 is also provided.
If the number of 04 lines occurs frequently and the value held in the in-cell wiring 703 is destroyed, the number of out-cell wirings that can pass over the in-cell wiring 703 is checked by the same method as in the second embodiment, It is also possible to set a limit on the maximum number of passing wires in the limit area 707.

As described above, even in the standard cell, the effect of improving the wiring property can be obtained by providing the wiring restriction region.

As a second modification of the first and second embodiments of the present invention, the restriction of the wiring direction given in the wiring restriction region prohibits the wiring in the X-axis direction or the Y-axis direction. It can be given as an attribute. Figure 17
It is a top view which shows the wiring restricted area of the 2nd modification of this invention. It is prohibited to lay the passing wiring in the wiring restricted area 801 in the Y-axis direction. Therefore, the passage wiring 80
2 can pass through the wiring restricted area 801 in the X-axis direction. Further, when the restriction of the wiring direction in the wiring restriction area 802 is prohibited in the X-axis direction, the wiring restriction area 802
It is possible for the passing wiring 802 to pass therethrough only in the Y-axis direction.

[0068]

As described in detail above, according to the present invention,
In the placement and routing library, a wiring restricted area that has a restriction in the passing wiring direction is provided to perform automatic wiring, so while preventing cell malfunction due to outside-cell wiring, the outside-cell wiring is not bypassed on the cell The wiring property of the integrated circuit can be improved by passing the wiring in a direction orthogonal to the inner wiring. This makes it possible to design an integrated circuit capable of achieving a high degree of integration and a high-speed response by reducing the wiring laying area and the wiring length.

[Brief description of drawings]

FIG. 1 is a flowchart showing a wiring method for an integrated circuit according to a first embodiment of the present invention.

FIG. 2 is a flowchart showing a program for performing an automatic wiring process according to the first embodiment of the present invention.

FIG. 3 is a plan view showing a library for automatic placement and routing of SRAM macros.

FIG. 4 is a plan view showing a state where external macro wiring is laid using the SRAM macro placement and routing library shown in FIG. 3;

FIG. 5 shows the automatic wiring process of the first embodiment of the present invention.
It is a top view which shows the macro outside wiring laid on the net.

FIG. 6 is a plan view showing a state in which a non-macro wiring is laid in a wiring prohibited area or a wiring restricted area.

FIG. 7 is a flowchart showing a wiring method for an integrated circuit according to a second embodiment of the present invention.

FIG. 8 is a flowchart showing a program for automatic wiring processing according to a second embodiment of the present invention.

FIG. 9A is a plan view showing the maximum passing wiring laid in the wiring restricted area, and FIG. 9B shows a result of simulation of the passing wiring set in the wiring restricted area.

FIG. 10 is a plan view showing a placement / routing library of an SRAM macro including a wiring restricted area.

FIG. 11 is a plan view showing a state in which wiring is laid in a placement / routing library of an SRAM macro.

FIG. 12 is a plan view showing a state in which wiring is laid on a net by the automatic wiring processing of the second embodiment.

FIG. 13 is a plan view showing the structure of a library for automatic placement and routing of SRAM macros.

FIG. 14 is a plan view showing a state in which wiring is laid by performing the automatic wiring processing of the second embodiment on a placement and wiring library of an SRAM macro.

FIG. 15 is a plan view showing a state in which external macro wiring is laid parallel to the digit lines of the SRAM macro.

16A is a plan view showing a standard cell, FIG.
(B) is a plan view showing a state where the conventional wiring prohibited area is provided in (a) and the wiring is laid, and (c) is a wiring where the wiring restricted area of the first modified example of the present invention is provided in (a) It is a top view showing the appearance of having been laid.

FIG. 17 is a plan view showing a wiring restricted area according to a second modified example of the present invention.

18A is a plan view showing automatic wiring of an SRAM macro, and FIG. 18B is an enlarged plan view of a memory cell portion of the SRAM macro.

FIG. 19 is a plan view showing an SRAM macro having a wiring prohibited area.

FIG. 20 is a flowchart showing a method of designing a wiring using a wiring prohibited area.

FIG. 21 is a flowchart showing a program in an automatic wiring process of Conventional Example 4.

FIG. 22 is a plan view showing a state in which a macro external wiring 105 is laid in the wiring prohibited area 101.

23 is a diagram showing a layout of a memory cell portion of the semiconductor integrated circuit described in Conventional Example 5. FIG.

FIG. 24 is a configuration example of a library to which the technique of Conventional Example 5 is applied.

FIG. 25 is a plan view showing a state in which external macro wiring is concentrated in the SRAM macro of Conventional Example 5.

FIG. 26 is a plan view showing a wiring region in which many slits are provided in a wiring prohibited region in a direction orthogonal to a digit line.

[Explanation of symbols]

1, 203, 205, 401, 503, 505, 60
1; wiring restricted area 2, 102, 402, 602; digit line 3, 103, 403, 603; memory cell section 4, 104, 404, 604; SRAM macro 5, 405a, 405b, 605a, 605b, 605
c: Outer macro wiring 101, 207, 502; Wiring prohibited area

─────────────────────────────────────────────────── ─── Continuation of front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 21/82 G06F 17/50 H01L 27/04 H01L 21/822 H01L 21/8242 H01L 27/108

Claims (5)

(57) [Claims] 1. A macro controller for a placement and routing library of an integrated circuit used for automatic design of a semiconductor integrated circuit device.
The wiring that passes through the inside of the
The direction is orthogonal to the noise sensitive wiring inside the macro cell
A library for placement and routing of an integrated circuit, wherein a wiring restricted area which is permitted only in a direction is provided. 2. A semiconductor integrated circuit device placement and routing library of integrated circuit used in the automated design of Sutanda
It is provided in the battery cell and the
The line direction is weak to the noise inside the standard cell.
A placement / routing library for an integrated circuit, wherein a wiring restricted area which is permitted only in a direction orthogonal to a line is provided. Wherein the routing restrictions area, placement and routing library according to claim 1 or 2, characterized in that the number of wires passing through the wire restricted area is limited. 4. A step of generating a placement and routing library having a wiring restricted area which is permitted only in a direction in which the out-of-cell wiring passes through a direction orthogonal to the in-cell wiring, and a placement position of the placement and routing library. When the automatic placement step of deciding and laying out, the step of confirming whether or not the wiring direction permitted in the wiring restricted area and the direction of the outside-cell wiring to be laid match, and the step of checking, A wiring method for an integrated circuit, wherein: a wiring that passes through the wiring restricted area is laid; and if the wirings do not match in the checking step, a wiring that bypasses the wiring restricted area is laid. 5. The wiring restricted area is limited in the number of wires that can pass through the wiring restricted area, and a wiring direction permitted in the wiring restricted area and a direction of an out-of-cell wiring to be laid coincide with each other. In this case, the number of out-of-cell wires that have already passed through the wiring restricted area and the number of wires that can pass through the wiring restricted area are checked, and the number of wires that can pass through the wiring restricted area has already passed through the wiring restricted area. When the number of wirings is larger than the number of wirings, the cell outside wirings that pass through the wiring restriction area are laid, and the number of wirings that have already passed through the wiring restriction area and the number of wirings that can pass through the wiring restriction area are The wiring method for an integrated circuit according to claim 4 , wherein, when they match, an out-of-cell wiring that circumvents the wiring restricted area is laid.