JP3390660B2 - Manufacturing method of dielectric isolation substrate - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a dielectric isolation substrate on which a semiconductor device such as a power IC is formed.

[0002]

2. Description of the Related Art In a dielectric isolation substrate, a plurality of single crystal isolation island regions are formed in a support, and each single crystal island region is electrically insulated from the support by an insulating film. Since the single crystal island regions are insulated and separated from each other by the insulating film in the single crystal island regions, a semiconductor element having a relatively high breakdown voltage of about several hundreds of V can be formed. Therefore, the dielectric isolation substrate is a semiconductor substrate suitable for various power ICs.

A conventional method for manufacturing a dielectric isolation substrate will be described below with reference to FIG. FIG. 3 shows a cross section of an outer peripheral portion of a silicon substrate in a conventional manufacturing method. (3a) is a single crystal silicon substrate 17 on the side where elements are formed.
In (3a), a plurality of isolation trenches 18 are formed on one surface of the substrate 17 by etching or the like, a silicon oxide film 19 is formed as an insulating film on the isolation trench formation surface, and a vapor phase growth method is performed on the silicon oxide film 19. By polycrystalline silicon layer 2
0 is deposited. Next, as shown in (3b), the polycrystalline silicon layer 20 deposited on the outer periphery and the back surface of the substrate 17 is processed into a predetermined shape to remove it, and the surface of the polycrystalline silicon layer 20 is ground and ground in (3c). It is made flat by polishing and processed into a mirror surface.

After cleaning the substrate 17 and the single crystal silicon substrate 21 serving as a support, the substrate 1 is processed as shown in (3d).
The surface of the polycrystalline silicon layer 20 of No. 7 and the mirror surface of the substrate 21 are bonded to each other and bonded by heat treatment. The joined substrate is processed and removed in the hatched region 22 shown in (3e). Further, the other surface of the single crystal substrate 17 in which the separation groove 18 is formed is ground and polished to produce a dielectric separation substrate 23 having a plurality of single crystal island regions shown in (3f).

The technique described in Japanese Patent Publication No. 58-45182, for example, is related to the conventional method for manufacturing a dielectric isolation substrate.

[0006]

[Problems to be Solved by the Invention]
First, a wafer is placed horizontally on a positioning jig with the mirror surface of the wafer facing upward, and the mirror surface of another wafer is placed on the wafer so as to face it. The positioning jig is used to prevent the wafers from being misaligned. This is because when the above wafers are stacked, water molecules existing between the wafers cause the stacked wafers to remain floating and freely shift in the horizontal direction.
Next, when a part of the stacked wafers is pressed with a force of several hundreds of g, bonding between the wafers starts. Bonding starts from the pressed part and spreads at a speed of several cm / sec, and the entire bonding surface is bonded. One of the forces considered to bond the wafers to each other is a hydrogen bond that acts between water molecules and OH groups adsorbed on the mirror surface of the wafer. The bonded wafers are heat-treated at a high temperature of 1000 ° C. or higher, so that the wafers are completely bonded to each other.

FIG. 4 shows voids generated at the bonding interface of the dielectric isolation substrate manufactured by the conventional manufacturing method. The void is a region where the wafers are not joined yet. Voids tend to be concentrated in the outer peripheral portion, and the state of the void is roughly divided into a dot-shaped void 24 and a void 25 having a region that extends to the outer peripheral end portion. The dot-shaped voids 24 are spatially closed, and since the bonding tends to progress and disappear due to the heat treatment in the subsequent element process, it does not adversely affect other wafers and devices during the process progress. . However, since the void 25 has an unbonded region that extends to the outer peripheral edge, it may be exposed to chemicals in the bonding interface or shock during wafer transfer during subsequent processes such as heat treatment, photolithography, and cleaning. There is a risk that the crystal island region will peel off from the bonding interface. In this case, not only the peeled wafer but also the peeled portion becomes a foreign substance, which adversely affects not only other wafers but also the semiconductor manufacturing apparatus. Therefore, the wafer in which the void 25 is generated must be immediately defective, and the yield is significantly reduced.

The following two factors can be considered for the generation of the void 25.

One is a jig for aligning the wafers with each other at the time of bonding. Generally, the outer diameters of the two semiconductor substrate wafers to be bonded are approximately the same size with a tolerance of about ± 0.5 mm. ), Holes 26 along the outer periphery of the wafer to prevent misalignment.
Or a jig in which rod-shaped pins 27 are provided at intervals along the outer periphery of the wafer as shown in FIG. 5B. FIG. 6 is a partial cross-sectional view of the outer peripheral portion when the wafers are bonded together. At the time of bonding, if the pins or walls 28 for aligning the wafer and the jig are in strong contact, the bonding between the wafers is hindered and spread in the vicinity of the contact portions due to the stress due to the elastic deformation of the outer peripheral portion of the wafers. The void 25 that does not have a closed space as shown in FIG.
Occurs.

The other is chipping that occurs at the outer peripheral edge of the wafer in the process before bonding. When chipping occurs, crystal distortion occurs in the chipping and the region in the vicinity thereof. That is, when the chipping range extends to the wafer surface, crystal distortion also occurs on the wafer surface. It is conceivable that a wave of bonding between the wafers is blocked by this crystal distortion in the vicinity of chipping and a similar void 25 is generated. Actually, the position of the chipping of the wafer and the position of the void 25 are in good agreement, and it can be said that the occurrence of the void 25 is greatly related to the chipping.

An object of the present invention is to provide a method for manufacturing a dielectric isolation substrate, which is produced by bonding two semiconductor substrates together, to prevent the occurrence of voids in the outer peripheral portion of the wafer and to suppress the reduction in the yield of the wafer. It is to provide a manufacturing method.

[0012]

In order to solve the above-mentioned problems, the method for manufacturing a dielectric isolation substrate of the present invention includes (1) an outer peripheral portion of a first single crystal semiconductor substrate having a main surface on which a semiconductor element is formed. In the step of processing and removing the polycrystalline silicon layer deposited on the substrate, a step is provided on the outer peripheral portion on the polycrystalline semiconductor layer side, and further, the outer diameter of the step is adjusted to the second single crystal semiconductor substrate serving as a support. And again (2) a second support
Is characterized in that a step is provided on the outer peripheral portion of the surface of the single crystal semiconductor substrate to be bonded, and the outer diameter of the step is adjusted to that of the first single crystal semiconductor substrate to perform the bonding.

The method for manufacturing the dielectric isolation substrate according to the present invention will be described in some detail.

(A) Since the polycrystalline semiconductor layer of the first single crystal semiconductor substrate having the main surface for forming the semiconductor element is formed by the vapor phase epitaxy method, the outer peripheral wall surface of the substrate wafer has almost the same thickness as the surface. A polycrystalline semiconductor layer is formed. The thicker the polycrystalline semiconductor layer is, the larger the outer diameter of the substrate wafer is, and the polycrystalline semiconductor layer deposited near the back surface of the outer peripheral wall is likely to be peeled off, which may cause the generation of foreign matter. Therefore, first, the outer peripheral wall surface is processed into a shape having a predetermined outer diameter. At this time, it is processed into a structure in which a step is provided on the outer peripheral portion on the polycrystalline semiconductor layer side. In the subsequent steps, the surface of the polycrystalline semiconductor layer is ground to make the thickness distribution in the first substrate surface uniform, and the surface is polished to remove scratches peculiar to grinding and to make a flat mirror surface for bonding.

When the wafer comes into strong contact with the alignment portion of the jig during bonding due to the processing with the step, the point of stress concentration is not on the bonding surface but on the stepped portion. Since the influence of the outermost periphery of the wafer on the surface is mitigated, voids are less likely to occur. Further, even if chipping occurs at the outer peripheral edge, the bonding surface separates from the position of chipping due to the step, so that voids due to the effect of chipping are less likely to occur.

Next, a description will be given below of the processing in which a step is provided on the outer peripheral portion of the second single crystal semiconductor substrate which becomes the support.

(B) The same step as that of the first substrate is formed on the outer peripheral portion of the surface to be bonded of the second single crystal semiconductor substrate to be the support. After processing, the surfaces to be bonded are thinly polished to flatten and mirror finish. Then, the first single crystal semiconductor substrate manufactured by a conventional method is attached. By performing this processing, the same action as (A)
It is possible to reduce the occurrence of voids due to the jig described above. Further, even if chipping is present in the first single crystal semiconductor substrate in the conventional method, the bonding region is within the outermost periphery of the substrate due to the step difference of the second single crystal semiconductor substrate. Therefore, the effect of chipping is mitigated, and voids caused by chipping can be reduced.

Further, in (A) and (B), since the outer diameters of the wafers are not changed, the alignment of the wafers at the time of bonding can be performed in the same manner as the conventional method.

[0019]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings.

(Embodiment 1) FIG. 1 shows an embodiment of the present invention by using a sectional view of an outer peripheral portion of a single crystal silicon substrate.

First, as shown in FIG. 1 (a), a plurality of V-shaped separation grooves 2 are formed on one surface of a single crystal silicon substrate by anisotropic etching such as alkali etching, and thermal oxidation is performed on the entire surface of the substrate. Then, a polycrystalline silicon layer 4 is deposited by a vapor phase epitaxy method on the surface where the separation groove 2 of the single crystal silicon substrate 1 on which the silicon oxide film 3 having a predetermined thickness is formed is formed to form a substrate 5. The single crystal silicon substrate of this embodiment has a wafer outer diameter of 125 ± 0.5 mm (5 inches). Next, as shown in (1b), the substrate 5 is processed to have a step on the polycrystalline silicon layer 4 side. This is processed into the shape shown in (1b) over the entire circumference including the orientation flat portion. In this embodiment, the stepped portion is a curved surface of r = 0.25 mm, and the processing length L1
= 0.6 mm and step T1 = 0.2 mm. The step T1 of the present embodiment is a value that takes into consideration the strength of the outer circumference of the substrate in the work environment, and the step T1 may be increased as long as a work environment that does not impose a mechanical load on the outer circumference of the board can be secured. The outer diameter of the substrate 5 is 125 ± 0.2 mm, and the inclined portion 6 on the back surface side is processed so that the polycrystalline silicon layer 4 does not remain. Next, in (1c), the surface of the polycrystalline silicon layer 4 of the substrate 5 is ground and polished to flatten the surface of the polycrystalline silicon layer 4 to make it a mirror surface for bonding.

Next, as shown in (1d), a substrate 5 and a single crystal silicon substrate 7 having an outer diameter of 125 ± 0.2 mm which serves as a support.
Are washed and then attached. Since the outer diameter of the substrate 5 is the same as the outer diameter of the single crystal silicon substrate 7, the wafers can be aligned with each other in the same manner as in the conventional method. The bonded substrate 8 is heat-treated in an oxygen atmosphere at 1100 to 1200 ° C. for 1 to 2 hours to bond the interface between the substrate 5 and the substrate 7. After the heat treatment, the hatched region 9 of the substrate 8 bonded as shown in (1e) is processed and removed by a generally used wafer outer peripheral grinding machine. At this time, the processing length L2 needs to be longer than L1 shown in (1b). In this embodiment, L2 = 1.0 mm. In the outermost peripheral portion 10 of the bonding interface, an unbonded portion having a periphery of 0.1 to 0.2 mm remains due to polishing sag of the bonding surface of the substrate 1. L2
Is for removing this unbonded portion, and L2 ≧ L1 +
If it is 0.4 mm, it can be completely removed. Then, the substrate 5 side is ground and polished to form a plurality of single crystal islands 11 as shown in (1f).
The dielectric isolation substrate 12 on which is formed is completed.

Fifty dielectric isolation substrates each were manufactured by the conventional method and this embodiment, and the void generation state of both of them was evaluated by the ultrasonic reflection method. As a result, voids having no closed space as shown in FIG. 4 were obtained. No. 25 did not occur in this example, whereas four sheets occurred in the conventional method. Further, in the step (1c), an experiment was conducted in which chipping was intentionally made on the outer periphery of the substrate 5 with a diamond cutter and the substrates were bonded together, but the above voids did not occur.

(Embodiment 2) FIG. 2 shows another embodiment of the method for manufacturing a dielectric isolation substrate of the present invention.

FIG. 2 (a) is a sectional view of the outer peripheral portion of the single crystal silicon substrate 13 which serves as a support. First, as shown in (2b), the entire outer circumference including the orientation flat portion of the substrate 13 is processed into a shape having a step on the bonding surface side. The processing length L3 at the outer peripheral edge was 1.0 mm, the step T2 was 50 μm, and the angle α of the step was 120 °. The outside diameter of the substrate 13 is 125 ± 0.2 mm as in the conventional method. After the outer peripheral processing, the surface is thinly polished to finish the edge portion 14 of the step smoothly. Next, as shown in (2c), the substrate 13 and the single crystal silicon substrate 15 for forming the element processed by the conventional method are subjected to cleaning treatment and then bonded. Since the outer diameters of the substrate 13 and the substrate 15 are the same, the positioning at the time of bonding can be performed in the same manner as the conventional method. After performing the same heat treatment as in Example 1, as shown in (2d), a part of the outer periphery of the substrate 15 and the bonding side of the substrate 13 are processed and removed by a generally used wafer outer periphery grinding machine. At this time, the angle β is processed so that β> α. The length of L4 may be L4 ≧ L3. Then, by grinding and polishing the substrate 15 side, the dielectric isolation substrate 16 shown in (2e) is completed.

Fifty dielectric isolation substrates were produced in this example, but no void was generated as in the case of the first example. Further, an experiment was conducted in which chipping was intentionally made and bonded to the outer periphery of the substrate 15 as in Example 1, but no void was generated.

The point of difference of Example 1 from Example 1 is that a single crystal semiconductor substrate on which an element is formed is provided with a step on the outer periphery of a single crystal semiconductor substrate serving as a support without changing the conventional manufacturing method. Therefore, the same effect as that of the first embodiment can be obtained.

The same effect can be obtained even if the stepped portion has a curved shape or an angled shape.

Further, the present invention may use a single crystal semiconductor substrate having a wafer size other than 5 inches. Further, the surface of the semiconductor substrate serving as a support may be a single crystal, a polycrystal, or an oxide film.

[0030]

As described above, in the method for manufacturing a dielectric isolation substrate by bonding, by processing the outer periphery of one of the substrates to be bonded with a step, a void extending to the outer peripheral edge is formed. Occurrence can be reduced.

[Brief description of drawings]

FIG. 1 is a sectional view of an outer peripheral portion of a semiconductor substrate according to an embodiment of the present invention.

FIG. 2 is a sectional view of an outer peripheral portion of a semiconductor substrate according to another embodiment of the present invention.

FIG. 3 is a sectional view of an outer peripheral portion of a semiconductor substrate according to a conventional manufacturing method.

FIG. 4 is a state diagram of generated voids in a dielectric isolation substrate in a conventional manufacturing method.

FIG. 5 is a jig for position alignment at the time of bonding.

FIG. 6 is a state diagram of a semiconductor substrate and an outer peripheral portion of a jig during bonding.

[Explanation of symbols]

1, 17 ... Single crystal silicon substrate, 2, 18 ... Separation groove,
3, 19 ... Silicon oxide film, 4, 20 ... Polycrystalline silicon layer, 5, 15, 17 ... Element formation side silicon substrate, 7, 1
3, 21 ... Support-side single crystal silicon substrate, 8 ... Adhered silicon substrate, 11 ... Single crystal island, 12, 16, 23 ...
Dielectric isolation substrate, 24, 25 ... Void, 26 ... Hole for aligning wafer of bonding jig, 27 ... Pin for aligning wafer of bonding jig, 28 ... For aligning wafer of bonding jig Outer wall or pin.

─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Toyoichi Nemoto 3-1-1, Saiwaicho, Hitachi-shi, Ibaraki Hitachi Ltd. Hitachi factory (72) Inventor Yuji Takayanagi 3-chome, Saiwaicho, Hitachi, Ibaraki No. 1 Hitachi, Ltd., Hitachi factory (72) Inventor, Koji Sakuraba 3-1-1, Saiwaicho, Hitachi, Ibaraki Hitachi, Ltd., Hitachi factory (56) Reference: JP-A-4-85827 (JP, A) (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 21/762 H01L 21/02 H01L 27/12

Claims (2)

(57) [Claims] 1. A step of forming an isolation groove on one surface of a first single crystal semiconductor substrate, and a step of forming an insulating film on the one surface of the single crystal substrate after forming the isolation groove. A step of forming a polycrystalline semiconductor layer on the insulating film, a step of processing and removing the polycrystalline semiconductor layer deposited on the side surface of the single crystal semiconductor substrate, and a surface of the polycrystalline semiconductor layer being flattened. A step of adhering a second single crystal semiconductor substrate to the planarized surface of the polycrystalline semiconductor layer, and a step of grinding and polishing the first single crystal semiconductor substrate to form a single crystal island region a step, in the dielectric isolation substrate manufacturing method comprising, before the step of Ru bonding the second single crystal semiconductor substrate, the entire outer peripheral portion of the first polycrystalline semiconductor layer side surface of the single crystal semiconductor substrate to, in the center of the substrate from the outer periphery of the substrate Only in the first
A step of providing a step of length L1, after the step of bonding the second single crystal semiconductor substrate
And a second single bond with the outer peripheral portion of the first single crystal semiconductor substrate.
The second semiconductor single crystal half by grinding the outer peripheral portion of the crystal semiconductor substrate.
The second length L2 from the outer periphery of the conductor substrate to the center of the substrate
And a step of providing a step, and the first length L1 and the second length L2 have a relationship of L2> L1.
A method of manufacturing a dielectric isolation substrate, comprising: 2. A step of forming an isolation groove on one surface of a silicon single crystal semiconductor substrate; a step of forming an insulating film on the one surface of the single crystal substrate after forming the isolation groove; on the insulating film, forming a polycrystalline semiconductor layer, a step of the removal processing of the polycrystalline semiconductor layer deposited on the side surface of the single crystal semiconductor substrate, a step of flattening the surface of said polycrystalline semiconductor layer A second silicon layer on the surface of the planarized polycrystalline semiconductor layer.
A step of laminating a single crystal semiconductor substrate, and a step of grinding and polishing the first single crystal semiconductor substrate to form a single crystal island region . before this Ru bonding the single crystal semiconductor substrate process, the entire outer peripheral portion of the second side surface of the bonding of a single crystal semiconductor substrate, the direction from the substrate outer periphery to the center of the substrate
A step of providing a step length L3 of 3, after the step of bonding the second single crystal semiconductor substrate
And a second single bond with the outer peripheral portion of the first single crystal semiconductor substrate.
The second semiconductor single crystal half by grinding the outer peripheral portion of the crystal semiconductor substrate.
The fourth length L4 from the outer periphery of the conductor substrate toward the center of the substrate
And a step of providing a step, and the third length L3 and the fourth length L4 have a relationship of L4> L3.
A method of manufacturing a dielectric isolation substrate, comprising: