JP3393408B2 - A framing method in a digital video signal recording device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [0001] BACKGROUND OF THE INVENTION 1. Field of the Invention
For example, a digital video signal recording device using DCT.
The present invention relates to a method of framing a frame. [0002] 2. Description of the Related Art A digital video signal is, for example, a rotating head.
Digital VTR recording on magnetic tape
Have been. Because of the large amount of digital video signal information,
Uses high-efficiency coding to reduce the amount of transmitted data
Often done. Among various high efficiency codings, DC
Commercialization of T (Discrete Cosine Transform) is progressing
You. [0003] DCT converts an image of one frame into, for example, (8
× 8), and transform this block into an orthogonal transform.
This is a cosine conversion process which is a kind of conversion. That
As a result, (8 × 8) coefficient data is generated. like this
Coefficient data can be run-length codes, Huffman codes, etc.
It is transmitted after undergoing variable length coding processing. During transmission
Is encoded to facilitate data processing on the playback side.
The output code signal is transferred to a fixed-length sync block.
Data area, and a synchronization signal, I
Frame constituting sync block to which D signal is added
Is made. A digital VTR using a magnetic tape,
Disc recording devices that use disc-shaped recording media
Means that one field or one frame of video data
It is usually recorded on a plurality of tracks. However
However, as in the DCT described above, a variable length output is formed.
In such a case, the data amount during these predetermined periods fluctuates. This
Therefore, in order to reduce the data amount for a predetermined period to a target value or less,
Buffering processing is required. As an example, one field or one frame
For a shorter period of time (called a buffering unit).
Control the amount of data in one field or one frame.
As a result, even during the entire
Buffering processing has been proposed. Buffery
In the coding process, the coefficient data for the AC generated in DCT is applied.
Requantization in a sharp quantization step
This is processing to keep it below the standard value. In the transmitted data, quantum
The code of the quantization step or the quantization number
Inserted together with the encoded data. The component signals (Y, U, V) are converted to DC
When performing T encoding, a unit called a macroblock is derived.
Yes. In the (4: 1: 1) method, the luminance signal
And four DCT blocks (YYYY)
Two DCT blocks for the color difference signal
The macroblock is constituted by the ku U and V.
In the (4: 2: 0) scheme, four (2 × 2) DCTs are used.
Blocks (YYYY), and
A macro block is formed by two DCT blocks U and V.
Is configured. Component-based digital VT
In R, the data that can be used as the reproduced image data is
This is reproduced in units of macro blocks. Therefore,
Even if each color is in a different macroblock
Even if the difference data U and V and the luminance data Y can be reproduced,
The image cannot be composed. [0007] In the recording data, sync blocks are continuous.
Configuration. The code included in this one sync block
Relation between macro signal and macro block is not specified
And can reproduce all the code signals of one sync block
However, when viewed in macroblock units, all are always valid
Cannot be treated as sensitive data. This means that
When performing variable speed playback to retrieve playback data in blocks
It becomes a title. Therefore, the applicant of the present application has
Corresponding to an integer number, for example, one macroblock
Insert the output and use the macro block as much as possible during variable speed playback.
Provision of a recording device that can reproduce component data in units
I am planning. [0008] As a video signal,
Even with SD (standard definition) signals, the field frequency
There is a difference of 50Hz and 60Hz, and the aspect ratio is
Different SD wide systems exist, and data volume
However, there may be half SD-L systems. These ties
The video signal of the tape is also the same rotating head and magnetic tape
It is preferable to be able to record / reproduce with the VTR of the mechanism including
No. In the case of such a digital VTR,
The amount of recorded data differs depending on the type of video signal.
The configuration of the data recorded / reproduced for each type is set.
Had been established. As a result, recording / reproduction of digital VTR
There is a disadvantage that the scale of the circuit for production increases.
Was. In addition, sync between different types of video signals.
Since the data amount differs when the block length is fixed,
Make the data arrangement in the sync block exactly the same
Is impossible, just make the sync block length equal
Then, the circuit scale is not sufficiently reduced. Therefore, the object of the present invention is to
When recording video signals
Thus, a sync block is formed, and the regulation of the recording / reproduction circuit is
Digital video signal recording device frame
It is an object of the present invention to provide a computerized method. [0011] SUMMARY OF THE INVENTION The present invention provides a digital
When cosine transform and variable length coding of video signal
In addition, the data amount of the encoded output for a predetermined period
Control to fit within the data area of the block.
Buffering circuit for the
The output is configured as a sync block, and multiple
Having a device for recording as a single track
Framing method in a video signal recording apparatus.
When recording SD type digital video signals,
Indicates the area where video data is allocated for each sync block.
It is divided into 1, 2, 3 and 4 areas, and N
1st, 2nd, 3rd and 4th
Of the first digital video signal in the divided area of
Place the coded output of the cosine transform block ofEach thin
The first, second, third and fourth areas of the block
When the encoded output of one digital video signal is arranged
The first, second, third and fourth divided areas respectively
When the DC component of the luminance signal component is
In addition, the order of the luminance signal component and the chrominance signal component is
AndCompared with SD type digital video signals,
4/3 times the number of cosine transform blocks recorded on the rack
When recording the second digital video signal of
The coded outputs of the M cosine transform blocks are first and second
And in the third divided areaDistributed to1 / 3M
Place cosine transform block in fourth divided areaAnd
The first, second and third areas of each sync block
When the coded output of digital video signal 2 is arranged
In each of the first, second and third divided areas,
The DC component of the luminance signal component is
The order of the degree signal component and the color signal component is assumed to be predetermined.Ruko
Frame of a digital video signal recording device characterized by
It is a method of systemization. [0012] [Function] When recording an SD type digital video signal
Means that the buffering circuit has a data
30 DCT blocks (= 6 macro blocks) in the rear
Of the encoded output so that the encoded output corresponding to
Control the amount of data. Truck compared to SD type
4/3 times the number of cosine transform blocks recorded in SD
Wide or SD-L type digital video signal
When recording, the buffering circuit has 5 sync blocks.
40 DCT blocks (= 6 macros) in the data area of
Block + 4DCT block)
The data amount of the encoded output is controlled so as to be included. each
The data area of the sync block is divided into four. 30D
The encoded output corresponding to the CT block is
Data that includes data corresponding to 6DCT blocks
Configuration. Encoding output corresponding to 40 DCT blocks
Force is within the first to third divided areas of each sync block
The one corresponding to the 30DCT block is the same as the SD type
It is arranged with the regularity of. The remaining 10 DCT blocks
And the encoded output corresponding to the fourth
Packed in the area. [0013] BRIEF DESCRIPTION OF THE DRAWINGS FIG.
It will be described in the light of the above. FIG. 1 shows the recording side of a digital VTR.
2 shows a configuration of a provided video data processing circuit. FIG.
In, the input terminal indicated by 1 is
Video data is provided. This video data is
Is supplied to the conversion circuit 2. The present invention relates to different types of components.
Color video signal, and process the processed data.
To record data on magnetic tape with a rotating head
Here, SD, SD wide, and SD-L
It is intended for processing of different types of video signals. FIG.
Is for SD signals with an aspect ratio of (4: 3)
It is. The format of the SD signal is shown below. 525/60 (SD60) system Sampling frequency: 13.5 MHz Number of samplings / line: 858 Frame rate: 29.97Hz Line frequency: 15.734 kHz Effective pixel: Y 720 (H) x 480 (V) CR, CB 180 (H) x 480 (V) 625/50 (SD50) system Sampling frequency: 13.5 MHz Number of samplings / line: 864 Frame rate: 25Hz Line frequency: 15.625 kHz Effective pixel: Y 720 (H) x 576 (V) CR, CB 360 (H) x 288 (V) Component-based luminance signal Y and color
To process the difference signals CR, CB, the macroblock is
Stipulated. In the SD60 system, as shown in FIG.
, Four Y blocks and 1 at the same position in one frame
A total of 6 blocks of U blocks and one V block
Construct one macroblock. As for the Y signal, FIG.
As shown in B, the total number of DCT blocks in one frame is
(90x60 = 5400) for the color difference signal.
Is, as shown in FIG. 2C, this is (22.5 × 60 = 1
350), for a total of 8100 DCT blocks / one frame.
There is a frame. Therefore, 8100 ÷ 6 = 1350
This is the number of macro blocks in one frame. In the SD50 system, as shown in FIG.
, Four Y blocks and 1 at the same position in one frame
U blocks or one V block (line sequential)
) Constitute one macroblock. Y signal
As a result, as shown in FIG.
The number of locks is (90 × 72 = 6480).
For the signal, as shown in FIG. 2F, this is (45 × 3
6 = 1620), and as a whole9720DCT block
/ 1 frame exists. Therefore,9720$ 6 =16
20Is the number of macroblocks in one frame. FIG. 3 shows that the aspect ratio is (16: 9).
This indicates an SD wide format. SD Wide is
It is specified in the following format. 525/60 (SD Wide 60) system Sampling frequency: 18 MHz Number of samplings / line: 1144 Frame rate: 29.97Hz Line frequency: 15.734 kHz Effective pixel: Y 960 (H) x 480 (V) CR, CB 240 (H) × 480 (V) 625/50 (SD Wide 50) system Sampling frequency: 18 MHz Number of samplings / 1 line: 1152 Frame rate: 25Hz Line frequency: 15.625 kHz Effective pixel: Y 960 (H) x 576 (V) CR, CB 480 (H) x 288 (V) Macro block for SD Wide 60 system
The configuration of the lock is the same as that of the SD60 as shown in FIG. 3A.
It is. For the Y signal, all DCT blocks of one frame
3B, (120 × 60 = 72)
00), and the color difference signals are as shown in FIG. 3C.
This is (30 × 60 = 1800), which is 1
There are 0800 DCT blocks / one frame. Follow
10800 ÷ 6 = 1800 is a macro in one frame
This is the number of blocks. FIG. 3D shows the SD Wide 50 system.
In the same way as the SD50, a macro block is
You. As for the Y signal, as shown in FIG.
The total number of DCT blocks in the system is (120 × 72 = 864)
0), and the color difference signals are as shown in FIG. 3F.
In addition, this is (60 × 36 = 2160).1
2960There is a DCT block / one frame. Follow
hand,12960$ 6 =2160Is a macro in one frame
This is the number of blocks. FIG. 4 shows an aspect ratio of (4: 3).
However, the data amount is halved, and S can be recorded for a long time.
1 shows the format of DL. SD-L has the following format
Specified in the mat. 525/60 (SD-L60) system Sampling frequency: 9 MHz Number of samplings / line: 572 Frame rate: 29.97Hz Line frequency: 15.734 kHz Effective pixel: Y 480 (H) x 480 (V) CR, CB 120 (H) x 480 (V) 625/50 (SD-L50) system Sampling frequency: 9 MHz Number of samplings / line: 576 Frame rate: 25Hz Line frequency: 15.625 kHz Effective pixel: Y 480 (H) x 576 (V) CR, CB 240 (H) x 288 (V) The structure of a macro block in the case of SD-L60
As shown in FIG. 4A, SD60 and SD wide
And 60 are the same. FIG. 4B shows the Y signal.
Thus, the total number of DCT blocks in one frame is (60 × 6
0 = 3600), and the color difference signal is shown in FIG.
As shown, this is (15 × 60 = 900),
With body54There are 00DCT blocks / one frame.
Therefore,5400 ÷ 6 = 900 is a macro in one frame
This is the number of blocks. In the SD-L50 system, as shown in FIG.
Thus, the macro block is configured similarly to the SD50.
You. As for the Y signal, as shown in FIG.
The total number of DCT blocks in the system is (60 × 72 = 4320)
As shown in FIG. 4F, the color difference signal
This is (30 × 36 = 1080), and as a whole6480
There is a DCT block / one frame. Therefore,64
80$ 6 =1080Is the number of macroblocks in one frame
It is the number. The configuration of the recording system shown in FIG.
To explain again, in the blocking circuit 2, the raster
The video data in the scanning order is (8) as illustrated in FIG. 5A.
× 8) is converted into data having a DCT block structure.
The output of the blocking circuit 2 in FIG.
It is supplied to the road 3. In the shuffling circuit 3, the tape
Errors due to longitudinal scratches, clogs on the head, etc.
Focus and make correction impossible, resulting in poor image quality
To prevent it from being noticeable, for example,
As a unit, a macro block is
Shuffling is performed. The output of the shuffling circuit 3
It is supplied to a DCT (cosine transform) circuit 4. DCT times
From the road 4, as shown in FIG.
The coefficient data of AC1 to AC63 is generated. (8 × 8) coefficient generated by DCT circuit 4
The DC component DC of the data is supplied to the packing circuit 10.
And 63 of them, AC1 to AC63, are delayed.
The signal is supplied to a quantization circuit 6 via a path 5. AC coefficient
As shown in FIG. 5B, the data is stored in the zigzag scan order.
Transmitted in order from low AC to high AC
Is done. In addition, the coefficient data of this AC is
And the activity generating circuit 8. delay
The circuit 5 determines an appropriate quantization number QNO in the estimator 7.
And a delay amount corresponding to the time required to perform the operation.
The quantization number QNO from the estimator 7 is
It is supplied to the packing circuit 10. In the quantization circuit 6, the AC component in the coefficient data is
AC1 to AC63 are requantized. That is,
In the quantization step, the coefficient data for AC is divided and
The quotient is converted to an integer. If this quantization step is estimator 7
They are determined by the quantization numbers QNO. digital
In the case of a VTR, processing such as editing is performed in one field or
Is performed in units of one frame, so one field or
Indicates that the amount of data generated per frame must be less than the target value.
It is necessary. Data generated by DCT and variable length coding
Since the data amount changes depending on the pattern to be encoded,
Field or buffer shorter than one frame period
To reduce the amount of data generated by the
Buffering processing is performed. Here, 5 sync
Buffering unit to be used in the lock data area
Knit data (30 DCT blocks for SD, S
(40 DCT blocks for D-wide and SD-L)
Is buffered so that Buffery
Shortening the buffering unit
Simplification of buffering circuit, such as reducing memory capacity
It is for conversion. The activity generating circuit 8 has a function of D
The amount of AC component is checked in units of CT blocks, and the DC
2-bit activity indicating T block activity
Generate the activity code AT. As an example,
The absolute value of coefficient data AC1 to AC63
Count the number of items above, and show the
The activity code AT is generated. As an example, below
The activity code AT described above is generated. Count value is (0-10): (00) The count value is (11-18): (01) The count value is (19 to 25): (10) The count value is (26-63): (11) The count value is the AC component of the DCT block.
It represents a measure of quantity. Therefore, to control the amount of generated data
When the AT is (00) and the AC component is small, the quantum
It is necessary to reduce the conversion step, while AT is (1
In 1), when there are many AC components, the quantization step should be increased.
There is a need to. Thus, the quantization step is determined.
Activity is used as a guide. This
The activity code AT is calculated by the estimator 7 and the package.
Is supplied to the switching circuit 10. The output of the quantization circuit 6 is a variable length coding circuit 9
And run-length coding, Huffman coding, etc.
Done. For example, the continuous number of "0" in the coefficient data of the code
Is stored in ROM.
Variable-length code (encoded
Output) is employed.
The code signal from the variable length coding circuit 9 is used as a packing circuit.
10 is supplied. The packing circuit 10 has a code signal
Is converted to byte-wide data. Packing circuit 10
The output is supplied to the framing circuit 11. Framed times
Road 10 has a code signal and activity code A
T forms the allocated data. In the framing circuit 11, a packing circuit
10, the synchronization signal, the quantization number QN
O, ID signal and auxiliary code AUX are added. And
From the framing circuit 11, data of a sync block configuration is provided.
Appears. The output of this framing circuit 11 is parity
The error correction code is supplied to the generation circuit 12 and is not encoded.
Is done. A product code is used as an error correction code.
To the horizontal and vertical data.
The encoding of the code-Solomon code is performed. Horizontal
The error correction code in the vertical direction is called the inner code,
The error correction code is called an outer code. Inner code is 1 sync
It does not apply to the data contained in the data area of the block.
Thus, a horizontal parity PT is generated. Vertical parity only
May be included. During variable speed playback,
Data extracted as a link block is treated as valid.
Error correction using the inner code is performed. The output of the parity generation circuit 12 is output terminal 1
It is taken out to 3. Although not shown, this recording data
2 rotations via channel coding circuit and recording amplifier
It is supplied to a head and recorded on a magnetic tape. The estimator 7 has a function of the buffering unit.
The amount of generated data can be less than or equal to the target value, and
The quantization step having the smallest value is determined. In addition,
Referring to the activity code AT, the DCT block
An appropriate quantization step is determined for each. Figure 6 shows the estimate
1 shows an example of the container 7. n quantization circuits 20₁, 20_Two,
..., 20_nTo the coefficient data from the DCT circuit 4.
Data is supplied. These quantization circuits 20₁~ 20_nTo
Are different quantum values from the quantization step generation circuit 21.
, Δn are supplied respectively.
It is. At each quantization step, the result is divided and converted into an integer.
Output from the variable length encoding circuit 22₁~ 22_nTo each
Be paid. These variable length coding circuits 22₁~ 22
_nIs a variable length coding circuit that actually generates a variable length code
Unlike the code No. 9, the code length data of the variable length coded output is generated.
Live. The data of this code length is stored in the accumulation circuit 23.₁~ 23
_nRespectively. Accumulation circuit 23₁~ 23_nTo
Is supplied with a reset pulse from the terminal 24. Accumulation times
Road 23₁~ 23_nOccurs in the buffering unit
To calculate the amount of code signal
A reset pulse is generated for each reset. Accumulation circuit 23₁~
23_nIs supplied to the determination circuit 25. The target value from the terminal 26 is supplied to the judgment circuit 25.
Am and the activity code AT from the terminal 27
Supplied. Accumulation circuit 23₁~ 23_nOutput and target value A
m is compared with the target value within the range not exceeding the target value Am.
Activity close to the value Am and of the DCT block
A quantization step adapted to the tee is determined. This judgment
The quantization number QNO is determined by the output, and the output terminal 28
Is taken out. This quantization number QNO is used as the quantization circuit 6
Supplied to The quantization circuit 6 quantizes the quantization number.
A ROM for converting into steps is provided. The estimator 7 is limited to the configuration shown in FIG.
A method of sequentially performing quantization at different quantization steps
For example, various configurations can be adopted. Also, all orders
Common quantization step for coefficient data of
The quantization step is not limited to
May be used. In other words, the coefficient data for the AC
Divide into multiple groups according to the number and quantize step
For each of multiple groups
I do. And when different quantization steps are used,
Multiple sets of quantization steps for a group of
Quantization is performed using a set of multiple quantization steps.
The optimal quantization step is determined with reference to the result. Further, two tracks are placed on the magnetic tape.
Are simultaneously driven by two closely spaced rotating heads
Is formed and one frame of data is divided into multiple tracks
Recorded. Figure 7 shows the number of tracks of each type described above.
Show. One frame for SD50 and SD Wide50
Data is recorded on 12 tracks, SD60 and
And SD Wide 60, one frame contains 10 data
Recorded on the track. SD-L50, SD-L60
Each of them has 6 and 5
One frame data is divided and recorded on the track. What
Note that the PCM audio signal is error-correction-coded,
In the audio data recording section provided in one track
Be recorded. One frame of each type of video signal described above
As can be seen by comparing the number of macroblocks per
D-wide and SD-L types are SD type
4/3 times the number of macroblocks. One recording track
The number of sync blocks recorded in the
When set properly, SD wide and SD-L type
Recorded data is compressed to 3/4 of that of SD type
You. FIG. 7B shows one buffering unit (B
Indicates the number of DCT blocks included in UF). SD'sIf
In the data area of 5 sync blocks, 5 macros
Block (30DCT block) code signal
Buffering is done as Paraphrase
If the buffering unit (5 macroblocks)
Data amount is within the data area of 5 sync blocks.
Is controlled as follows.SD wide andIn SD-L,
6 macro blocks + 4 DCT blocks = 40 DCT blocks
Is included in one buffering unit. FIG. 7C shows one track on the magnetic tape.
As shown, the buffering units BUF0-BUF
26 data are recorded and each buffering unit
Is composed of 5 sync blocks SYNC1 to SYNC5.
It is. This track format uses unified processing.
For the sake of clarity, the same
You. The shuffling performed by the shuffling circuit 3
A description will be given of the switching process. One frame of SD50 data
Is basically shuffled.
Will be described. One frame (45 ×
36) video data of a macroblock is horizontally divided for 5 minutes
Crack. This means that the buffering unit has 5 macro blocks.
This is because it is composed of a lock. In addition, one frame
The data is equally divided in the vertical direction by the number of tracks (12). Obedience
Therefore, as shown in FIG. 8, (9 × 3 = 27 macroblocks)
H) is formed. This is supermak
I will call it a rock block. In one frame, (5
× 12 = 60 super macroblocks). For each row of 12 super macroblocks
And figure8As shown in the figure,
Specify the lock number. Super macro block number is 1 frame
Corresponding to the track number on which the
You. Change the arrangement of super macro block numbers between columns.
By doing so, shuffling is achieved. The 27 macro blocks in each super macro block
As shown in FIG.
Number is assigned. 5 macros of buffering unit
When collecting blocks, the (super macro block number
-Macroblock number). An example
For example, (0-0) of the buffering unit BUF0 is
From the super macro block of number 0 to the
It is a collection of rock blocks. The shuffled video data is
DCT transform, buffering process, variable length code
Then, the data is recorded on a magnetic tape. Continuous
2 frames of video data and corresponding recording data
Are recorded in the track format shown in FIG. this
Represents what is shown in FIG. 7C over two frames.
It is. The odd frame tracks and even frame tracks
The recording order is changed between the tracks of the game.
By the shuffling process described above, the two rotating heads
Error caused by scratches on the clog or tape on one side
Can be distributed, so error correction is easy.
Becomes An SD50 system and an SD60 system to be described later
Stem included in one buffering unit
5 sync blocks (SYNC1 to SYNC5)
Are shown in FIG. Each sync block has
Contains one macroblock and one buffering unit
Contains 5 macroblocks (= 30 DCT blocks)
I will. The length of one sync block is, for example, 90 bytes.
It is Block synchronization signal at the beginning of the sync block
SYNC (2 bytes) is located, followed by the ID signal
To position. This ID signal is a 2-byte ID signal (ID
0, ID1) and parity IDP for ID signals
(1 byte). 77 bytes of the remaining 85 bytes
Is the data area, and the last 8 bytes are the product code
Is the parity of the inner code. At the beginning of the data area,
1-byte quantization number Q for identifying a quantization step
NO and auxiliary code AUX are located. Then 75
Byte is data (variable length code or outer encoded paris
T). One sync block includes one macro block.
(YYYY, U, V) code signal and each DC
Activity code AT and T
And a motion flag M are inserted. The motion flag M is DCT
A 1-bit flag indicating the presence or absence of motion detected for each block.
It is a lag. In FIG. 1, for simplicity, the motion detection circuit is:
Omitted. Each of the 75-byte areas has a fixed length,
For example, four areas with a length of 18 bytes and the beginning of the fraction
Area. For every 18 bytes,
DC generated in the four Y DCT blocks
The component (9 bits) is arranged, and then the motion flag M and
And an activity code AT. 18-buy
Area is 12 bytes and 6 bytes
Each is divided. As a result, in addition to the first fractional area,
Eight areas are formed. The first area is a fixed AC-H area.
It is. The next 12-byte area including the DC component is Y AC
-L area, 6-byte area is fixed AC-H area
The rear. These bytes are used to duplicate standard symbols.
Prepare several sheets, and for each encoded output, 1DCT
Examine the distribution of the number of bytes in the encoded output corresponding to the block
Is selected by In the next 18-byte area,
AC-L area, DC (for example, U) DC,
For lug M, activity code AT, AC-L
Area. In addition, the next 18-byte area
A is the AC-L area of Y and the fixed AC-H area,
The last 18-byte area is the AC-L area of Y,
(Eg, V) DC, motion flag M, activity
This is an area for code AT and AC-L. Each A
The AC-H component protruding from the CL area is the first AC
-Packed in order from the H area. Within the AC-L area
If there is an empty area, that is, a variable AC area,
Here, the protruding AC-H component is packed. The ID signal has a frame ID, a format,
Identification bit, 2 bits indicating type of recording data, sync
Includes block address and parity byte IDP. Fret
The frame ID is inverted for each frame. The identification bit is
Format for digital VTR of the embodiment of
External formats, such as those on data storage devices
To identify When this is "1", the digital VT
R means the format. When this is "0", other
Means the format. The recording data identification bit is
Indicates the type of recording data (video, audio, etc.). Sa
Furthermore, the sync block address is one frame of data.
And all of the thin tracks recorded on multiple tracks
This is the address that is serially numbered for the block. Further, the auxiliary code AU in the data area
X is also a kind of ID signal, and is a broadcast form of a video signal.
Information such as an expression and an audio mode is included. data
Record quantization number QNO and auxiliary code AUX in area
The reason is that the error correction code of the ID signal is
Error correction code for data in the data area
This is because the correction ability is high. The sync block data described above is
It is configured by a memory conversion circuit 11. This sync block
Has been improved in the following points. First,
Within one sync block, code signal of approximately one macro block
Signal exists, so that one sync block
Data reproduced in units of data can be used effectively. No.
2, a fixed area is provided as an AC-H area.
However, since these are dispersed, the AC-H component
Can be reduced due to a propagation error. Third
The fixed AC-H area is provided before the first DC component
Have been. Therefore, it protrudes from the sync block
The AC-H component is packed earlier.
Lowers the chances of spanning the sync block
You. Fourth, the AC-
The H component is packed from the beginning of the fixed AC-H area.
Thus, the AC-H component has address information. So
As a result, even if there is an error in the previous sync block,
Refresh with sync block. The above-described shuffling processing of SD50 and
Track format for other types of video signals
Even expand. Hereafter, videos of types other than SD50
The signal processing will be described. First, the SD60 video signal
The processing will be described with reference to FIG. In one frame,
As shown in FIG. 11, (22.5 × 60 macroblocks)
Video data exists. This is (45 × 30 macro
Block). This modification is based on the 22.5 macro block of each row.
22 macroblocks and fractional 0.5 macroblocks
And the second, fourth,... 60th even-numbered rows
The 22 macroblocks located in the odd-numbered rows are
After the black block, and finally two 0.5
By combining the macroblocks into one macroblock.
Is done. As a result, the allocation of (45 × 30 macro blocks)
A row is obtained. In SD60, one frame of data is 1
It is recorded on track 0, so this is
Crack. On the other hand, the horizontal direction is divided into 5 equal parts as in the case of SD50.
You. Therefore, an array of (5 × 10 super macroblocks)
Is formed. For each column of 50 super macroblocks,
Numbering according to the shuffling pattern
It is. Like the SD50, 27 Macs in the super block
The block is numbered. And SD6
0 is the same as the track format shown in FIGS. 7C and 9
It is. In SD60, one frame of data contains 10 lines.
Since it is recorded on the track, (m = 9). This S
The data structure of one buffering unit of D60
This is shown in FIG. 10 as in the case of the above-described SD50. Next, FIG.
It will be described with reference to FIG. 1 of (60 × 36 macro blocks)
The video data of the frame is vertically divided by the number of tracks (1
It is equally divided in 2). In the horizontal direction, the buffering unit
For a set of 6 macroblocks + 4 DCT blocks,
(3 × 36 macroblock) at end (indicated by A and B codes)
), And 54 macroblocks are divided into six equal parts. The result
As a result, except for both ends (6 × 12 super macro block)
C) is formed. A super macro block consisting of 27
It is the same as that described above composed of black blocks. Each of the 12 super macroblocks in each column
Columns are numbered according to shuffling patterns
Is made. SD Wide 50 track format
Is the same as FIG. 7C and FIG. For example, buffer
(0-0) of the switching unit BUF0 is the number 0 of each column.
The macro block of number 0 is collected from the super macro block.
6 macro blocks. In SD Wide 50,
(M = 11). Shafts at both ends of one frame image
The fling processing will be described later. FIG. 13 shows the processing of the SD wide 60.
In one frame, as shown in FIG.
Black block) video data. This is (6
(0 × 30 macro blocks). This deformation
Translates 30 macroblocks in each row into 27 macroblocks
One leftmost macroblock and two rightmost macroblocks
Divided, located in the second, fourth,... 60th even-numbered row
27 macro blocks in odd-numbered rows
Connect after block. 3 Macs at both ends of odd-numbered row
Block is added to the left end, and the three
Collect the black blocks on the right edge. Thereby, (60 ×
30 macroblocks) is obtained. It on both ends
The reference numerals A and B are given respectively. In the SD wide 60, one frame of data
Is recorded on 10 tracks.
Divide by 0. On the other hand, 54 blocks excluding both ends A and B
Divide horizontally into six equal parts. As a result, except for both ends
(6 × 10 super macroblocks) are formed. Sue
A macro block is composed of 27 macro blocks.
This is the same as described above. Each of the (6 × 10) super macroblocks
For the rows, corresponding to the shuffling pattern (0-
9) is numbered. And SD Wide 60
The track format is the same as in FIG. 7C and FIG.
You. In the SD wide 60, (m = 9). 1 frame
The processing at both ends of the program image will be described later. FIG. 14 is a block diagram of the SD-L50 system shuffling.
3 shows a ring process. In this system, one frame
(30 × 36 = 1080 macro blocks) and 27
One frame in a super macro block including a DCT block
Is divided. As shown in FIG.
18 (1 × 6 macroblock) strikes from the side
And cut out the remaining 972 macroblocks
Is divided into super macroblocks. Each super macrob
The macro block is numbered (0-26)
It is the same as that described above including the step. This division is
Rather, the jigsaw puzzle is formed as illustrated. M (= 6) super macrobs lined up in the vertical direction
A shuffling number is assigned to each lock. SD-L50
Track format is the same as FIG. 7C and FIG.
You. The peripheral 108 macro blocks are denoted by A and A in FIG.
As shown by the symbols B and C,
Divided into groups of rock blocks. This one frame
The processing at both ends of the image will be described later. FIG. 15 shows the processing of the SD-L60. 1
In frames, video of (15x60 macroblocks)
Data exists. This is the (30 × 30 macro block
H). This deformation is the second, fourth, ...
.15 macroblocks located in the 60th even-numbered row
Connected after 15 macroblocks in odd-numbered rows
You. Furthermore, the 30 macroblocks with a plus sign are:
14 macroblocks except the leftmost one in the first row,
One macroblock at the left end of the line and one at the right end of the 60th line
14 macroblocks except for, and one macro at the right end of line 59
And rock blocks. 60 macroblo with minus sign
The block consists of the leftmost 30 macroblocks of the odd-numbered rows,
A total of 60 with the rightmost 30 macroblocks of the even-numbered row
Contains macroblocks. These peripheral macro blocks (total 90 macro blocks)
Black block) as shown in FIG.
Black block). Surrounding macroblocks
Excluding 810 macro blocks, 30 super macro blocks
Divided into Each super macroblock is (0-2
Including the macroblocks numbered in 6)
Same as described above. This division is not rectangular, but
In a jigsaw puzzle. M (= 5) super macrobs lined up in the vertical direction
A shuffling number is assigned to each lock. SD-L60
Track format is the same as FIG. 7C and FIG.
You. The 90 peripheral macroblocks are denoted by A,
As shown by the symbols B and C, each
Divided into groups of rock blocks. This one frame
The processing at both ends of the image will be described later. For SD Wide and SD-L systems
FIG. 16 shows the processing of peripheral macro blocks
Will be explained. For the SD Wide 50 system,
As shown in FIG. 12, each of the (3 × 36 macroblocks)
H) surrounding macroblocks A and B occur. SD
In the wide 60 system, as described above and shown in FIG.
And the surrounding macros of (3 × 30 macroblocks)
Blocks A and B occur. Put these two together
Is divided vertically by three macroblocks.
As a result, the resulting peripheral super macroblock (= 6 ×
3 = 18 macroblocks).
As shown in FIG. In addition, (18
Black block = 27 × 4 = 108 DCT block)
You. In the SD-L50 system, as described above, FIG.
As shown in FIG. 4, each of the (1 × 36 macroblocks)
H), surrounding macroblocks A, B and C occur.
In the SD-L60 system, as described above and shown in FIG.
And the surrounding macros of (1 × 30 macroblocks)
Blocks A, B and C occur. As shown in FIG.
As shown in the figure, the combination of these
Divide by locks. The resulting peripheral super
Within a macroblock (= 3 × 6 = 18 macroblocks)
For each, as shown in FIG.
Is attached. Further, the peripheral super macro blocks a to
r, as shown in FIG.
Each T block is divided into 27 (n-0 to n-26)
You. Here, in the SD Wide 50 system, (n = 0 to
11), and in the SD Wide 60 system, (n = 0)
9), and in the SD-L50 system, (n = 0 to
5), and in the SD-L60 system, (n = 0 to
4). The SD memory shuffled as described above
And one buffering unit of SD-L (= 40
The data of the DCT block) includes five sync blocks shown in FIG.
Recorded as lock configuration. Data for each sync block
In front of the data area, (6 DCT blocks: 1 macro block)
Locked) encoded output. Upper three thin
(6DCT block) in the remaining data area of the block
(Macroblock: 1 macroblock). So
As a result, 36 DCT blocks are arranged. Shown by bold line
So, the remaining data area of the lower two sync blocks
A 4DCT block is arranged in the block. Like this 40D
Allocate CT blocks in the data area of 5 sync blocks
Can be placed. Here, the SD tag described above and shown in FIG.
The sync block configuration of the
And the sync block configuration of SD-L. SD card
, The encoded output of the Y DCT block is 12 bytes.
Is inserted in the section of the unit length, but the data amount is reduced to 3/4
Since it is compressed, this is (12 × 3/4 = 9 bytes)
G). Also, the coded output of the DCT block of C
Is inserted in the 6-byte section, but the data amount is
Since it is compressed to 3/4, this is converted to (6 × 3/4 =
(4.5 bytes / 5 bytes). In addition, a fixed AC
-Change the H area from 6 bytes to 4 bytes. The fourth division formed by dividing it into four every 18 bytes
In the first, second and third divided areas, (Y, Y)
(C, AC-H, Y) (Y, C, AC-H)
I do. As a result, DC components are regularly located every 9 bytes.
The resulting sequence is The fourth of the remaining 5 sync blocks
In the split area, (Y,
Y) (C, AC-H, Y) (Y, C, AC-H) (Y,
Y) Compatible with 10 DCT blocks of (C, AC-H, Y)
Stuff your data. Thus, every 18 bytes
The position of the stream is located, and data is
In FIG. 10 and FIG.
It exists in common between the data structures of FIG. The first three buys
That there is a fixed AC-H area for
Same layout of lug M and activity code AT
It is. Of course, in the SD type, (Y = 12 bytes, C
= 6 bytes), SD wide and SD-L type
Then, (Y = 9 bytes, C + AC-H = 9 bytes)
And has a periodicity of 18 bytes. Referring to FIG.
The advantage of the data structure of the sync block described in FIG.
7 also occurs similarly. In the data structure shown in FIG.
The T block correctly recreates the top three sync blocks.
When created, contributes to the playback image as one macroblock
can do. Also, the 4DCT block is used for other blocks.
Correct the 2DCT block included in the buffering unit.
When the image is reproduced properly, the image is reproduced as one macro block.
Can be contributed to. Consider error correction coding
When taking this into account or during variable speed playback,
Lock, in particular, 4DCT block is one macroblock
There is a high risk of not being able to contribute. The peripheral supermac shown in FIG.
4DCT block obtained by the
It is arranged in the data area enclosed by the thick line. Therefore, this
Even if the 4DCT block becomes error data,
The inside can be degraded inconspicuously. Image during variable speed playback
The image can be similarly improved. In addition, multiple
Do not fix 6DCT blocks that span the sync block
It is more preferable to make a round. Further, the present invention is different from the SD type.
HD (high resolution) type
Double the number of recording tracks of the SD signal for the video signal
It can also be applied when recording in This HD type is
Data structure similar to the SD type
You. [0079] According to the present invention, a recording / reproducing disk is provided.
Digital video signals of different types
Ensure that the data structure of the sync block has the same regularity
Can be. Therefore, processing at the time of recording and reproduction or
The circuit configuration can be simplified.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of a recording data processing circuit of a digital VTR to which the present invention is applied. FIG. 2 is a schematic diagram used for describing an SD type video signal. FIG. 3 is a schematic diagram used for describing an SD wide type video signal. FIG. 4 is a schematic diagram used for describing an SD-L type video signal. FIG. 5 is a schematic diagram used for describing DCT. FIG. 6 is a block diagram illustrating an example of an estimator. FIG. 7 is a schematic diagram illustrating the number of tracks, a buffering unit, and a track format according to the embodiment; FIG. 8 is a schematic diagram for explaining shuffling of the SD50 system. FIG. 9 is a schematic diagram showing a track format on a tape. FIG. 10 is a schematic diagram illustrating a data configuration of a buffering unit in the SD system. FIG. 11 is a schematic diagram for explaining shuffling of the SD60 system. FIG. 12 is a schematic diagram for explaining shuffling of the SD Wide 50 system. FIG. 13 is a schematic diagram for explaining shuffling of the SD Wide 60 system. FIG. 14 is a schematic diagram for explaining shuffling of the SD-L50 system. FIG. 15 is a schematic diagram for explaining shuffling of the SD-L60 system. FIG. 16 is a schematic diagram for explaining shuffling around a SD wide and SD-L system. FIG. 17 is a schematic diagram illustrating a data configuration of a buffering unit in the SD wide and SD-L systems. [Description of Signs] 3 Shuffling circuit 4 DCT circuit 6 Quantization circuit 7 Estimator 11 Frame formation circuit

Claims (1)

(57) [Claim 1] Cosine transform and variable length encoding of a digital video signal are performed, and the data amount of encoded output in a predetermined period is stored in the data area of N sync blocks. Buffering means for controlling to fit,
Means for recording the output of the buffering means as a plurality of tracks on a recording medium in the form of a sync block, the method comprising: recording a first digital video signal in a digital video signal recording apparatus. In this case, the video data arrangement area of each sync block is divided into first, second, third and fourth areas, and the first, second, third and third areas formed by the N sync blocks are divided. In the fourth divided area, M of the first digital video signal
Coded outputs of the cosine transform blocks, and the first, second, third and fourth
Encoding the first digital video signal in an area
When arranging the outputs, the first, second, third and third
And a luminance signal component at a predetermined position in each of the four divided areas.
And the luminance and chrominance signal components
And the number of the cosine transform blocks recorded on the track is 4/3 compared to the first digital video signal.
When recording a second digital video signal of the fold, the M-number of the cosine transform first the encoded output of the block, and placed in the second and third of the divided area, the 1 / 3M number of The cosine transform block is arranged in the fourth divided area, and the first, second and third areas of each of the sync blocks are arranged.
The encoded output of the second digital video signal
When arranging, the first, second and third divided areas
The DC component of the luminance signal component is
And the order of the luminance and chrominance signal components is predetermined.
A framing method for a digital video signal recording device, characterized in that: