JP3394480B2 - Semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ball grid array (BGA) type semiconductor device, and more particularly to a wiring structure on a chip of a chip size BGA having bumps for external connection on the chip.

[0002]

2. Description of the Related Art As a conventional example of a chip size BGA having bumps for external connection on the chip, Japanese Patent Laid-Open Nos. 7-321157 and 10-18965 are known.
No. 0, JP-A No. 11-121518, and the like.

For example, FIG. 6A and FIG.
32A is a view showing an example of a film carrier semiconductor device disclosed in Japanese Patent No. 3211157, FIG.
(B) is a sectional view showing a section taken along line XX 'of (a).

This film carrier semiconductor device comprises
A wiring layer 63 obtained by processing a metal foil of copper or the like into a desired shape by etching or the like, and a film portion corresponding to a portion directly below the wiring layer 63 provided with a region connected to an electrode of a semiconductor chip. The film carrier is made of an organic insulating film 64 such as a polyimide resin having an opening 65 formed therein. On the other hand, the semiconductor bare chip 61 has electrode pads 62 arranged on the outer peripheral edge thereof, and each pad 62 is electrically connected via an adhesive layer in the state where bumps or barrier metals are not formed. 50 is a passivation film on the chip 61,
The chip 61 and the film carrier are adhered by an adhesive tape 67. Further, bump electrodes 66 made of, for example, solder are formed as external connection pads of the film carrier. As shown in FIG. 6A, the bump electrodes 66 are arranged in a grid pattern at the same pitch, for example, by utilizing almost the entire surface of the portion where the semiconductor bare chip is mounted on the film carrier. The wiring layer 63 is formed on the chip-corresponding surface side of the film carrier, and one end thereof is connected to the bump electrode 66 through the via hole 69.

Further, FIGS. 7 (a) and 7 (b) show Japanese Unexamined Patent Publication No. 10-
It is a figure which shows the semiconductor device disclosed by 189650 gazette, (a) is a top view, (b) is sectional drawing.

In this semiconductor device, a resin substrate 72 is bonded onto a semiconductor element 70 with an adhesive tape 71, and electrodes 73 of elements arranged in the central portion of the semiconductor element 70 and a surface conductor 74 of the resin substrate 72 are made of metal. With the structure in which the thin wires 75 are electrically connected, the connection region is sealed with the sealing resin 76, and the solder balls 77 are provided as external terminals, a semiconductor device having a size equivalent to that of a semiconductor element is realized.

Further, FIGS. 8 (a), 8 (b) and 8 (c) are views showing a semiconductor device disclosed in Japanese Patent Application Laid-Open No. 11-121518, which is a prior application by the present inventor. It is a figure and a partially expanded sectional view.

Referring to FIG. 8, in this semiconductor device, a chip 81 is covered with a resin sheet material 83 except for a pad 82, and the pad 82 is placed up to a solder ball mounting position on the resin sheet material 83. A metal layer 84 is formed on the resin sheet material 83 from a portion thereof, and a resin layer 85 for a cover coat is left while leaving the solder ball mounting portion.
The solder ball 86 is mounted on the above-mentioned solder ball mounting portion after the coating.

[0009]

In any of the conventional chip size BGA type semiconductor devices described above, a film carrier, a resin substrate or a film carrier provided with wiring for connecting pads on the semiconductor chip and bumps for external connection is used. An insulating substrate is bonded to the surface of the chip via an insulating adhesive tape or the like to form bumps on the film carrier or the bump forming portion or land portion on the substrate, or the resin sheet is bonded on the chip except the pad portion. , After forming a wiring and a land portion for connecting the pad portion and a land portion for mounting a solder ball for external connection on this resin sheet, and further covering the land portion with a resin to form a protective film for the wiring, soldering The ball is mounted on the land, and no consideration has been given to the problem of noise on the wiring that connects the pad and bump. It was bought.

That is, since the chip size BGA type semiconductor device is mounted with the surface of the chip on which the external connection bumps are formed facing the mounting substrate, the mounting substrate is connected to the pads and bumps of this chip after mounting. The distance between the wiring on the chip and the wiring on the mounting board is very short, and the wiring connecting the pads and bumps is closely attached to the chip surface. If the chips are short and no measures are taken, there is a problem that they are easily affected by each other.

Therefore, an object of the present invention is to provide a chip size B
In a GA type semiconductor device, after mounting, mutual interference with the wiring on the mounting substrate is prevented, and further, without any special processing on the chip side, the wiring connecting the pad and the bump portion and the wiring inside the chip are mutually connected. Another object of the present invention is to provide a semiconductor device capable of preventing the above interference.

[0012]

Therefore, a semiconductor device according to the present invention is provided with a semiconductor chip, a first insulating resin, a wiring, a second insulating resin, which are all formed on the chip.
At least a bump for external connection and a first metal film,
The wiring is formed on the chip via a first insulating resin and connects the bonding pad of the chip to the bump, and the second insulating resin is formed on the upper layer of the wiring and covers the bump formation region. Except for the bumps, the first metal film is formed on the second insulating resin to cover the entire surface of the chip except the bumps, and the bumps are scattered all over the chip.
And have a plurality of different slits and parts.

Another semiconductor device of the present invention is a semiconductor chip, a first insulating resin, a wiring, a second insulating resin, an external connection bump, and a first metal, which are all formed on the chip. At least a film, a third insulating resin, and a second metal film, the second metal film being formed on the chip through the third insulating resin, and the entire surface of the chip except the bonding pad portion of the chip And the wiring is formed on the first metal film via a first insulating resin film to connect the bonding pad of the chip and the bump, and the second insulating resin is The chip is formed on an upper layer of the wiring and covers the entire surface of the chip except the bump formation region, and the first metal film is formed on the second insulating resin and covers the entire surface of the chip except the bump portion. is doing.

At this time, the first metal film or the second metal film may be provided with a plurality of slits different from the bump forming portions scattered over the entire surface of the chip.

Further, at least the wiring and the first metal film are preferably formed of a wiring material containing copper as a main material.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a diagram for explaining a semiconductor device according to a first embodiment of the present invention, in which (a) is a schematic plan view,
(B) is a schematic sectional view taken along the line PP 'of (a). Further, FIG. 2 is an enlarged cross-sectional view of part A of FIG.
FIG. 3 is a plan view of the semiconductor device of the first embodiment before the first metal film is formed.

Referring to FIGS. 1 to 3, the semiconductor device 1 of this embodiment has a chip 2 in which a desired function is formed, and a first surface which covers the entire surface of the chip 2 except for the bonding pad 3. A first polyimide film 4 which is a first insulating resin, and a land 5 on which a solder ball for external connection formed at a predetermined position on the first polyimide film 4 is mounted.
A wiring 6 connecting the pad 3 and the land 5 formed on the first polyimide film 4, and a second polyimide film 7 as a second insulating resin covering the entire surface of the chip except the land 5. A first copper film 8 which is a first metal film formed on the second polyimide film 7 so as to cover the entire surface of the chip except the land 5 and not to expose the end portion to the land 5. A coating resin film 9 formed on the first copper film 8 so as to cover the entire surface of the chip except the land 5.
And a solder ball 10 which is a bump for external connection formed on the land 5.

Although not shown, the wiring 6 and the first copper film 8 are both a barrier metal such as titanium nitride (TiN) or titanium tungsten (TiW) and a low resistance metal film such as a copper film. It has a laminated structure.

The first copper film 8 is connected to a ground potential terminal (not shown) on the chip 1 so as to be fixed at the ground potential. Further, in order to relieve the stress due to the difference in the coefficient of thermal expansion from the second polyimide film 7, the first copper film 8 is appropriately slit 11 so that the first copper film 8 does not exist in a large integrated area. Has been formed.

Next, an outline of a method of manufacturing the semiconductor device 1 will be described.

First, the chip 1 having a desired function built therein.
Is formed on a wafer (not shown), and an electrical test for non-defective products has been completed. Polyimide is applied and patterned to expose the pads 3 of each chip 1 to form a first insulating resin. The polyimide film 4 of No. 1 is formed. Next, using a vacuum sputter device (not shown), TiN to be a barrier metal
Alternatively, TiW is evaporated to a thickness of about 200 nm, copper, which is a low resistance metal film, is continuously evaporated to a thickness of about 500 nm, and patterned to form the wiring 6.

Next, copper is plated at a thickness of about 10 μm to 15 μm on the portion where the bumps for external connection are to be formed to form a land 5, and a second polyimide film 7 is applied to a thickness of about 10 μm to form the land 5. Only the part of is exposed.

Next, TiN or TiW having a thickness of about 200 nm and a thickness of 500 n are formed on the second polyimide film 7.
Copper of about m is continuously deposited by a sputtering apparatus, and is patterned so that the end portion is not exposed at the portion of the land 5 other than the ground potential terminal to form the first copper film 8. At this time, the slit 11 is also formed at the same time.

Next, 10 to 5 coating resin is applied to the entire surface.
A coating resin film 9 is formed by applying a thickness of about 0 μm to expose the land 5. The coating resin film 9 adheres to the second polyimide film 7 through the slit 11 provided in the first copper film 8.

Next, a solder paste is applied to each land 5 to mount a solder ball, and each land 5 is reflowed.
Solder balls are bonded to each of them to form solder balls 10 which are bumps for external connection. After that, the wafer is cut into individual pieces by dicing or laser to complete the semiconductor device 1 of the present embodiment.

As described above, the semiconductor device 1 according to the present embodiment has the first copper film connected to the ground potential via the second polyimide film 7 on the wiring 6 connecting the pad 3 and the land 5. Since 8 is formed, it is possible to prevent mutual interference with the wiring on the mounting substrate after mounting.

Next, a semiconductor device according to the second embodiment of the present invention will be described.

FIG. 4 is a diagram for explaining a semiconductor device according to a second embodiment of the present invention, in which (a) is a schematic plan view,
(B) is a schematic sectional view taken along the line Q-Q 'of (a). Further, FIG. 5 is an enlarged sectional view of a B part in FIG.

The semiconductor device 20 of this embodiment is the same as that of the first embodiment in the plan view of (a), but there is a difference in sectional structure.

Specifically, referring to FIGS. 4 and 5, the semiconductor device 20 of the present embodiment covers the entire surface of the chip 2 excluding the pad 2 having the desired function and the pad 3 on the surface thereof. Third polyimide film 2 which is a third insulating resin
1 and a second copper film 22 that is a second metal film that covers the entire surface of the chip except for the pad 3 formed on the third polyimide film 21, and the second copper film 22. First polyimide film 4 which is the first insulating resin formed on top
A land 5 for mounting an external connection solder ball formed at a predetermined position on the first polyimide film 4, a pad 3 and a land 5 formed on the first polyimide film 4. A second polyimide film 7 as a second insulating resin that covers the entire surface of the chip except the land 6 and the wiring 6 to be connected.
And a first copper film 8 which is a first metal film formed on the second polyimide film 7 so as to cover the entire surface of the chip except the land 5 and not to expose the end portion to the land 5.
And a coating resin film 9 formed on the first copper film 8 so as to cover the entire surface of the chip except the land 5.
It has solder balls 10 which are bumps for external connection formed on the lands 5. The second copper film 22 is formed so that the end portion is not exposed at least at the pad 3, and is connected to a fixed potential, for example, the ground potential like the first copper film 8.

That is, the semiconductor device 20 of this embodiment
Is further provided with a third polyimide film 21 and a second copper film 22 that cover the entire surface of the chip except the pad 3 between the chip 2 and the first polyimide film 4,
Different from the first embodiment.

As for the manufacturing method, a chip 1 having a desired function is formed on a wafer (not shown), and polyimide is applied to a product which has been electrically tested to determine whether it is a good product or not. The pad 3 of each chip 1 is exposed to form a third polyimide film 21.

Next, TiN or TiW having a thickness of about 200 nm and a thickness of 500 are formed on the third polyimide film 21.
A second copper film 2 to be a second metal film is formed by continuously depositing copper having a thickness of about nm by a sputtering device, and patterning the end portions of the pad 3 other than the ground potential terminal so as not to be exposed.
1 is formed. At this time, slits (not shown) may be formed in the second copper film 21 as well.

Next, the polyimide is applied again and patterned to expose the pads 3 of each chip 1 to form the first polyimide film 4 serving as the first insulating resin. After that, the manufacturing process is the same as that of the first embodiment, and thus the description thereof is omitted.

By further providing the second copper film 22 which is connected to the ground potential and covers the entire surface of the chip surface except the pad 3 portion, the surface of the chip 2 is subjected to special treatment (shield plate formation, etc.). Pad 3 without applying any
It is also possible to suppress mutual interference between the wiring 6 connecting the wiring 5 and the land 5 and the inside of the chip 2.

The present invention is not limited to the above description of the embodiments, but various modifications can be made within the scope of the gist thereof. For example, the first copper film 8 or the second copper film 22
In the above description, both are connected to the ground potential. However, this may be a power supply potential or another intermediate potential as long as it is a fixed potential, and the first copper film 8 and the second copper film 22
And may have different potentials.

[0038]

As described above, the chip size BGA type semiconductor device having the bumps for external connection on the chip of the present invention is fixed on the upper and lower sides of the wiring connecting the bonding pads of the chip and the bumps with the insulating resin. By providing a metal film that is connected to the electric potential and covers substantially the entire surface of the chip,
The effect of preventing mutual interference with the wiring on the mounting board after mounting, and further preventing mutual interference between the wiring connecting the pads and bumps and the wiring inside the chip without any special processing on the chip side. Is obtained.

[Brief description of drawings]

1A and 1B are views for explaining a semiconductor device according to a first embodiment, in which FIG. 1A is a schematic plan view, and FIG.
It is a typical sectional view in a P'line.

FIG. 2 is an enlarged cross-sectional view of a portion A of FIG.

FIG. 3 is a plan view of the semiconductor device according to the first embodiment before a first metal film is formed.

4A and 4B are views for explaining the semiconductor device according to the second embodiment, in which FIG. 4A is a schematic plan view and FIG.
It is a schematic sectional drawing in the Q'line.

FIG. 5 is an enlarged sectional view of a B part in FIG. 4 (b).

FIG. 6 is a diagram showing an example of a film carrier semiconductor device disclosed in Japanese Patent Laid-Open No. 7-321157.
(A) is the top view, (b) is sectional drawing which shows the cross section along the XX 'line of (a) figure.

7A and 7B are views showing a semiconductor device disclosed in Japanese Patent Laid-Open No. 10-189650, wherein FIG. 7A is a plan view and FIG. 7B is a sectional view.

FIG. 8 is a diagram showing a semiconductor device disclosed in Japanese Patent Application Laid-Open No. 11-121518, which is a plan view, a sectional view, and a partially enlarged sectional view, respectively.

[Explanation of symbols]

1,20 Semiconductor device 2 chips 3 pads 4 First polyimide film 5 lands 6 wiring 7 Second polyimide film 8 First copper film 9 Coating resin film 10 solder balls 11 slits 21 Third Polyimide Film 22 Second copper film

Claims (8)

(57) [Claims] 1. A semiconductor chip, and a first insulating resin, a wiring, a second insulating resin, all of which are formed on the chip.
At least a bump for external connection and a first metal film,
The wiring is formed on the chip via a first insulating resin and connects the bonding pad of the chip to the bump, and the second insulating resin is formed on the upper layer of the wiring and covers the bump formation region. Except for covering the entire surface of the chip, the first metal film is formed on the second insulating resin, covers the entire surface of the chip except the bump portion, and is scattered over the entire surface of the chip. Van
Wherein a that have a different plurality of slits and the flop forming portion. 2. A semiconductor chip, and a first insulating resin, a wiring, a second insulating resin, all of which are formed on the chip.
An external connection bump, a first metal film, a third insulating resin, and a second metal film are provided at least, and the second metal film is formed on the chip via a third insulating resin. The entire surface of the chip except for the bonding pad portion is covered, and the wiring is firstly formed on the second metal film.
Connecting the bonding pad of the chip and the bump through the insulating resin film, and the second insulating resin is formed in the upper layer of the wiring and covers the entire surface of the chip except the bump forming region. Coated, the first
Is formed on the second insulating resin and covers the entire surface of the chip excluding the bump portion. Wherein the first metal film, the claims having a plurality of different slits the bump forming portions scattered over the entire surface of the chip
2. The semiconductor device according to 2 . 4. The semiconductor device according to claim 2, wherein the second metal film has a plurality of slits different from the bonding pad portions scattered over the entire surface of the chip. 5. The semiconductor device according to claim 1, wherein at least the wiring is formed of a wiring material whose main material is copper. 6. The semiconductor device according to claim 1, wherein the first metal film is formed of a wiring material containing copper as a main material. 7. The semiconductor device according to claim 1, wherein the bump is a solder ball. 8. The semiconductor device according to claim 1, wherein the bumps are arranged in a grid on the surface of the chip.