JP3395259B2 - Semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and its manufacturing method, and more particularly to a semiconductor device on an insulating amorphous material and its manufacturing method.

[0002]

2. Description of the Related Art Recently, large-sized, high-resolution liquid crystal display panels, high-speed, high-resolution contact-type image sensors, and three-dimensional ICs.
In order to meet such needs, there is a demand for a technique for forming a high-performance thin film transistor on an insulating amorphous substrate such as glass or quartz or an insulating amorphous material such as SiO 2.

As such a semiconductor device using amorphous silicon or polycrystalline silicon as a device material, good results have been obtained in terms of variations in characteristics of each device and yield. In particular, the one using polycrystalline silicon as the element material has a relatively high movement due to the technique of melting and recrystallization by laser light and the technique of solid-phase growing amorphous silicon to form a polycrystalline silicon film of large grain size. A device having a certain degree can be manufactured relatively easily. Therefore, L
It has become possible to be applied as a switching element or a driving element of a CD or an image sensor.

However, due to high definition and large capacity of liquid crystal panels, application to SRAM, etc., there is a demand for an element having not only an on-current but also a smaller off-leakage. In the case of an element using amorphous silicon or polycrystalline silicon as an element material, it is known that it is effective to provide an offset between the gate electrode and the drain region in order to reduce off-leakage. An element having a different structure is often used.

Looking at the application of thin film transistors to SRAMs, for example, the Institute of Electronics, Information and Communication Engineers Technical Report SDM-
Very often, a thin film transistor in which the gate electrode is located below the channel region as used in 91-18 is used. In the case of such an element, a non-self-aligned process of forming a source / drain region by forming a resist in a photolithography process different from the process of forming a gate electrode and using the resist as a mask is used. Has been.

[0006]

However, when the non-self-aligning process as described above is used, the influence of misalignment cannot be avoided. Usually, an alignment margin of about 0.15 to 0.2 μm is provided for the actually required offset amount in order to compensate for the influence of such misalignment and to secure the lower limit value of the required offset. Considering the effect of misalignment,
In the worst case, this doubled value can be added to the actually required offset. The size of the offset actually required is about 0.1 to 0.3 μm, and the decrease in the actual value of the on-current and the variation in the characteristics due to the offset added in the above-described manner become considerably large. .

Therefore, the present invention is to solve such a problem, and by providing a structure of a thin film transistor and a manufacturing method for reducing the influence of misalignment, the actual value of the on-current of the thin film transistor is improved and the characteristics thereof are improved. It suppresses the variation of.

[0008]

In order to solve the above problems, a semiconductor device according to the present invention comprises: (1) a substrate, a gate electrode provided above the substrate, and the same gate electrode an electrode disposed on a layer of, and arranged insulating film to cover the gate electrode and the electrode, wherein disposed above the insulating film, a semiconductor film having a channel region and the source region and the drain region and the offset And, wherein the offset is
Is disposed between the rain region, an end portion of the source region side of the drain region is disposed immediately above the electrode, the electrode, the drain region or the gate
It is connected to the gate electrode .

(2) The substrate, the gate electrode arranged above the substrate, and the same layer as the gate electrode.
Cover the electrodes and the gate electrode and the electrodes.
The insulating film that is disposed and the insulating film that is disposed above the insulating film.
Channel region, source region, drain region, offset
Anda semiconductor film having the offset, Cha
The drain region is arranged between the drain region and the drain region, and an end portion of the drain region on the source region side is formed of the electrode.
They are arranged on a straight, wherein the electrode, the supply voltage when the drain region has a conductivity of N-type, when the drain region has a P-type conductivity to the ground potential, is connected It is characterized by

[0010] (3), characterized in that the side walls to said electrode and said gate electrode is formed.

(4) The end of the source region on the drain region side is formed immediately above the gate electrode.

[0012]

[0013]

[0014]

[0015]

[0016]

FIG. 1 is a process sectional view showing an example of a method of manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 1A shows a state in which a gate electrode 102 of a thin film transistor, an induction electrode 103 and a gate insulating film 104 are formed on an insulating substrate 101.

The insulating substrate 101 has a normal pressure C on its surface.
A quartz glass substrate having an NSG layer formed by the VD method is used. Alternatively, the substrate may be formed on a silicon substrate having an insulating film formed on its surface or a silicon substrate having an MOS transistor formed thereon and having an interlayer insulating film formed thereon.

The polycrystalline silicon film forming the gate electrode 102 and the induction electrode 103 is an amorphous silicon film formed at a substrate temperature of 540 ° C. by low pressure CVD using silane (SiH 4) as a source gas, and then ion-implanted. Is formed by polycrystallizing by introducing N-type impurities by annealing at 800 ° C. for 20 minutes, and the film thickness is 100.
It is 0Å. By using such a step, a polycrystalline silicon film having a flat surface morphology can be obtained, which contributes to improvement of withstand voltage of the gate insulating film 104 formed thereover and improvement of on-current of the manufactured thin film transistor. is doing.

The gate insulating film 104 is formed at a substrate temperature of 7 by a low pressure CVD method using silane and nitrous oxide (N2O).
The film is formed at 80 ° C., and the film thickness is 200Å.

The gate electrode 102 and the induction electrode 103 are formed by patterning the above-mentioned polycrystalline silicon layer by a photolithography process.

The distance between the gate electrode 102 and the induction electrode 103 determines the size of the drain side offset 110 of the thin film transistor to be manufactured, and is about 0.4 μm. This value of 0.4 μm is not an optimum value for forming the semiconductor device of the present invention, but is a rate-determined value due to the limitation of the current processing using photolithography using i-line. It is preferable that the thickness is about 1 to 0.3 μm. For this reason, it is very useful to use a phase shift mask and a photolithography process using an excimer laser beam that can further reduce the processing size.

Further, since the offset 110 is an amount that can be controlled by the dimensional accuracy of photolithography and etching, it is possible to suppress the variation in the size of the effective offset to 0.1 μm or less.

FIG. 1 (b) shows a process of forming a source / drain region by ion implantation after forming a polycrystalline silicon layer to be a channel region on the gate insulating film. .

Polycrystalline silicon film 10 which becomes the channel region
8 is LPCV using disilane (Si2H6) as a source gas
After forming an amorphous silicon film by the D method at a substrate temperature of 480 ° C., it is annealed in an N 2 atmosphere at 600 ° C. for 8 hours + 650 ° C., 2 hours + 700 ° C., 1 hour to form a polycrystalline film. The film thickness is about 200Å. By performing such heat treatment, a polycrystalline silicon film having a large grain size of about 1 μm is obtained. Ion implantation for adjusting the threshold voltage Vth of the thin film transistor manufactured after this step may be performed.

The resist mask 107 is formed so as to overlap the induction electrode 103 by about 0.2 μm on the mask by an amount corresponding to the alignment margin 111. The size of this overlap is set depending on the accuracy of alignment control and the accuracy of resist dimension control. It is preferable to use a value of about 0.1 to 0.3 μm depending on the method of accuracy control. Appropriate.

After forming the resist mask, BF2 ions are changed to 2
A source / drain region is formed by implanting 8E14 at 5 keV.

FIG. 1C shows a completed state of the thin film transistor.

After performing ion implantation for forming the source / drain regions, 800 ° C. and 20 ° C. in an N 2 atmosphere.
Then, the impurities introduced into the source / drain regions are activated.

In the thin film transistor manufactured by the above-mentioned method, the end of the drain region formed by ion implantation is formed on the induction electrode 103 even if the influence of alignment variations is included. On the other hand, since the induction electrode 103 is connected so as to have the same potential as the drain electrode, carriers are also induced on the induction electrode 103 even in the channel polycrystalline silicon into which the impurity for forming the drain region is not introduced, and the alignment is performed. By providing the margin 111, the resistance of the offset portion added to the offset 110 is reduced. Therefore, even if the alignment is offset in the direction of increasing the offset, the decrease in the on-current is suppressed to a low level, and the minimum value of the on-current including the alignment variation is greatly improved.

Further, when the induction electrode 103 is connected to the gate electrode, when the thin film transistor is turned on, carriers are induced in the channel polycrystalline silicon on the induction electrode 103, which is the same reason as described above. Can suppress the decrease of the on-current.

Further, the thin film transistor having the structure shown in FIG. 1C has a smaller leak current when turned off than the thin film transistor formed by the conventional method having the same channel length and offset length. This is because, in the case of a junction formed by introducing impurities in polycrystalline silicon, the effect of widening the effective cross-sectional area of the junction due to the difference in impurity diffusion between crystal grains and crystal grain boundaries can be seen. In the case of the thin film transistor manufactured by the above method, the effective drain region end is formed not by the introduction of impurities but by the induced region, so that the effective drain end cross-sectional area contributing to the leak current at the time of OFF is reduced. It is thought to be to do.

FIG. 2 is a process sectional view showing another example of a method of manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 2A shows an insulating substrate 201 in which a SiO2 film is formed on the surface of a silicon substrate by a low pressure CVD method.
It shows a state in which an amorphous silicon layer 209 is newly formed after forming the patterns of the gate electrode 202 and the induction electrode 203 of the thin film transistor on the above.

The gate electrode 202 and the induction electrode 203 are formed at a substrate temperature of 500 ° C. by a low pressure CVD method using disilane as a raw material gas. PH 3 is added to the raw material gas to perform in situ doping. .
After forming a pattern by photolithography, a 1500 Å amorphous silicon film 209 is newly formed under the same film forming condition as that for forming the layer on which the gate electrode 202 is formed.

FIG. 2B shows a state in which the gate insulating film 204 is formed after forming the gate electrode 202 and the induction electrode 203.

From the state shown in FIG. 2A, first, an amorphous silicon film 209 is formed by chlorine-based anisotropic dry etching.
Is etched back to form the gate electrode 202 and the induction electrode 20.
A side wall is formed at 3. Next, annealing is performed at 800 ° C. for 20 minutes to polycrystallize the amorphous silicon film. Further, the gate insulating film 2 is formed at a substrate temperature of 780 ° C. by a low pressure CVD method using silane and nitrous oxide as source gases.
04 is formed in 200Å.

The pattern interval between the gate electrode 202 and the induction electrode 203 formed in FIG. 2A is 0.4 μm, and this value is determined by the limit of the pattern interval that can be formed by photolithography using the current i-line. ing. However, in order to improve the characteristics of the manufactured thin film transistor, it is desirable to reduce the distance between the gate electrode 202, the induction electrode, and the induction electrode 203 to about 0.1 to 0.3 μm, and by using the above steps, About 0.25 μm
Has been reduced to. Therefore, it is possible to manufacture a thin film transistor having a higher on-current than that of the embodiment shown in FIG.

In FIG. 2C, after forming an amorphous silicon film 208 to be a channel region on the gate insulating film, a resist mask 207 to be a implantation mask for forming source / drain regions is formed by ion implantation. It shows the state of being done.

Amorphous silicon film 20 serving as a channel region
No. 8 is a film formed at a substrate temperature of 480 ° C. by a low pressure CVD method using disilane as a source gas, and the film thickness is about 200Å.
After the amorphous silicon film 208 is formed, heat treatment at 400 ° C. or higher is not performed until the amorphous silicon film 208 is crystallized until ion implantation for source / drain formation is performed. Even when a protective film for ion implantation is used, the protective film is formed by a process capable of forming a film at 400 ° C. or lower, such as plasma CVD or LTO. If necessary after this step, ion implantation for adjusting the threshold voltage Vth of the manufactured thin film transistor may be performed.

The resist mask 207 is provided so as to overlap the induction electrode 203 by 0.1 μm on the mask. Actual alignment margin 2 of resist mask 207
11 is the above-mentioned amount of overlap + side wall and is about 0.2
μm. The size of the alignment margin depends on the accuracy of alignment control and the control of resist dimension control.
It is preferable that the thickness is about 0.1 to 0.3 μm.

After forming the resist mask, BF2 ions are changed to 2
The source / drain regions are formed by implanting 4E14 at 5 keV.

FIG. 2D shows a completed state of the thin film transistor.

After ion implantation for forming the source / drain regions, 600 ° C., 8 hours + 600 ° C., 2 hours + 700 ° C., 1 hour + 800 ° C. in N 2 atmosphere,
Annealing for 20 minutes is performed to activate the impurities introduced into the source / drain regions. By activating the impurities introduced by ion implantation with the channel region in an amorphous state in this manner, the size of the drain-side offset required to suppress the leak current when the thin film transistor is turned off is reduced. can do. The amount of offset on the drain side required when the channel region is made of polycrystalline silicon and impurities are simply activated at 800 ° C. is about 0.3 μm. When the annealing conditions are used, the required drain-side offset can be set to 0.1 μm or less.

As described above, the effect of performing the activation annealing in the amorphous state of the channel region is particularly high at 600 ° C. to 7 ° C.
After annealing at 00 ° C for about 1 to several tens of hours, 7
This is the case where annealing is performed at 00 ° C. or higher, but the present invention is not limited to such heat treatment, and the effect is recognized even when annealing is performed at a temperature of 700 ° C. or higher. For example, even when the activation annealing is simply performed at 800 ° C., the required drain-side offset is set to 0.
It can be reduced to about 15 to 0.2 μm.
Further, when the annealing is performed at 700 to 700 ° C. or more after the annealing is performed at 600 to 700 ° C. for about 1 to several tens of hours, a lower resistance value can be obtained at the same impurity dose amount. Therefore, it is possible to reduce the dose of ion implantation for forming the source / drain,
Also in this respect, there is an effect that the magnitude of the required drain side offset can be reduced.

As shown in this embodiment, when the offset 220 having a size of 0.3 μm or less is used, the offset on the drain side required for suppressing the off current is reduced. The combination of such techniques is useful for manufacturing a thin film transistor having good characteristics.

FIG. 3 is a pattern diagram of a cell and an equivalent circuit diagram showing an example in which the semiconductor device according to the embodiment of the present invention is used as a load in an SRAM cell.

FIG. 3A shows a pattern of a MOS transistor formed in the substrate. The upward-sloping hatched portion indicates the active region in the substrate and the upward-sloping diagonal portion indicates the MOS.
The pattern of polycide used as a gate of a transistor is shown. Reference numerals 301 and 302 denote memory cell driver transistors and 303 and 304 transfer transistors.

FIG. 3B shows the pattern of the load thin film transistor stacked on FIG. 3A. The upward-sloping hatched portion indicates the gate electrode layer pattern of the thin-film transistor and the upward-sloping diagonal portion. Shows the pattern of the polycrystalline silicon layer which becomes the channel of the thin film transistor, and the broken line shows the pattern of the resist mask when performing the ion implantation for forming the source / drain of the thin film transistor.

FIG. 3C shows an equivalent circuit of the memory cell shown in FIGS. 3A and 3B.
The elements of 01 to 306 are the same as those of FIG. 3 (a) and FIG. 3 (b).
01 to 306, 310 indicates a power supply line, and 311 indicates a ground line.

Reference numerals 305 and 306 denote load P-type thin film transistors to which the structure of the semiconductor device of the present invention is applied. 307 and 308 are shown in FIG.
3 shows an induction electrode corresponding to 103 or 203 in the embodiment shown in FIG. When the thin film transistor of the present invention is applied to the CMOS structure as in the present embodiment, the potential for connecting the induction electrodes 307 and 308 uses the potential on the drain side of the thin film transistor or the potential on the gate electrode as well as the ground potential. You can also In this embodiment, the induction electrode 3
Reference numerals 07 and 308 indicate the case where they are connected to the ground line.

When the induction electrodes 307 and 308 are connected to the ground line in this way, a channel is strongly induced on the induction electrode regardless of the state of the memory cell.
Therefore, the thin film transistors 305 and 306 are always in a state where a high on-current can be obtained, and high stability of data retention can be obtained.

FIG. 4 is a cell pattern diagram showing another example of the case where the semiconductor device according to the embodiment of the present invention is used as a load in an SRAM cell.

FIG. 4A shows a pattern of a MOS transistor formed in the substrate. The upward-sloping hatched portion indicates the active area in the substrate, and the upward-sloping diagonal portion indicates the MOS transistor.
The pattern of polycide used as a gate of a transistor is shown. Reference numerals 401 and 402 denote driver transistors of memory cells, and 403 and 404 transfer transistors.

FIG. 4B shows a pattern of a load thin film transistor stacked on FIG. 4A, in which a hatched portion rising to the left shows a pattern of a gate electrode layer of the thin film transistor and a hatched portion rising to the right. Shows the pattern of the polycrystalline silicon layer which becomes the channel of the thin film transistor, and the broken line shows the pattern of the resist mask when performing the ion implantation for forming the source / drain of the thin film transistor.

Reference numerals 405 and 406 denote P-type thin film transistors for load, to which the structure of the semiconductor device of the present invention is applied. 407 and 408 are shown in FIG.
In the present embodiment, the induction electrodes corresponding to 103 or 203 are shown. In this example, the induction electrodes 407 and 40 are shown.
Reference numeral 8 shows the case where the thin film is connected to the gate electrode of the transistor.

FIG. 5 is a pattern diagram of a cell showing another example in which the semiconductor device according to the embodiment of the present invention is used as a load in the cell of the SRAM.

FIG. 5A shows a pattern of a MOS transistor formed in the substrate. The upward-sloping shaded area represents the active region in the substrate, and the upward-sloping hatched area represents the MOS.
The pattern of polycide used as a gate of a transistor is shown. Reference numerals 501 and 502 denote driver transistors of memory cells, and 503 and 504 transfer transistors.

FIG. 5B shows a pattern of a load thin film transistor stacked on FIG. 5A. A hatched portion in the upper right direction indicates a pattern of the gate electrode layer of the thin film transistor, and a hatched portion in the upper left direction. Shows the pattern of the polycrystalline silicon layer which becomes the channel of the thin film transistor, and the broken line shows the pattern of the resist mask when performing the ion implantation for forming the source / drain of the thin film transistor.

Reference numerals 505 and 506 denote load P-type thin film transistors to which the structure of the semiconductor device of the present invention is applied. 507 and 508 are shown in FIG.
In the present embodiment, the induction electrodes corresponding to 103 or 203 are shown. In this example, the induction electrodes 407 and 40 are shown.
Reference numeral 8 shows the case where the thin film is connected to the drain of the transistor.

In this way, when the induction electrodes 507 and 508 are connected to the drain side potential of the thin film transistor, it is possible to simply form a pattern.

FIG. 6 is a pattern diagram of a cell showing another example of the case where the semiconductor device according to the embodiment of the present invention is used as a load for an SRAM cell and its equivalent circuit. The split word line type cell is shown. When applied to.

FIG. 6A shows a pattern of a MOS transistor formed in the substrate. The upward-sloping shaded area represents the active region in the substrate and the upward-sloping hatched area represents the MOS.
The pattern of polycide used as a gate of a transistor is shown. Reference numerals 601 and 602 denote driver transistors of memory cells, and 603 and 604 transfer transistors.

FIG. 6B shows a pattern of the load thin film transistor stacked on FIG. 6A, in which the upward-sloping hatched portion represents the gate electrode layer pattern of the thin-film transistor and the upward-sloping diagonal portion. Shows the pattern of the polycrystalline silicon layer which becomes the channel of the thin film transistor, and the broken line shows the pattern of the resist mask when performing the ion implantation for forming the source / drain of the thin film transistor.

FIG. 6C shows an equivalent circuit of the memory cell shown in FIGS. 6A and 6B, and 6 in FIG.
The elements of 01 to 606 are the same as those of 6 of FIG. 3 (a) and FIG. 3 (b).
01 to 606, 610 is a power supply line, and 611 is a ground line.

Reference numerals 605 and 606 are P-type thin film transistors for load, to which the structure of the semiconductor device of the present invention is applied. 607 and 608 are shown in FIG.
The induction electrode corresponding to 103 or 203 in the embodiment shown in FIG.
8 shows an example in which 8 is connected to the ground line 611.

In the above-described embodiment, the present invention has been described by using the P-type thin film transistor. However, when the ion implantation for forming the source / drain shown in FIG. 1 or FIG. Can also be applied to an N-type thin film transistor by using As. When an N-type thin film transistor is used for CMOS, the potential connecting the induction electrode 103 or 203 shown in FIG. 1 or 2 is
It is also possible to use the potential of the power supply line in addition to the potential of the drain side of the thin film transistor or the potential of the gate electrode.

[0068]

As described above, according to the present invention, it is possible to reduce the influence of misalignment in the offset forming process on the drain side, improve the actual value of the on-current of the thin film transistor, and suppress the characteristic variation. It has become possible. It also has the effect of reducing the leak current when the thin film transistor is turned off, and can be applied to a device having a higher degree of integration.

[Brief description of drawings]

FIG. 1 is a process sectional view showing an example of a manufacturing process of a semiconductor device in an example of the present invention.

FIG. 2 is a process sectional view showing another example of the manufacturing process of the semiconductor device according to the embodiment of the invention.

FIG. 3 is a diagram showing a semiconductor device according to an embodiment of the present invention as an SRAM.
FIG. 3 is a pattern diagram showing an example of the case where the cell is applied as a load to the cell and its equivalent circuit diagram.

FIG. 4 is a diagram illustrating a semiconductor device according to an embodiment of the present invention as an SRAM.
FIG. 7 is a pattern diagram showing another example of the case where the load is applied to the cell of FIG.

FIG. 5 illustrates a semiconductor device according to an embodiment of the present invention as an SRAM.
FIG. 7 is a pattern diagram showing another example of the case where the load is applied to the cell of FIG.

FIG. 6 is a diagram showing a semiconductor device according to an embodiment of the present invention as an SRAM.
FIG. 3 is a pattern diagram showing an example of the case where the cell is applied as a load to the cell and its equivalent circuit diagram.

[Explanation of symbols]

101, 201 ... Insulating substrates 102, 202 ... Gate electrodes 103, 203, 307, 308, 407, 408, 5
07, 508, 607, 608 ... Induction electrodes 104, 204 ... Gate insulating films 105, 205 ... Sources 106, 206 ... Drains 107, 207 ... Resists 108, 208, 209 ... Amorphous silicon films 110, 210 ... Drain side offsets 111, 211 ... Alignment margins 301, 302, 401, 402, 501, 502, 6
01, 602 ... Transfer transistors 303, 304, 403, 404, 504, 505, 6
04, 605 ... Driver transistors 305, 306, 405, 406, 505, 506, 6
05, 606 ... Thin film transistors 310, 610 ... Power supply lines 311, 611 ... Ground lines

Claims (4)

(57) [Claims] 1. A substrate, a gate electrode arranged above the substrate, an electrode arranged in the same layer as the gate electrode, and an insulating film arranged so as to cover the gate electrode and the electrode. When the disposed over the insulating film, a semiconductor film having a channel region and the source region and the drain region and the offset,
And the offset is between the channel region and the drain region.
Is disposed, the end portions of the source region side of the drain region is disposed immediately above the electrodes, said electrodes, said drain region and said gate electrode
A semiconductor device characterized by being connected . 2. A substrate, a gate electrode arranged above the substrate, an electrode arranged in the same layer as the gate electrode, and arranged so as to cover the gate electrode and the electrode.
The insulating film and the channel region and the source region are disposed above the insulating film.
A semiconductor film having a region, a drain region and an offset ;
And the offset is between the channel region and the drain region.
Are arranged in the end portion of the source region side of the drain region is located above the straight of the electrode, the electrode is the supply voltage when the drain region has a conductivity of N-type A semiconductor device, wherein the drain region is connected to a ground potential when the drain region has P-type conductivity. 3. A process according to claim 1 or 2, characterized in that the side walls to said electrode and said gate electrode is formed
The semiconductor device according to. 4. The semiconductor device according to claim 1, wherein an end of the source region on the drain region side is formed immediately above the gate electrode.