JP3395693B2 - Digital signal processor - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention converts an originally digital signal, such as a personal computer signal, into an analog signal, and converts the analog image signal into a digital signal again for digital signal processing. The present invention relates to a digital signal processing device.

[0002]

2. Description of the Related Art A video signal of a personal computer signal is a digital signal originally converted into an analog signal. Recently, in order to perform various kinds of signal processing on a video signal of a personal computer signal, it has become more frequent to convert the analog signal into a digital signal again. An image enlarging device is an example of a digital signal processing device that converts a personal computer signal into a digital signal and processes the digital signal. 2. Description of the Related Art A projector device is often equipped with an image enlarging device for enlarging an image of a personal computer signal when the personal computer signal is displayed and used for a presentation or the like.

FIG. 4 is a diagram for explaining resampling in which a personal computer signal which is a digital signal is converted into an analog signal, and the analog signal is converted into a digital signal again. In FIG. 4, (A) is originally a digital personal computer signal. The discrete value signal shown in FIG. 4A is converted into an analog signal shown in FIG. 4B by a D / A converter (not shown). By being converted into an analog signal as shown in FIG. 4 (B), it becomes an image that can be viewed on display means such as a cathode ray tube. The analog signal shown in FIG. 4B is output by an A / D converter (not shown).
It is converted into a digital signal shown in FIG. 4C, and signal processing such as enlargement is performed.

In the process of originally converting a personal computer signal, which is a digital signal, into an analog signal, the waveform of the analog signal is distorted due to the characteristics of the transmission path. When re-sampling the distorted analog signal, it is necessary to adjust the sampling point in order to transmit an accurate value. Figure 5
FIG. 6 is a diagram for explaining adjustment of sampling points in resampling. In FIG. 5, it is indicated by a solid line.
Is an unadjusted sampling point that deviates from the original sampling position. A circle indicated by a broken line is a sampling point to be sampled by the adjustment which is the original sampling position. As a result of distortion occurring in the waveform of the analog signal,
The position to be sampled is not the sampling point indicated by ◯ of the solid line, but the position indicated by ◯ of the broken line.

FIG. 6 is a block diagram showing an example of a conventional digital signal processing apparatus, which is for adjusting the sampling points shown in FIG. In FIG. 6, a video signal of a personal computer signal which is an analog signal is input to the A / D converter 1 and converted into a digital signal. The horizontal synchronizing signal of the video signal is input to the PLL circuit 2 and the PLL
The circuit 2 generates a clock synchronized with the horizontal synchronizing signal. This clock is input to the phase adjustment circuit 3. An adjustment signal is input to the phase adjustment circuit 3, the phase of the input clock is adjusted by this, and it is input to the A / D converter 1 as a sampling clock.

Since the A / D converter 1 converts the video signal into a digital signal by the phase adjusted sampling clock, the phase of the sampling point is adjusted as shown in FIG. This makes it possible to avoid sampling at the data change point (that is, between the original pixel and the pixel). If the phase of the sampling point is shifted, it will appear as severe noise on the screen and deterioration of signal characteristics. However, such a problem can be prevented in the digital signal processing device provided with the phase adjustment circuit 3. The digital signal output from the A / D converter 1 is input to the signal processing circuit 4 and subjected to various kinds of signal processing.

[0007]

In the conventional digital signal processing apparatus described above, when the PC signal is sampled by the A / D converter 1 at the same sampling rate as the original digital signal, No particular problem occurs. However, when the A / D converter 1 samples a personal computer signal at a sampling rate n (n is an integer of 2 or more) times the sampling rate of the original digital signal, a problem occurs.

FIG. 7 is a diagram for explaining a problem in the conventional digital signal processing device. FIG. 7 shows the operation in the case of sampling a personal computer signal at a sampling rate twice the sampling rate of the original digital signal. Sampling at a double sampling rate means that two identical sampling data are continuously output. Data a1, shown in FIG.
As indicated by a2 and data b1 and b2, as the expected value, two identical data are continuously output by the double sampling by the A / D converter 1. However, in FIG. 7B, data a1, a2 'and data b
One of the data a2 ', b, as shown as 1, b2'
2'may be different from the data a2, b2 which is the expected value which should be the position shown by the broken line.

This is because when a digital signal is converted into an analog signal, the signal theoretically deteriorates due to the aperture effect. In particular, in a pattern of only one data such as one line, the high frequency band is deteriorated, and the signal deterioration is remarkable. In sampling at n times the video signal,
Since the sampling points are at regular intervals, there is a high possibility that distortion will occur in any of the data multiplied by n. If distortion occurs in the data multiplied by n, it will appear as visual disturbance such as image disturbance and deterioration of frequency characteristics.

The present invention has been made in view of the above problems, and in a digital signal processing apparatus for converting a digital signal converted into an analog signal into a digital signal again for signal processing, the analog signal is converted into the original digital signal. It is an object of the present invention to provide a digital signal processing device capable of preventing visual interference when sampling is performed at a sampling rate n times higher than the sampling rate (n is an integer of 2 or more).

[0011]

In order to solve the above-mentioned problems of the prior art, the present invention provides a digital signal processing apparatus for converting a digital signal converted into an analog signal into a digital signal again and processing the signal. The analog signal is sampled at a sampling rate n (n is an integer of 2 or more) times the sampling rate of the original digital signal, and n consecutive sampling data are output for one sampling data of the original digital signal. A /
A D converter (1) and a selective replacement circuit (5) for selecting one of the n continuous sampling data and replacing the other n-1 sampling data with the selected sampling data. The present invention provides a digital signal processing device characterized by comprising:

[0012]

BEST MODE FOR CARRYING OUT THE INVENTION A digital signal processing apparatus of the present invention will be described below with reference to the accompanying drawings. 1 is a block diagram showing an embodiment of a digital signal processing device of the present invention, FIG. 2 is a block diagram showing an example of a specific configuration of the selection circuit 5 in FIG. 1, and FIG. 3 explains the operation of FIG. FIG. In FIG. 1, the same parts as those in FIG. 6 are designated by the same reference numerals.

In FIG. 1, a video signal of a personal computer signal which is an analog signal is input to an A / D converter 1 and converted into a digital signal. The horizontal synchronizing signal of the video signal is input to the PLL circuit 2, and the PLL circuit 2 generates a clock synchronized with the horizontal synchronizing signal. This clock is input to the phase adjustment circuit 3. An adjustment signal is input to the phase adjustment circuit 3, the phase of the input clock is adjusted by this, and it is input to the A / D converter 1 and the selection replacement circuit 5 as a sampling clock.

The A / D converter 1 converts a video signal into a digital signal by using a phase-adjusted sampling clock. The A / D converter 1 samples the personal computer signal at a sampling rate n (n is an integer of 2 or more) times the sampling rate of the original digital signal. Therefore, the rate of the sampling clock is n times that of the original digital signal. By adjusting the phase of the sampling clock, the phase of the sampling point is adjusted, and sampling at the data change point (that is, between the original pixel and the pixel) can be avoided. A /
The digital signal output from the D converter 1 is input to the selective replacement circuit 5 provided by the present invention. To the selective replacement circuit 5, as an example, a horizontal reference signal that is valid once in the horizontal period generated from the horizontal synchronizing signal is input.

The selective replacement circuit 5 is composed of the A / D converter 1
One of the n sampling data continuously input to one sampling data (1 pixel) of the original digital signal is selected, and each of the other n-1 sampling data is selected. It is replaced by one sampling data. The data output from the selective replacement circuit 5 is input to the signal processing circuit 4 and subjected to various kinds of signal processing.

Here, the specific configuration and operation of the selective replacement circuit 5 will be described with reference to FIGS. In addition,
2 and 3 show the configuration and operation in the case of sampling a personal computer signal at a sampling rate twice the sampling rate of the original digital signal. As shown in FIG. 2, the selective replacement circuit 5 includes flip-flops 51 to 53 and 56, an inverter 54, and a selector 55.

In FIG. 2, the flip-flop 51 receives the digital data shown in FIG. 3A output from the A / D converter 1. The A / D converter 1 is
A personal computer signal is sampled at a sampling rate twice the sampling rate of the original digital signal. Therefore, the input data D0, D1 and D2, D shown in FIG.
3 is sampling data (pixel) of the original digital signal
2 are continuously output and correspond to the data a1 and a2 and the data b1 and b2 shown in FIG.

FIG. 3B output from the phase adjusting circuit 3.
The sampling clock shown in FIG.
To 53 and 56. A horizontal reference signal which becomes high once in the horizontal period shown in FIG. 3F is input to the flip-flop 53.

The flip-flop 51 delays the input data by one clock and inputs it to the flip-flop 52. The flip-flop 52 outputs the input data to 1
Delay by the clock. When the output of the flip-flop 51 is the signal A and the output of the flip-flop 52 is the signal B, the signals A and B are the data shown in FIGS. 3C and 3D, respectively. The signals A and B have a weight of 8 bits as an example. Flip-flop 53
Output of the flip-flop 53 via the inverter 54.
3 is input to the flip-flop 53 as shown in FIG.
As shown in (E), a toggle operation selection signal that alternately repeats high and low is output.

Here, since the sampling is doubled, that is, the input data is doubled, the flip-flop which is the delay device is a flip-flop 51 which delays the input data by one sampling clock.
And two flip-flops 52 that delay the input data by two sampling clocks. For n-times sampling, n delay devices (flip-flops) that delay by 1 to n sampling clocks are provided. In this case, the selection signal is a signal for sequentially selecting the n delay devices in a toggle manner.

Signals A and B are input to the selector 55,
The selector 55 alternately selects the signals A and B by the selection signal from the flip-flop 53. If the signal A is selected when the selection signal is high and the signal B is selected when the selection signal is low, the data D1, D3, D5 ... Are extinguished, and the data D1, D3, D5. D2
It is replaced by D4 .... As a result, the signal C output from the selector 55 is the data D as shown in FIG.
0, D0, D2, D2, D4, D4 ... That is, this means that one of the two consecutively output data is selected with respect to the original sampling data, and the other one data is replaced with the selected data. The signal C is delayed by the flip-flop 56, and as shown in FIG.
The output data is shown in (H).

In the example of FIG. 7B, the data a1 is shown in FIG.
3A corresponds to the data D0 in FIG.
If it corresponds to the data D1 of (A), the data a2 '
Data a1 instead of data a2 ′ without using
Is used twice consecutively. Therefore, in the present invention, the two sampling data that form a pair are exactly the same data, so that one value does not deviate from the expected value as in the conventional case.

The data D can be set by setting the selection signal.
0, D2, D4 ... Are replaced with data D1, D3, D5 ... And the signal C is replaced with data D1, D1, D3, D3, D5.
It may be D5 ... In the example of FIG. 7B, the data a2 ′ may be used twice consecutively instead of the data a1. The conventional problem occurs because the values of two data, which should originally be the same, are different from each other. Therefore, one of the two consecutively output data is selected and the other data is selected. Is replaced with the selected data, the conventional problems can be solved well.
Therefore, any of the n pieces of data that are continuously output may be selected.

[0024]

As described in detail above, the digital signal processing apparatus of the present invention samples an analog signal at a sampling rate n (n is an integer of 2 or more) times the sampling rate of the original digital signal. , An A / D converter that outputs n consecutive sampling data for one sampling data of the original digital signal, and one of the n consecutive sampling data is selected, and other n -Since it is configured to include a selective replacement circuit that replaces one sampling data with the selected sampling data, it is extremely simple configuration and very effectively prevents visual disturbance such as image distortion and frequency characteristic deterioration. can do.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram showing an example of a specific configuration of a selection circuit 5 in FIG.

FIG. 3 is a timing diagram illustrating the operation of FIG.

FIG. 4 is a diagram for explaining resampling for converting a digital signal converted into an analog signal into a digital signal again.

FIG. 5 is a diagram for explaining adjustment of sampling points in resampling.

FIG. 6 is a block diagram showing a conventional example.

FIG. 7 is a diagram for explaining a problem in the conventional example.

[Explanation of symbols]

1 A / D converter 2 PLL circuit 3 Phase adjustment circuit 4 Signal processing circuit 5 Selective replacement circuit

─────────────────────────────────────────────────── --- Continuation of the front page (56) Reference JP-A-10-294666 (JP, A) JP-A-8-65165 (JP, A) JP-A-63-141471 (JP, A) JP-A-10- 63826 (JP, A) JP 8-179751 (JP, A) JP 7-177347 (JP, A) JP 5-14691 (JP, A) JP 8-111774 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H03M 1/00-1/88 G06T 3/40 H04N 1/393

Claims (2)

(57) [Claims] 1. A digital signal processing device for converting a digital signal converted into an analog signal into a digital signal again for signal processing, wherein the analog signal is a sampling rate n of the original digital signal (n is an integer of 2 or more). ) Sampling at a double sampling rate and outputting n consecutive sampling data for 1 sampling data of the original digital signal, and 1 of the n consecutive sampling data While selecting one, the other n-1 sampling data are
A digital signal processing device comprising a selective replacement circuit that replaces the selected sampling data. 2. The selective replacement circuit delays the sampling data output from the A / D converter by 1 to n sampling clocks, respectively.
2. The digital signal processing device according to claim 1, further comprising: a plurality of delay devices and a selector that sequentially selects the outputs of the n delay devices in a toggle manner.