JP3396039B2 - Solid-state imaging device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an XY address type solid-state image pickup device capable of bidirectional image pickup and scanning which can perform a normal image pickup operation and a mirror image pickup operation.

[0002]

2. Description of the Related Art As a demand for a solid-state image pickup device, in addition to a demand for miniaturization and high image quality, multi-functionalization can be mentioned. One of them is a mirror image function (horizontal reversal function) used for rearward confirmation when the solid-state imaging device is mounted on a vehicle. As a method for realizing this mirror image function, for example, a CCD image sensor is disclosed in Proceedings 2-7 (p31-32) of the 1991 National Conference of the Television Society.
FIG. 18 shows the configuration of a CCD image sensor having this mirror image function.

In FIG. 18, H1, H1B, H2, H2
B is the clock of the horizontal transfer CCD, a is the horizontal transfer CC
D and b are vertical transfer CCDs, and c is a pixel. In the CCD image sensor thus configured, in the normal image pickup operation, the flow of charges in the horizontal transfer CCDa is in the direction of the solid line in the figure, and in the mirror image pickup operation, the flow of charges is in the direction of the broken line. Considering the case where this configuration is applied to an XY address type image sensor, it is necessary to prepare horizontal scanning circuits for the forward direction and the backward direction respectively.

As another method of providing a bidirectional imaging scanning function, as disclosed in JP-A-1-302972, an up-down counter and a multiplexer are combined and the result of up-down counter counting is used in advance. A method is known in which a predetermined pulse signal is supplied from a multiplexer and the scanning direction is switched depending on whether the counter is up-counting or down-counting.

[0005]

However, if the conventional method is used to realize the bidirectional imaging scanning for the XY address type solid-state imaging device, the following problems occur. That is, first, when the configuration shown in FIG. 18 is applied to the XY address type solid-state imaging device, the forward and backward scanning circuits are required. Therefore, there is a problem that the chip area increases. On the other hand, JP-A-1-30
The method disclosed in Japanese Patent No. 2972 requires a complicated circuit configuration in order to configure the up / down counter and the multiplexer, and thus has a problem that the chip area also increases.

The present invention has been made in order to solve the above-mentioned problems in the conventional image sensor capable of bidirectional image pickup scanning, and is an XY capable of bidirectional image pickup scanning with a simple structure.
An object is to provide an address type solid-state imaging device.

[0007]

In order to solve the above-mentioned problems, the solid-state image pickup device according to the present invention has a light receiving section in which photoelectric conversion elements are two-dimensionally arranged as shown in the conceptual diagram of FIG. 1 and a horizontal scanning circuit 2 for sequentially reading the light accumulation signals of the photoelectric conversion elements of the light receiving unit 1 by the XY address system.
The horizontal scanning circuit 2 includes a vertical scanning circuit 3 and a signal reading unit 4, and the horizontal scanning circuit 2 controls a scanning direction by a clock control, and a horizontal shift register 5 for controlling an input clock to the horizontal shift register 5. The vertical scanning circuit 3 further includes a scanning direction control circuit 6, and the vertical scanning circuit 3 includes a vertical shift register 7 whose scanning direction is switched by clock control, and a vertical scanning direction control circuit 8 which controls an input clock to the vertical shift register 7. The scanning direction control circuits 6 and 8 for horizontal and / or vertical are controlled to switch the scanning direction.

In the solid-state image pickup device constructed as described above, the horizontal and / or vertical scanning direction control circuits 6 and 8 control the clocks input to the horizontal shift register 5 and / or the vertical shift register 7, respectively. Alternatively, the vertical scanning direction is switched. Therefore, it is possible to realize a solid-state imaging device capable of bidirectional imaging scanning, which does not require a complicated circuit configuration or a plurality of scanning circuits and can be applied to mirror image imaging, upside-down imaging, and the like with a reduced increase rate of a chip area.

[0009]

EXAMPLES Next, examples will be described. FIG. 2 is a circuit configuration diagram showing a clock type inverter constituting a shift register used in a scanning circuit, which is a main part of a first embodiment of an XY address type solid-state image pickup device capable of bidirectional image pickup scanning according to the present invention. Is. In the figure, PM1 to PM3 are P
The channel MOS transistors NM1 to NM3 are N
It is a channel MOS transistor. As shown in the figure, two sets of gates to which a clock is applied are provided in parallel with PM2, NM2 and PM3, NM3, and different clock signals VCKP, XVCKP, VCK are provided to the respective gates.
N, XVCKN are provided. The clock signals XVCKP and XVCKN represent inverted signals of the clock signals VCKP and VCKN, respectively. The clock signal V is output to the output VOUTP.
When CKP is at "L" level, an inverted signal of the input VIN appears, and when clock signal VCKP is at "H" level, the previous state is maintained. Similarly, when the clock signal VCKN is at "L" level, an inverted signal of the input VIN appears at the output VOUTN, and when the clock signal VCKN is at "H" level, the previous state is held.

FIG. 3 is a circuit configuration diagram showing a shift register having an N-stage configuration in which the clock type inverters shown in FIG. 2 are connected in cascade. In FIG. 3, 101 to 108 are clock lines of the shift register, 109 is a start pulse input terminal of the shift register, SR (1), SR (2), ...
SR (N) is the output terminal of the shift register, SR (0.
5), SR (1.5), ... SR (N + 0.5) are intermediate nodes of the shift register. 4 and 5 show pulse timings for explaining the operation of the shift register shown in FIG. 3. FIG. 4 shows the case of forward scanning and FIG. 5 shows the case of backward scanning.

First, the forward scanning will be described. Clock lines VCKN1, VCKN2, and VCKP as shown in FIG. 4 are supplied to the clock lines 101 to 104 in FIG.
1, VCKP2 are applied, and clock lines 105 to 108
Has clock pulses VCKN1, VCKN2, VCK
An inverted signal of P1 and VCKP2 is given. The clock pulses VCKN1 and VCKN2 are always at "H" level, the clock pulses XVCKN1 and XVCKN2 are always at "L" level, and the gate connected to the clock line to which these signals are applied is always in the off state.

Regarding the operation of the shift register at this time,
A description will be given based on the timing chart of FIG. When the start pulse VST at the “H” level is input to the input terminal 109 of the shift register for the period of t ₁ to t ₄ , first, the clock pulse VCKP2 is applied to the intermediate node SR (0.5).
, The inversion signal of the start pulse VST appears, so that the inversion signal of the start pulse VST shifts in synchronization with the fall of the clock pulse VCKP2, and becomes the “L” level during the period of t ₂ to t _5. Become. Next, the clock pulse VCKP1 is "L" at the output terminal SR (1).
At the time of the level, the inverted signal of the intermediate node SR (0.5) appears, so that the start pulse VST shifts in synchronization with the falling of the clock pulse VCKP1 and becomes the “H” level during the period of t ₃ to t ₆ . Similarly, the shift operation is performed thereafter, and the shift register output terminals SR (1), SR (2),
.. The signals as shown in FIG. 4 sequentially appear in SR (N).

Next, the reverse scanning will be described. The clock lines 101 to 104 have clock pulses VCKN1, VCKN2, VCKP1 and VCKP2 as shown in FIG.
Is given. At this time, the clock pulse VCKP1,
VCCP2 is always "H" level, clock pulse XVC
KP1 and XVCKP2 are always at "L" level, and the gates connected to the clock lines to which these signals are applied are always off. The operation of the shift register at this time will be described based on the timing chart of FIG. When the shift register input terminal 109 receives the start pulse VST that is at the “H” level during the period from t ₁ to t ₄ , first, the intermediate node SR (N + 0.5) becomes the intermediate node SR (0 similar to .5), and t ₂ period ~t ₅ "L" level. Next, the output terminal SR (N) is t
₃ ~t becomes ₆ period "H" level, similarly shift operation is performed following a shift register output terminal SR (N), S
Signals as shown in FIG. 5 sequentially appear in R (N-1), ... SR (1).

As described above, in the shift register shown in FIG. 3, the scanning direction is switched by controlling the signal applied to the clock line of the shift register, and the shift register has only one start signal input terminal. Good. By using this shift register in the scanning circuit, a solid-state image pickup device capable of bidirectional image pickup and scanning can be obtained, and horizontal mirror image pickup and vertical image pickup can be performed.

Next, a second embodiment will be described. Figure 6
Is a second of the XY address type solid-state imaging device according to the present invention.
A circuit configuration of one stage of the shift register of the scanning circuit in the embodiment is shown, and operation timing charts thereof are shown in FIGS. FIG. 9 shows the configuration of a shift register in which the configuration shown in FIG. 6 is connected in N stages, and FIGS. 10 and 11 are timing charts for explaining the operation of the shift register shown in FIG. 7 and 10 show the timing in the forward scanning, and FIGS. 8 and 11 show the timing in the backward scanning.

First, the structure of one shift register will be described with reference to FIG. p-channel transistor
The source of 209 is the power supply line “V _DD ” 201, the drain is the source of the p-channel transistor 210, and the gate is n.
It is connected to the gate of the channel transistor 212. The gate of the p-channel transistor 210 is connected to the clock line "VCK1" 203, and the drain thereof is connected to the drain of the n-channel transistor 211. The gate of the n-channel transistor 211 is a clock line "XV".
CK1 ″ 206, the source is n-channel transistor 21
Connected to the drain of 2. The drain of the n-channel transistor 212 is connected to the ground line "VSS" 202.

P-channel transistors 213, 214 and n
The connection configuration with the channel transistors 216 and 218 is the same as the connection configuration with the p-channel transistors 209 and 210 and the n-channel transistors 211 and 212 described above. However, the gate of the p-channel transistor 214 is connected to the clock line “VCKP” 204, and the gate of the n-channel transistor 216 is connected to the clock line “XV”.
It is different in that it is connected to CKP ″ 207. Further, the source of the p-channel transistor 215 is the drain of the p-channel transistor 213 and the p-channel transistor 213.
It is connected to the source of 214, the drain is connected to the drain of the n-channel transistor 217, and the gate is connected to the clock line "VCKN" 205. Further, the source of the n-channel transistor 217 is the source of the n-channel transistor 216 and the n-channel transistor 218.
Of the clock line "XV"
It is connected to CKN "208.

The gate of the p-channel transistor 209 and the gate of the n-channel transistor 212 are connected to each other, and the input terminal 200 of the shift register (one stage) is connected.
And the drain of the p-channel transistor 210,
The drain of the n-channel transistor 211, the gate of the p-channel transistor 213, and the gate of the n-channel transistor 218 are connected to each other and serve as the output terminal SR of the shift register (one stage). Further, a connection point “VOUTP” 219 between the drain of the p-channel transistor 214 and the drain of the n-channel transistor 216
Is connected to the input terminal of the shift register of the next stage in the forward scanning, and the connection point "VOUTN" 220 between the drain of the p-channel transistor 215 and the drain of the n-channel transistor 217 is the next-stage shift in the backward scanning. It is designed to be connected to the input terminal of the register.

Next, the operation of one stage of the shift register shown in FIG. 6 will be described. First, when the start pulse "VST" shown in FIGS. 7 and 8 is input to the input terminal 200, the pulse appearing at the output terminal SR has the waveforms shown in FIGS. Then, at the time of forward scanning, the connection point "VOUTP"
The signal of 219 is the connection point "VOUTN" at the time of reverse scanning.
Since the signals of 220 respectively become the input signals of the next stage, the output of the shift register of the next stage becomes the pulse "SR '" shown in FIGS.

FIG. 9 is a circuit configuration diagram of a shift register in which the configuration shown in FIG. 6 is connected in N stages. In the shift register shown in FIG. 9, one having two input terminals for forward scanning and backward scanning is shown.
It is also possible to connect the input terminals in common to form one as in the embodiment.

Next, the operation of the shift register shown in FIG. 9 will be described. First, the case of forward scanning will be described with reference to the timing chart shown in FIG. In FIG. 9, an input terminal "VSTP" 200, a clock line "VC"
K1 "203," VCKP "204," VCKN "205, and clock lines" XVCK1 "206," XVCKP "
Timing pulses shown in FIG. 10 are given to 207 and "XVCKN" 208. Here, clock pulse "XVCK1"
Is an inverted signal of the clock pulse "VCK1", and the pulses "XVCKP" and "XVCKN" are inverted signals of the clock pulses "VCKP" and "VCKN", respectively.

Since the clock pulse "VCKN" and the clock pulse "XVCKN" are always at "H" level and "L" level, respectively, the p-channel transistor
215-1, 215-2, ... 215- (N-1), 215-N and n-channel transistors 217-1, 217-2, ... 217- (N-1), 21
7-N is always off. Input terminal "VSTP" 20
0, given a start pulse "VSTP" is the period "L" level of t ₁ ~t ₄ shown in FIG. 10, p-channel transistors 209-1 and n channel transistor 212-1
And the p-channel transistor 210-1 which operates at the timing of the clock pulse "VCK1" and the n-channel transistor 211-1 which operates at the timing of the clock pulse "XVCK1", the output terminal SR (1) is
At time t ₂ , the p-channel transistor 210-1 is turned on and the “H” level is output, and at time t ₅ , the n-channel transistor 211-1 is turned on and the “L” level is output. That is, the start pulse "VST" is applied to the output terminal SR (1).
The inverted signal of P ″ is (t ₂ −t ₁ ) {= (t ₅ −
A pulse that shifts by (t ₄ )} and becomes “H” level during the period of t ₂ to t ₅ appears.

A p-channel transistor 213-1 and an n-channel transistor 218-1 which operate by the pulse appearing at the output terminal SR (1), and a clock pulse "VCKP".
P-channel transistor that operates at the timing of
1, by the n-channel transistor 216-1 which operates at the timing of the clock pulses "XVCKP", n-channel transistors 216-1 is turned ON at time t ₃ to the node SR (1p), "L" level is output , The p-channel transistor 214-1 is turned on at time t ₆ ,
The "H" level is output. That is, the node SR (1
In p), the inversion signal of the pulse appearing at the output terminal SR (1) is shifted by (t ₃ −t ₂ ) {= (t ₆ −t ₅ )}, and the period “L” during the period from t _{3 to} t _6. A pulse that becomes "level" appears. Similarly, the shift operation is performed and the output terminal SR
(1), SR (2), SR (3), ... SR (N-
2), SR (N-1) and SR (N) are sequentially output with pulses. During forward scanning, the node SR (1n),
SR (2n), SR (3n), ... SR (N-2n),
SR (N-1n) and SR (Nn) are in a floating state.

Next, the case of reverse scanning will be described with reference to FIG. In the shift register shown in FIG. 9, the input terminal "VSTN" 221, the clock line "V"
CK1 ”203,“ VCKP ”204,“ VCKN ”205,
And clock lines "XVCK1" 206, "XVCK"
Pulses are given to P "207 and" XVCKN "208 at the timings shown in Fig. 11. Since the clock pulses" VCKP "and" XVCKP "are always at" H "level and" L "level, respectively, the p-channel transistor 21
4-N, 214- (N-1), ... 214-2, 214-1 and n-channel transistors 216-N, 216- (N-1), ... 216-2, 216-1
Is always off.

The input terminal "VSTN" 221 has t shown in FIG.
₁ ~t is the _fourth period "L" level start pulse "V
If STN "is given, p-channel transistor 209-N
And the n-channel transistor 212-N, the p-channel transistor 210-N operating at the timing of the clock pulse “VCK1”, and the n-channel transistor 211-N operating at the timing of the clock pulse “XVCK1”. At N), the p-channel transistor 210-N is turned on at time t ₂ to output “H” level, and the n-channel transistor 211-N is turned on at time t _5.
Then, the "L" level is output. That is, the output terminal SR
In (N), the inverted signal of the start pulse “VSTN” is shifted by (t ₂ −t ₁ ) {= (t ₅ −t ₄ )} and becomes “H” level during the period of t ₂ to t _5. The pulse appears. A p-channel transistor 213-N and an n-channel transistor 218-N which operate by the pulse appearing at the output terminal SR (N), and a p-channel transistor 215-N which operates at the timing of the clock pulse "VCKN".
And the n-channel transistor 217-N which operates at the timing of the clock pulse “XVCKN”, the n-channel transistor 217-N is turned on at the time t ₃ and the “L” level is output to the node SR (Nn). , The p-channel transistor 215-N is turned on at time t ₆ ,
The "H" level is output. That is, the node SR (N
In n), the inversion signal of the pulse appearing at the output terminal SR (N) is shifted by (t ₃ −t ₂ ) {= (t ₆ −t ₅ )}, and the period “L” during the period from t _{3 to} t _6. A pulse that becomes "level" appears. Similarly, the shift operation is performed and the output terminal SR
(N), SR (N-1), SR (N-2), ... SR
Pulses are sequentially output to (3), SR (2), and SR (1). Note that during reverse scanning, the nodes SR (Np), S
R (N-1p), SR (N-2p), ... SR (3
p), SR (2p) and SR (1p) are in a floating state.

In this embodiment, as compared with the case of the first embodiment, the number of transistors constituting one stage of the shift register can be reduced by 2 and the number of clock lines can be reduced by 2, so that the configuration is simple. Further, the size of the element can be reduced.

Next, a third embodiment will be described. Figure 12
13 is a circuit configuration diagram of a shift register used in the scanning circuit in the third embodiment, and FIGS. 13 and 14 are pulse timing diagrams for explaining the operation of the shift register shown in FIG. In FIG. 12, 301, 302, 303, 304 are shift register clock lines, 305 is a shift register start pulse input terminal, SR (1), SR (2), ...
・ SR (N) is the output terminal of the shift register, SR (0.
5), SR (1.5), ... SR (N + 0.5) are intermediate nodes of the shift register. Also, P (0.5), ... P
(N + 1.5) is a p-channel transistor,
(0.5), ... N (N + 1.5), TP (0.5), ... T
P (N + 0.5), TN (1.5), ... TN (N + 1.5)
Is an n-channel transistor, P (0.5) and N
(0.5), ... P (N + 1.5) and N (N + 1.5) constitute an inverter, and TP (0.5), ... TP (N + 0.5.
5), TN (1.5), ... TN (N + 1.5) form a transfer gate. Then, as shown in the figure, one inverter and two transfer gates are connected in cascade to form an N-stage shift register.

Next, the operation of the shift register thus constructed will be described. First, the forward scan will be described with reference to FIG. Clock lines 301-304
Are clock pulses VCKP1 and VCKP shown in FIG.
2, VCKN1 and VCKN2 are provided. Since the clock pulses VCKN1 and VCKN2 are always at "L" level, the transfer gates TN (1.5), ...
TN (N + 1.5) is always off. In this state, the shift register input terminal 305 receives t ₁ to t ₃
When the start pulse VST at the “H” level is input for the period of, the start pulse VST is first input to the node SR (0.5) when the clock pulse VCKP2 is at the “H” level.
Since the inverted signal of P appears, the clock pulse VCKP2
The inverted signal of the start pulse VST shifts in synchronization with the rising edge of the signal, and becomes the “L” level during the period of t ₂ to t ₅ .
Next, the output terminal SR (1) receives the clock pulse VCKP1.
There "H" node SR (0.5) when the level for inverted signal appears in shifts the start pulse VST in synchronization with the rising edge of the clock pulse VCKP1, a t ₄ period ~t ₆ "H" level . Similarly, the shift operation is performed thereafter, and the output terminals SR (1), ... SR of the shift register
At (N), output signals as shown in the figure sequentially appear.

Next, reverse scanning will be described with reference to FIG. The clock lines 301 to 304 have clock pulses VCKP1, VCKP2 and VCK as shown in FIG.
N1 and VCKN2 are provided. In this reverse scan,
Since the clock pulses VCKP1 and VCKP2 are always at the “L” level, the transfer gate TP (0.
5), ... TP (N + 0.5) is always off. In this state, the shift register input terminal 305 receives t ₁ ~
When the start pulse VST which is at the “H” level during the period of t ₃ , is input, first, the node SR (N + 0.5) is changed from t ₂ to t ₅ like the node SR (0.5) in the forward operation. It becomes the “L” level for the period. Next, the output terminal SR (N) is t ₄
~t becomes ₆ period "H" level, and so shift operation is performed, the output terminal SR (N), the · · · SR (1), appearing the output signal as a sequential shown.

As described above, according to the shift register having the structure shown in FIG. 12, the scanning direction is switched by controlling the clock pulse signal applied to the clock line of the shift register, and the shift register is scanned. A solid-state imaging device capable of bidirectional imaging and scanning can be realized by using it in a circuit.

In the shift register having the structure shown in FIG. 12, the CMOS inverter is used as the inverter, but the same structure can be used as long as it has the same function such as an E / D type inverter. You can
Further, in the shift register having the configuration shown in FIG. 12, an n-channel transistor is used as the transfer gate, but it goes without saying that a CMOS type, a p-channel transistor or the like having the same function can be used. .

Further, also in the configuration of the shift register in which the inverter and the transfer gate are combined,
Similar to the second embodiment, it is possible to reduce the number of transistors and the number of clock lines by thinning out two transfer gates provided in parallel for each half stage.

Next, a fourth embodiment will be described. FIG. 15 is a circuit configuration diagram showing a part of the scanning circuit of the fourth embodiment.
A part of the scanning circuit of this embodiment is configured by adding a scanning direction control unit 10 for controlling a clock signal applied to the shift register to the shift register of the first embodiment shown in FIG. The shift register portion shown in FIG. 15 has the same configuration and operation as those described in the first embodiment.
Here, the description will be omitted, and only switching of the scanning direction will be described. In FIG. 15, a scanning direction control unit 10 is externally provided with a signal CONT for controlling the scanning direction and basic locks VCK1 and VCK2 for driving a shift register, and bidirectional scanning is performed according to the scanning direction control signal CONT. Clock signal VC required for operation shift register
KP1, VCKP2, VCKN1, VCKN2, XVC
KP1, XVCKP2, XVCKN1 and XVCKN2 are output.

FIG. 16 is a diagram showing a specific circuit configuration example of the scanning direction control unit 10, and FIG. 17 is a pulse timing diagram for explaining its operation. In the scanning direction control unit 10 shown in FIG. 16, when the scanning direction control signal CONT is at "H" level, the forward scanning is performed, and when the scanning direction control signal CONT is at "L" level, the backward scanning is performed. When the scanning direction control signal CONT is at the "H" level, the NORs 11-1 and 11-2 have the same function as the inverter, while the outputs of the NORs 11-3 and 11-4 are always at the "L" level. On the other hand, the control signal CONT
Is at "L" level, the output of NOR 11-1 and 11-2 is "L"
Since the outputs of the NOR 11-3 and 11-4 have the same function as that of the inverter, the clock signals VCKP1, ...
XVCKN2 is as shown in FIG. 17, respectively. Figure 17
4 is compared with the timing of FIG. 4 and FIG. 5 described in the first embodiment, it can be seen that the forward scanning is performed when the control signal CONT is “H” level and the backward scanning is performed when the control signal CONT is “L” level.

As described above, by forming the scanning circuit by adding the scanning direction control unit 10, it is possible to reduce the number of external signals and easily switch the scanning direction. In this embodiment, the control signal CONT is set to perform the forward scanning at the "H" level and the backward scanning at the "L" level, but it is also possible to reverse the scanning. Further, it goes without saying that the scanning direction control circuit is not limited to the configuration shown in FIG. 16 and may be any configuration capable of controlling a desired clock. Further, it is obvious that this scanning direction control circuit can be applied to other embodiments.

[0036]

As described above on the basis of the embodiments,
According to the present invention, the horizontal and / or vertical scanning circuit is configured so that the scanning direction can be switched by the control of the input clock signal. Therefore, the bidirectional imaging and the solid-state imaging capable of performing the bidirectional imaging can be performed. The device can be realized with a simple structure without requiring a complicated circuit or a plurality of scanning circuits, and with a reduced rate of increase in chip area.

[Brief description of drawings]

FIG. 1 is a conceptual diagram for explaining a solid-state imaging device according to the present invention.

FIG. 2 is a circuit configuration diagram of a clocked inverter forming the shift register of the first embodiment of the present invention.

FIG. 3 is a circuit configuration diagram of a shift register formed by connecting the clocked inverters shown in FIG. 2 in cascade.

FIG. 4 is a timing chart for explaining a forward scanning operation of the shift register shown in FIG.

5 is a timing chart for explaining a backward scanning operation of the shift register shown in FIG.

FIG. 6 is a circuit configuration diagram of one stage of a shift register according to a second embodiment of the present invention.

FIG. 7 is a forward run for one stage of the shift register shown in FIG.
7 is a timing chart for explaining the check operation.

FIG. 8 is a backward run for one shift register shown in FIG.
7 is a timing chart for explaining the check operation.

9 is a circuit configuration diagram of a shift register in which N stages of the configuration for one stage shown in FIG. 6 are connected.

10 is a timing chart for explaining a forward scanning operation of the shift register shown in FIG.

11 is a timing chart for explaining a backward scanning operation of the shift register shown in FIG.

FIG. 12 is a circuit configuration diagram showing a shift register according to a third embodiment of the present invention.

13 is a timing chart for explaining a forward scanning operation of the shift register shown in FIG.

14 is a timing chart for explaining a backward scanning operation of the shift register shown in FIG.

FIG. 15 is a circuit configuration diagram showing a part of a scanning circuit according to a fourth embodiment of the present invention.

16 is a circuit configuration diagram showing a configuration example of a scanning direction control unit in FIG.

17 is a timing chart for explaining the operation of the scanning direction control unit shown in FIG.

FIG. 18 is a diagram illustrating a configuration example of a conventional image sensor having a mirror image function.

[Explanation of symbols]

1 Light receiving part 2 Horizontal scanning circuit 3 Vertical scanning circuit 4 Signal readout section 5 Horizontal shift register 6 Horizontal scanning direction control circuit 7 Vertical shift register 8 Vertical scanning direction control circuit 10 Scanning direction controller

─────────────────────────────────────────────────── ─── Continuation of front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H04N 5/335

Claims (3)

(57) [Claims] 1. A light receiving section in which photoelectric conversion elements are two-dimensionally arrayed, and a light accumulation signal of the photoelectric conversion elements in the light receiving section are sequentially transferred to XY.
In a solid-state image pickup device having horizontal and vertical scanning circuits for reading out by an address method and a signal reading unit and capable of bidirectional image pickup scanning, it serves to drive the horizontal and / or vertical scanning circuits and control the scanning direction. Horizontal and / or vertical scanning direction to output desired input clock signal respectively
A control circuit , a control gate is provided in the shift register of the horizontal and / or vertical scanning circuit, and the control gate is
A solid-state imaging device characterized in that bidirectional imaging scanning is enabled by making the scanning circuit scan and switching the scanning direction by making conductive or non-conductive corresponding to a scanning direction by a desired input clock signal. 2. The shift register is a clock type CM
Two sets of gates provided with a clock signal of the clock-type CMOS inverter are provided in parallel, and the gates are used as the control gates.
The solid-state imaging device according to claim 1, wherein the that. 3. The shift register comprises a combination of an inverter and a transfer gate, two transfer gates are provided in parallel, and
The solid-state imaging device according to claim 1, characterized in that the Geto and the control gate.