JP3396147B2 - Apparatus and method for measuring access time of semiconductor integrated circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an access time measuring apparatus and method for a semiconductor integrated circuit such as a semiconductor memory.

[0002]

2. Description of the Related Art Conventionally, in an access time measuring apparatus 1 having an electrical configuration as shown in FIG. 7, a semiconductor integrated circuit to be measured (hereinafter referred to as Device Under Test) such as a semiconductor memory is used.
(Hereinafter referred to as “DUT”) is measured. From the timing generation circuit 3 abbreviated as TG, the pattern generation circuit 4 abbreviated as PG and WF is the measurement timing signal for determining the measurement cycle time.
And a waveform format circuit 5, and a determination timing signal for determining the determination timing of the output signal is applied to an output determination circuit 6 abbreviated as CP. The pattern generation circuit 4 generates a test pattern, and the waveform format circuit 5 determines the waveform mode of the test signal given to the DUT 2. The test signal determined by the pattern generation circuit 4 and the waveform format circuit 5 is given as an input signal IN to the DUT 2 via the drive circuit 7 abbreviated as DR. The output signal OUT from the DUT 2 is compared with the expected value generated from the pattern generation circuit 4 at the timing determined by the output determination circuit 6 based on the determination timing signal from the timing generation circuit 3, and if they match, PA
If the SS signals do not match, the FAIL signal is output. The comparison result is stored in the determination result storage circuit 8 which is abbreviated as RM. The determination timing signal and the measurement timing signal have the same cycle.

FIG. 8 shows an electrical configuration of a prior art access time measuring apparatus 10 proposed by the applicant of the present application as Japanese Patent Laid-Open No. 6-324118 as a modification of the configuration of FIG. In this configuration, parts corresponding to those in FIG. 7 are designated by the same reference numerals, and redundant description will be omitted. The timing signal includes two different timing delay circuits 11, 12
Is generated from the timing generation circuit 13 so as to be separately derived from the maximum value side and the minimum value side of the access time. The cycles of the two determination timing signals are the same as those of the measurement timing signal, but the delay times are different. The output comparison circuit 16 responds to the two determination timing signals by
The output signal OUT from T2 is compared twice,
The judgment result is stored in the judgment result storage circuit 18, 1 for each timing signal.
9 are stored respectively.

FIG. 9 shows the measuring principle of the access time measuring device 1 shown in FIG. The timing generation circuit 3 determines from the measurement timing signal so that the period from the time t0 to the time t1 is one measurement cycle so that the input signal IN changes. The measurement cycle is set based on the operating speed of the DUT 2 so that the access time can be sufficiently measured. The determination timing signal generated from the timing generation circuit 3 is time t0 for each measurement cycle.
It is generated so that it becomes a measurement point that is shifted by a unit time Δt from t1 to t1. When a high level is expected as the output signal OUT and the determination result changes from F being FAIL to P being PASS at the measurement point of n × Δt, the access time is measured as n × Δt. . In such a measurement method, the maximum is (t1
The access time can be obtained with the accuracy of Δt by measuring −t0) / Δt times. In the prior art of FIG. 8, the measurement point can be changed from the maximum value side and the minimum value side, and two measurements can be performed in one measurement cycle, so the time required for the measurement can be shortened.

[0005]

In the configuration of FIG. 7, an input signal generating circuit including a timing generating circuit 3, a pattern generating circuit 4, a waveform format circuit 5 and a driving circuit 7, an output determining circuit 6 and a determination result. The output signal determination circuit configured by the storage circuit 8 operates according to the measurement timing signal and the determination timing signal having the same cycle, and therefore, the operation is performed once in one measurement cycle. Therefore, basically, the output determination circuit can make the determination only once for one operation cycle of the input signal applied from the input signal generation circuit to the DUT 2. Therefore, it is necessary to shift the measurement point for each measurement cycle as shown in FIG. 9 to search for the change point of the output signal. In the case of measuring the access time of the DUT 2, a very long measuring time is required especially for a memory device that operates at a low speed.

In the prior art of FIG. 8, two measurement points are provided in one measurement cycle to reduce the time required for access time measurement. However, the number of measurement points is determined by the circuit configuration of the input signal generation circuit including the timing delay circuits 11 and 12, the timing generation circuit 13, the pattern generation circuit 4, the waveform format circuit 5, and the drive circuit 7. It cannot be set arbitrarily. Further, the two determination timing signals need to be shifted so that one of them sequentially advances and the other of them sequentially delays, so that the circuit configuration itself becomes very complicated. Further, when the two determination timing signals are generated close to each other, the output determination circuit 16 needs to operate at a very high speed.

Generally, the access time measurement is performed by a test device capable of operating at high speed as a part of the function test of the semiconductor integrated circuit. This is because even if the semiconductor integrated circuit requires a relatively long access time, some AC characteristics to be measured must be measured in a short time. However, in the measuring method shown in FIG. 9, the measuring time is determined by the low-speed access time, and since the measurement is repeated many times, it takes a long time. Furthermore, the access time itself can be measured at the time when a match with the expected value is detected, but as shown in FIG. 7 in the prior art of JP-A-6-324118, the power supply voltage and the access time are It takes a longer time to perform the Shum characteristic evaluation, which is a two-dimensional characteristic evaluation showing the relationship.

An object of the present invention is to provide an access time measuring apparatus and method for a semiconductor integrated circuit which has a simple structure and can easily reduce the time required for measuring the access time.

[0009]

According to the present invention, an object to be measured is generated by generating an input signal for measurement having a predetermined waveform in a measurement cycle corresponding to the operating speed of a semiconductor integrated circuit whose access time is to be measured. The input signal generating circuit to be provided to the semiconductor integrated circuit and the determination cycle corresponding to the operating speed that is higher than the operating speed of the semiconductor integrated circuit and is possible as the measuring device, and the plurality of times are included in one measurement cycle of the input signal generation circuit , The output signal from the semiconductor integrated circuit in response to the timing signal from the determination signal generation circuit that generates the output determination timing signal and shifts the timing signal generation point for each measurement cycle, and the determination signal generation circuit. A comparison circuit that compares with a predetermined expected value to compare whether or not they match, and a comparison result of the comparison circuit divided into a plurality of times within one measurement cycle. And a storage circuit for storing, the determination signal generating circuit includes a frequency dividing circuit for dividing a signal having a determination cycle as a period, and generates a signal having the measurement cycle as an output of the frequency dividing circuit, The frequency divider circuit supplies the input signal generating circuit with a counter that counts clock signals having a determination cycle as a cycle, and compares the count value of the counter with data representing a preset frequency division ratio to match the count value. And a frequency division determination circuit that resets the count value of the counter when they match each other, and the storage circuit uses the count value of the counter as an address to store the comparison result of the comparison circuit. The access time measuring device for a semiconductor integrated circuit is characterized in that it is divided and stored for each determination cycle. According to the present invention, the semiconductor integrated circuit for which the access time is to be measured is supplied with the measurement input signal from the input signal generation circuit in the measurement cycle corresponding to its operating speed. The output from the semiconductor integrated circuit is compared with the expected value by the comparison circuit according to the timing signal generated from the determination signal generation circuit multiple times in one measurement cycle, and the comparison result is stored in the storage circuit in multiple times. To be done. By referring to the stored contents of the storage circuit, the time required from when the input signal is supplied until the comparison result matches the expected value can be obtained as the access time measurement value. Since multiple comparisons can be performed during one measurement cycle, a significant reduction in measurement time can be achieved.

Further, since the signal having the measurement cycle as the period is divided by the dividing circuit and given to the input signal generating circuit, if the dividing ratio is appropriately set, the measuring device operates at the maximum operating speed, Many comparisons can be made in one measurement cycle to maximize the reduction of measurement time.

Further, when the count value of the counter reaches a value preset as the frequency division ratio, the counter is reset by the judging circuit, and the counting of the clock signal having the cycle of the judging cycle is repeated again. By adding a simple configuration, the access time measurement time can be shortened.

Further, according to the present invention, a measurement input signal having a predetermined waveform is generated in the measurement target semiconductor integrated circuit in a measurement cycle corresponding to the operation speed of the semiconductor integrated circuit whose access time is to be measured. Predetermine signals from the semiconductor integrated circuit are given multiple times within one measurement cycle and with a time shift for each measurement cycle in a determination cycle corresponding to an independent operation speed that is faster than the input signal for measurement. When a comparison time point that matches the expected value is measured as the access time, the signal having the cycle of the determination cycle is divided to generate a signal having the cycle of the measurement cycle, and the measurement is performed. The counter counts the clock signal with the measurement cycle as the input signal for the counter and compares the count value of the counter with the data representing the preset frequency division ratio to match. It is determined whether or not there is a match, and if they match, the count value of the counter is reset, the coefficient is repeated, the count value of the counter is used as an address, and the comparison result is stored separately for each measurement cycle. And a method for measuring access time of a semiconductor integrated circuit. According to the present invention, in order to measure the access time of the semiconductor integrated circuit,
During one measurement cycle, a measurement for comparing the output from the semiconductor integrated circuit with an expected value is performed a plurality of times in a high-speed determination cycle that operates at an independent speed different from the measurement cycle,
A significant reduction in measurement time can be achieved.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a schematic electrical configuration of an embodiment of the present invention. Access time measuring device 2
0 is set according to an arbitrary condition set in the setting circuit 21.
The access time of the DUT 22 is measured. The timing generation circuit 23 of the present embodiment provides the pattern generation circuit 24 and the waveform format circuit 25 with a measurement timing signal having a cycle of a measurement cycle determined based on the operation speed of the DUT 22. The access time measuring device 20 itself can operate faster than the measurement cycle time. The output signal OUT from the DUT 22 is the comparison circuit 2
At 6, the value is compared with the expected value from the pattern generating circuit 24.
The output signal OUT is an input signal IN given to the DUT 22 from the waveform format circuit 25 via the drive circuit 27.
, And the time difference from the input to the output is measured as the access time.

In the present embodiment, the comparison in the comparison circuit 26 can be performed the number of times set by the setting circuit in one measurement cycle. The plurality of comparison results are divided into blocks and stored in the block-based determination result storage circuit 28. In the timing generation circuit 23, a frequency division counter 29 that performs frequency division at the frequency division ratio set by the setting circuit 21 and a timing generator 30 that generates a determination timing signal at a high speed operable as the access time measurement device 20. And are included. The determination timing signal is given to the comparison circuit 26 and the block-based determination result storage circuit 28, which designates the measurement point to be compared and indicates the switching timing of the blocks to be stored separately.

FIG. 2 shows the operation timing of the embodiment of FIG. In this embodiment, a case where the frequency division ratio N is set to 4 is shown. The determination cycle is executed with the test rate signal generated by the timing generator 30 as a reference. The frequency division counter 29 divides the test rate signal by four to generate a measurement timing signal which is a reference of the measurement cycle. An input signal to the DUT 22 is generated from the waveform format circuit 25 in synchronization with the measurement timing signal, and is supplied to the DUT 22 via the drive circuit 27. The output determination timing signal provided from the timing generator 30 to the comparison circuit 26 is generated N times during one measurement cycle, and the measurement cycle is divided into N blocks to obtain D
It is possible to take N measurement points within one operating cycle of the UT 22. Further, the output timing signal is generated by shifting in a constant time unit for each measurement cycle.

In the present embodiment, even in the low-speed operation DUT 22 which is particularly problematic in the prior art, the maximum measurement speed of the access time measuring device is used as the test rate, the value of the frequency division ratio N is selected, and the measurement cycle is set. If the operation speed of the DUT 22 is adjusted, the access time can always be measured at the highest measurement speed regardless of the operation speed of the DUT 22.

FIG. 3 shows an electrical configuration related to the setting circuit 21, the timing generation circuit 23, and the block-based determination result storage circuit 28 shown in FIG. The setting circuit 21 has m 2
4m and one m-input AND gate 50. 2-input AND gate 4
, 4m are supplied with m-bit division ratio setting signals S0, S1, ..., Sm. The other input of the 2-input AND gates 40, 41, ..., 4m is
M-bit output D0, D1, from the frequency division counter 29
..., Dm are given respectively.

From the AND gate 50, the m-bit frequency division ratio setting signals S0, S1, ..., Sm and the frequency division counter 29 are output.
, Dm of the m bits output from the high level output is derived only when the high level output is derived, and the reset signal RE for resetting the frequency dividing counter 29 is reset.
It becomes SET. Further, this output is the pattern generation circuit 2
4 and the waveform format circuit 25 are provided as a measurement timing signal indicating a measurement cycle. When the frequency divider counter 29 is reset, all the m-bit outputs D0, D1, ..., Dm representing the count value are at low level, and the test rate signal from the timing generator 30 is sequentially counted as the clock signal CK. That is, if a number N other than 0 is set as the frequency division ratio in the frequency division ratio signal, the frequency division counter 29 is reset every time the test rate signal is counted N times, and one measurement cycle is divided into N blocks. Will be done.

FIG. 4 shows the operation when setting the frequency division ratio N = 10 in FIG. The frequency division counter 29 matches the set value as the frequency division ratio when the test rate signal, which is the timing signal from the timing generator 30, is counted 10 times, so the measurement timing signal is output to the pattern generation circuit 24 and the waveform. Output to the format circuit 25,
The frequency division counter 29 itself is reset. by this,
The drive circuit 27 operates at a cycle 10 times as long as the cycle of the test rate signal, and supplies the input signal IN to the DUT 22 at a cycle 10 times as long as the test rate. Also,
Comparison circuit 26 and block-based determination result storage circuit 28
Operates in the same discrimination cycle as the test rate before frequency division, and outputs the output signal O from the DUT 22 for each test rate.
Perform UT determination. As a result, the output signal determination can be realized 10 times within one operation cycle of the input signal IN to the DUT 22. The determination results for 10 times are input to the address terminal of the block-based determination result storage circuit 28 using the count value of the frequency division counter 29 as a block number, and are stored for each determination block. Such a block-based determination result storage circuit 28 can be easily realized by a high-speed semiconductor memory. Therefore, only by providing the frequency division counter 29 and the memory as the block-based determination result storage circuit 28, it is possible to provide an arbitrary number of measurement points without constructing a complicated circuit,
The access time measurement can be speeded up. Further, since the time interval between the measurement points does not become shorter than the test rate, the comparison circuit 26 and the block-by-block determination result storage circuit 28 are not required to operate faster than the test rate.

FIG. 5 shows a procedure for measuring the access time of the DUT 22 in this embodiment. The measurement is started from step a1, and the division ratio is set in step a2 in consideration of the measurement cycle. At step a3, the DUT 22 is attached to the test socket. Next, in step a4, the input signal IN is applied from the drive circuit 27 to the DUT 22. In step a5, the comparison circuit 26 compares the output signal OUT from the DUT 22 with the expected value output from the pattern generation circuit 24 at the measurement point determined by the output determination timing signal. The comparison result is stored in the block-based determination result storage circuit 28 in step a6. Step a7
Then, it is determined whether or not the comparison of the frequency division ratio N times is completed. If not completed, the process returns to step a5 to move to the next block.

When the comparison of the frequency division ratio N times is completed in step a7, it is determined in step a8 whether or not the measurement is completed. If not finished, step a9
Then, the delay time of the output determination timing signal is shifted to shift the comparison timing, and the process returns to step a4. When it is determined in step a8 that the measurement is completed, step a
In step 10, the data stored in the block-by-block determination result storage circuit 28 is read, the access time is determined in step a11, and the measurement procedure for one DUT 22 is completed in step a12.

FIG. 6 shows in comparison (a) the difference between the case of measuring the access time of the DUT 22 according to the prior art as shown in FIG. 7 and (b) according to the concept of the present invention. DU
T22 operates at 100 ns and operates at 100 MHz (10 n
Assume a case where the access time is measured in 1 ns steps with a measuring device having the measurement speed of s). In the conventional technique of (a), one output measurement point is provided for one operation cycle of the input signal. In the present invention of (b), there are 10 output measurement points with N = 10. The measurement point is assumed to be shifted by 1 ns.

When the access time of the DUT 22 is 97 ns, one measurement point is changed in (a), and the output signal from the DUT 22 and the pattern generation circuit 24 are changed.
98 times are required to search for 97 ns that matches the expected value from According to this method, since there is one output measurement point for one operation cycle for measuring the access time of the DUT 22 operating at 100 ns, a maximum of 10
Zero measurements are required. Up to 5 when the operation is 500 ns
At 00 times and 1000 ns, the maximum is 1000 times.

In the present invention shown in (b), the frequency division ratio setting signals S0 to Sm of the setting circuit 21 are set to 1 in order to set N = 10.
Set to 0 decimal. When the timing generator 30 which is the test rate generates the discrimination timing signal of the cycle 10 ns 10 times, that is, when the frequency division counter 29 counts 10 times as the clock signal CK, the counter outputs D0 to Dm are divided by the frequency division ratio. It matches the signals S0 to Sm, and the pattern generation circuit 24 and the waveform format circuit 25
In addition to outputting the measurement timing signal of 100 ns cycle, the frequency dividing counter 29 itself is reset.

Therefore, as shown in FIG. 1, although an input signal having a cycle of 100 ns is applied to the DUT 22 by the drive circuit 27 operating at the timing from the waveform format circuit 25, the output from the timing generator 30 is output. Comparison circuit 26 that operates with the determination timing signal
Will determine the output from the DUT 22 at measurement points every 10 ns. As a result, it is possible to determine the output of 10 points for one operation cycle of the DUT 22. In addition, the determined result is stored in the block-based measurement result storage circuit 28 that operates at the operation timing 10 ns of the timing generator 30 for each block number 1 to 10. As shown in FIG. 3, the count values D0 to Dm of the frequency dividing counter 29 are stored in the block-based measurement result storage circuit 28.
Input as addresses A0-Am of block numbers 1-
Each of the 10 storage addresses is determined, and the determination result for each block from the comparison circuit 26 is stored in that address.

In the access time measuring device 20 of the present invention, as shown in FIG. 6 (b), the output judgment is performed in the cycle of 10 ns with respect to the operation cycle of 100 ns.
One operation cycle can be divided into 10 blocks of 10 ns each, and output determination can be performed for each block.
Therefore, in the case of an access time of 97 ns, the measurement result can be completed when the determination result of the 10th block matches the expected value with the number of measurements performed eight times. in this way,
In the present invention, for a DUT 22 operating at 100 ns,
The access time can be measured up to 10 times (N = 10). If the value of N that can be set arbitrarily is selected and set so that the maximum measurement speed (10 ns) of the measuring device can be measured, the operating speed of the DUT 22 will be 500 n.
If N = 50 and N = 100 are set for both s and 1000 ns, the measurement can be performed up to 10 times.
Therefore, high-speed access time measurement can be realized even in a semiconductor memory device operating at low speed. Also, the Shum characteristic evaluation and the like can be performed at high speed because the number of measurement cycles can be reduced.

[0027]

As described above, according to the present invention, since the access time can be measured a plurality of times in one measurement cycle, the measurement time required for highly accurate measurement can be greatly reduced. be able to. In addition, the Shum characteristics can be measured at high speed.

By appropriately setting the frequency division ratio, the measuring device can be operated at the maximum operating speed, and the measurement time can be shortened to the maximum.

Further, the access time measurement time can be shortened by adding a simple configuration in which the counter and the judging circuit are frequency dividing circuits.

Further, according to the present invention, the output from the semiconductor integrated circuit is compared with an expected value a plurality of times in a high-speed determination cycle that operates at an independent speed different from the measurement cycle during one measurement cycle. Measure access time,
A significant reduction in measurement time can be achieved.

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic electrical configuration of an embodiment of the present invention.

FIG. 2 is a time chart showing an example of the operation of the embodiment of FIG.

3 is a schematic logic circuit diagram of a determination signal generation circuit of the embodiment of FIG.

FIG. 4 is a time chart showing another example of the operation of the embodiment of FIG.

5 is a flowchart showing the operation of the embodiment of FIG.

FIG. 6 is a time chart showing a comparison between the conventional measuring method and the measuring method of the present invention.

FIG. 7 is a block diagram showing a schematic electrical configuration of an example of a conventional technique.

FIG. 8 is a block diagram showing a schematic electrical configuration of another example of the conventional art.

FIG. 9 is a time chart showing a conventional access time measuring method.

[Explanation of symbols]

20 Access time measuring device 21 Setting circuit 22 DUT 23 Timing generator 24 pattern generation circuit 25 waveform format circuit 26 Comparison circuit 27 Drive circuit 28 Block-based judgment result storage circuit 29 frequency division counter 30 timing generator 41-4m 2 input AND gate 50 m input AND gate

─────────────────────────────────────────────────── ─── Continuation of the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) G01B 31/319

Claims (2)

(57) [Claims] 1. An input signal for generating a measurement input signal having a predetermined waveform in a measurement cycle corresponding to an operation speed of a semiconductor integrated circuit whose access time is to be measured, and supplying the input signal to the semiconductor integrated circuit to be measured. Generates output judgment timing signals multiple times within one measurement cycle of the input signal generation circuit in a judgment cycle that is faster than the operation speed of the generation circuit and the semiconductor integrated circuit and corresponds to the operation speed possible as a measuring device. Then, in response to the timing signal from the determination signal generation circuit and the determination signal generation circuit, which shifts the timing signal generation point for each measurement cycle, the output signal from the semiconductor integrated circuit is compared with a predetermined expected value,
The determination signal generating circuit includes a comparison circuit that compares whether or not they match, and a storage circuit that stores the comparison result of the comparison circuit in a plurality of times within one measurement cycle. A frequency divider circuit for dividing a signal having a cycle as a cycle is provided, and a signal having the cycle as the measurement cycle is generated as an output of the frequency divider circuit and is given to the input signal generating circuit, wherein the frequency divider circuit is a decision cycle. The counter that counts the clock signal with the cycle is compared with the counter count value and the preset frequency division ratio data to determine whether they match, and when they match, the counter A frequency division determination circuit for resetting a numerical value, wherein the memory circuit uses a count value of a counter as an address and stores the comparison result of the comparison circuit for each determination cycle. Road of access time measurement device. 2. An input signal for measurement having a predetermined waveform is generated and applied to the semiconductor integrated circuit as the measurement target in a measurement cycle corresponding to the operating speed of the semiconductor integrated circuit as the access time measurement target, and the measurement is performed. In the judgment cycle corresponding to the independent operation speed faster than the input signal for, multiple times in one measurement cycle,
In addition, the signal from the semiconductor integrated circuit is compared with a predetermined expected value while shifting the time for each measurement cycle, and when the comparison time that matches the expected value is measured as the access time, the signal with the judgment cycle as the period is divided. Cycle, generate a signal with the cycle of the measurement cycle as the input signal for the measurement, count the clock signal with the cycle of the measurement cycle by the counter, and divide the count value of the counter by the preset frequency division. Compares with the data showing the ratio to determine whether they match, and when they match, resets the count value of the counter and repeats the coefficient, and uses the count value of the counter as the address to measure the comparison result. A method for measuring an access time of a semiconductor integrated circuit, characterized by storing the data separately for each cycle.