JP3396306B2 - Programmable logic array configuration method and programmable logic array module generator - Google Patents

Description

Detailed Description of the Invention

[0001]

The present invention relates to a programmable logic array formed on an LSI chip (hereinafter, PLA hereinafter) configuring the PLA for automatically generated using the software the layout of, and PLA module generational
The present invention relates to data.

[0002]

2. Description of the Related Art Conventionally, as a technique in such a field,
For example, some documents were described in the following documents. Reference 1: Takashi Tomizawa, Yasushi Matsuyama "Principles of CMOS VLSI Design" Maruzen Co., Ltd. P.335 Figure 2 shows a conventional CMOS PL
3 is a circuit diagram showing the configuration of A, FIG. 3 is a diagram showing a layout example of FIG. 2, and FIG. 4 is a diagram showing a truth table of FIG. 2 and 3, common reference numerals are given to common elements.

The PLA shown in FIGS. 2 and 3 is a PLA having three inputs, two outputs, and four product terms, and the second signal lines are input lines I1, I1 /, I2, I2. /, I3
I3 / and the product term lines P1, P2, P3 that are the first signal lines
12 logical products (hereinafter referred to as AN
AND array portion 1 having a sub region (that is, a cell ) , which is a region D, and an output line O, which is a fourth signal line.
1, O2 and product term lines P1, P2, P which are the third signal lines.
8 logical sums (3, P4 are orthogonal)
An OR array unit 2 having a sub-region (that is, a grid) which is a region ( OR ) , an input buffer unit 3, an output buffer unit 4, a product term line pull-up unit 5, and an output line pull-up unit 6 And have.

The AND array section 1 has transistors arranged in 12 cells according to "0" and "1" shown in the truth table of FIG. That is, the input lines I1, I1 /,
A transistor T is arranged at an intersection of I2, I2 /, I3, I3 / and each of the product term lines P1 to P4. Also in the OR array section 2, the output lines O1 and O2 are output according to the truth table.
And the transistor T is arranged at the intersection of the product term lines P1 to P4.

FIGS. 5 (i) and 5 (ii) are explanatory views of a conventional PLA module generator for automatically generating the layout of the PLA of FIG. 2, and FIG. 5 (i) is a block diagram of the configuration of the PLA module generator, and FIG. Figure (ii) is PLA
3 is a flowchart showing a method of configuring the above. The PLA module generator, for example, automatically generates the PLA layout of FIG. 2 by software, and includes a file reading unit t11 and a base layout generating unit t12 connected to the file reading unit t11. The output side of the base layout generating section t12 is connected to the AND array programming section t13, and the output side of the AND array programming section t13 is connected to the OR array programming section t14. The PLA module generator is also provided with a logical description file t15 and a leaf cell layout t16. The logical description file t15 is connected to the file reading unit t11, and the leaf cell layout t16 is connected to the base layout generating unit t12.

In this PLA module generator,
In step S1, the file reading unit t11 reads a corresponding file from the logic description file t15 that describes the logic of the PLA to be realized. FIG. 6 is a diagram showing a description example of the logical description file t15 in FIG. The number of PLA inputs, the number of outputs, the number of product terms, and the actual logic table, that is, the truth table, are described in the logic description file t15. In the example of FIG. 6, an example corresponding to the truth table of FIG. 4 is shown. ing. In the next step S2, the leaf cell layout t16 of each part prepared in advance is read based on the number of inputs, the number of outputs, the number of product terms, and the actual logical table in the file read by the background layout generation unit t12, and the PLA Create the entire background layout.

FIG. 7 is a diagram showing the base layout of FIG. As shown in FIG. 7, the underlying layout is formed of an active layer, a polysilicon layer, a metal layer, and a P implantation layer on the substrate. In the next step S3, based on the truth table read by the file reading unit t11, the AND array programming unit t13 places an N-channel field effect transistor (hereinafter referred to as N-type field effect transistor) at a necessary location in the AND array unit 1.
Place T) (called MOS). The procedure for specifically arranging the NMOST is as follows. For example, in order to program "0" in the first row and the first column from the truth table of FIG. 4, an NMOST1 is arranged between the input line I1 / and the product term line P1, and then the "T" in the first row and the second column is read. To perform 1 "programming, an NMOST2 is created between the input line I2 and the product term line P1. In the case of "-"don't care as in the 1st row and 3rd column, the NMOS is not arranged. Thereafter, the same operation is repeated to form the AND array section 1. Further, in step S4 after step S3, the NMOST is arranged in the OR array section 2.

[0008]

However [0005] In <br/> configuring and PLA module generator of conventional PL A, it has the following problems. Since the configuration is such that the NMOST is arranged in each cell of the AND array section 1 and the OR array section 2 according to the logic to be realized, that is, the truth table, the AND array section 1 and the OR array section 2 have N
It is composed of only one of the squares where the MOST is arranged and the square where the MOST is not arranged. When forming a large-scale PLA, for example, the area of the array region in which only the NMOST is arranged in the CMOS including the NMOS and the P-channel field effect transistor (hereinafter referred to as PMOS) becomes large, and the potential of the P-type substrate is changed to the ground potential. sub contacts fixed to Vss is, it will not be extensively arranged I passed. Therefore, there is a problem that a latch-up phenomenon peculiar to the CMOS circuit occurs and the operation of the LSI becomes unstable.

In order to solve the above problem, in FIG.
A region 7 for arranging sub-contacts for fixing the mold substrate potential is secured in advance in the base layout. However, providing the sub-contact regions 7 in the AND array section 1 and the OR array section 2 unnecessarily increases their areas, and as a result, there is a problem that the area of the entire PLA becomes large. On the other hand, the PLA module generator prepares leaf cells for sub-contacts in the base leaf cell file and forms a base layout having independent regions 7 as shown in FIG. 7 to prevent sub-contacts from being arranged over a wide range. I am trying to solve the problem. However, reducing the area of the entire PLA
Was difficult.

[0010]

In order to solve the above-mentioned problems, the first invention of the present invention is such that each is in a predetermined direction.
A plurality of extending first signal lines, and a plurality of the first signal lines
A plurality of second signal lines extending across the signal line of
And are provided on the front surface side of the substrate to form an AND array.
Together, each corresponds to a corresponding one of the plurality of first signal lines
A plurality of third signal lines electrically connected to each other,
A plurality of fourth signals extending across the plurality of third signal lines
And a signal line of the above are provided on the front surface side of the substrate to form an OR array.
In the PLA forming method to be formed, the following processing is performed.
Is going.

That is, the AND array and the OR array
The array area forming the a is defined by the plurality of first and second array areas.
Each intersection of the signal lines and the plurality of third and fourth signal lines
It is divided into a plurality of sub-regions each including each intersection. So
Then, in the truth table showing the desired logic,
In the sub area where it is instructed to place,
The first step of selectively arranging the star and the truth table
The sub-region indicating that no transistor is to be placed
Of the AND array side and the OR array side
The sub-region on one or the other of the sub-regions.
Second process for arranging contacts to fix the potential of
I try to do it.

The second invention is the configuration of the PLA of the first invention.
In the method, before the first step, the second step
A plurality of said contacts to be placed in
Contents of the truth table so that they are evenly arranged in the area
After rearranging the
Based on the above, the first step and the second step are performed.
I am sorry.

According to a third invention, each extends in a predetermined direction.
A plurality of first signal lines, and each of the plurality of first signals
A plurality of second signal lines extending across the line;
It is provided on the front side of the plate to form an AND array and
Each electrically to the corresponding one of the plurality of first signal lines
A plurality of connected third signal lines and a plurality of the third signal lines
A plurality of fourth signal lines extending so as to cross the signal line of No. 3
And are provided on the front surface side of the substrate to form an OR array.
In the PLA module generator, the plurality of first
Base layer for arranging first, second, third and fourth signal lines
Out part, programming part, contact placement part,
Is equipped with. The programming unit includes the AND
The array area forming the ray and the OR array,
Each intersection of a plurality of first and second signal lines and the plurality of first
And a plurality of intersections of the third and fourth signal lines, respectively.
It is divided into sub areas, and a truth table that expresses the desired logic is created.
And the sub
Transistors are selectively arranged in the region.
The contact placement part is
Of the sub-areas instructing not to place
Both the AND array side and the OR array side, or their
The potential of the substrate is fixed to one of the sub regions
The contact for disposing is arranged.

The fourth invention is a PLA module of the third invention.
In the contact generator,
The plurality of contacts to be arranged are arranged in the array area.
The contents of the truth table are arranged so that they are evenly distributed in the area.
Based on this sorted truth table
Processing in the programming section and the contact placement section
A truth table sort section is provided for performing the reason.

[0015]

According to the first invention, an AND array and an OR array are provided.
The array area forming the ray is divided into multiple sub areas
It Then, in the first step, based on the truth table,
In the predetermined sub-regions on the AND array side and the OR array side,
A transistor is arranged. Then in the second step
Based on the truth table, AND array side and OR array side
Transistors placed in both or either
To fix the substrate potential to a predetermined sub-region that is not
Contacts are placed. According to the second invention, a plurality of
The contacts are evenly distributed over the array area,
The contents of the truth table are rearranged. Then this average
Based on the replaced truth table, in the first step,
Transistors are arranged in the sub-region, and in the second step,
The contour is placed in a predetermined sub area where the transistor is not placed.
Are placed.

According to the third invention, an AND array and O
The array area forming the R array is divided into a plurality of sub areas.
Be kicked. Then, the base layout section allows a plurality of first
The first, second, third and fourth signal lines are arranged and
Based on the truth table, the
A transistor is arranged. After that, the contact placement part
The transistor is arranged according to the truth table.
The contact is arranged in a predetermined sub region which is not present. Fourth
According to the invention of claim 1, the truth table sorting unit
The contents are sorted and based on this sorted truth table.
Based on the
And the contact placement part
Are uniformly arranged in the array area.

[0017]

Embodiment (First Embodiment) FIG. 1 is a layout diagram of a PLA showing a first embodiment of the present invention. This PLA is shown in FIG. 2 used in the description of the conventional example.
4 to obtain a logic output equivalent to that of FIG. 4, and elements common to those of FIGS. 2 and 3 are denoted by common reference numerals. Figure 1
Is a PLA having 3 inputs, 2 outputs, and 4 product terms, and has input lines I1, I1 /, I on the P-type substrate.
2, I2 /, I3, I3 /, the output lines O1 and O2, and the four product term lines P1 to P4 are arranged in an intersecting manner. PLA
Are input lines I1, I1 /, I2, I which are second signal lines.
2 /, I3, I3 / and the product term line P1 which is the first signal line
Sub-areas that are 12 AND areas formed by P4
The AND array unit 1 having (that is, a square ) , the output lines O1 and O2 which are the fourth signal lines, and the product term lines P1 to P4 which are the third signal lines are orthogonal to each other. The OR array unit 2 having a sub region (that is, a square ) which is an OR region, the input buffer unit 3, the output buffer unit 4, the product term line pull-up unit 5, and the output line pull-up unit 6 In order to obtain the logical output of the truth table of FIG. 4, NMOS T1, T2, ... Are selectively laid out at the cells in the AND array section 1 and the OR array section 2 that are configured.
Further, a plurality of contacts (that is, sub-contacts ) A13, A32, O12, O21, O41, O42 for fixing the substrate potential are arranged in the cells where the NMOSs T1, T2, ... Are not arranged.

In the AND array section 1, the sub-contacts A13, to the cells corresponding to the 1st row and 3rd column and the 3rd row and 2nd column where "-"don't care shown in the truth table of FIG. 4 is to be programmed. A32 is arranged. Similarly, O
In the R array section 2, sub-contacts O12, O21, O41 in the cells corresponding to the 1st row, 2nd column, 2nd row 1st column, 4th row 1st column, and 4th row 2nd column where “0” should be programmed. ，
O42 is arranged. In this way, NMOST1, ...
Sub-contact A1 formed in the square where no
3, A32, O12, O21, O41, O42 fix the potential of the P-type substrate to the ground potential Vss. That is, the potential of the P-type substrate is appropriately fixed to the ground potential Vss like the conventional sub-contact formed in the sub-contact disposing region 7.

As described above, in this embodiment, the NMOS array T1, ... Is not provided in the AND array section 1 or the OR array section 2 in the PLA in advance without providing the area 7 for sub contact arrangement.
Sub-contacts A13, A32, O on the grid where no
12, O21, O41 and O42 are arranged. Therefore, AN
The area of the D array section 1 or the OR array section 2 is reduced, and the area of the entire PLA can be reduced.

(Second Embodiment) FIG. 8 is a layout diagram of a PLA showing a second embodiment of the present invention. Elements common to those in FIGS. 1, 2 and 3 are designated by common reference numerals. Has been done. PLA of FIG. 1 of the first embodiment
, The sub-contacts A13, ..., O12, ... Formed in the grids in which the NMOST1, ... Are not arranged are arranged in both the AND array section 1 and the OR array section 2, but FIG.
In the PLA shown in (1), a sub-contact disposing region 8 is set in advance in the AND array portion 1 and sub-contacts are formed therein. Similar to the first embodiment, only the OR array section 2 has sub-contacts O12, O21, O41 and O42 arranged in the cells where no NMOS is arranged.

Depending on the truth table to be realized by PLA,
In some cases, there is no square in the AND array section 1 for programming a "-" of don't care. In such a case, the sub-contacts O12, ... Are arranged in the cells of the OR array section 2 where no NMOS is arranged. In the case of the OR array unit 2, the cells for programming "0" are
Since the NMOS is not arranged, the sub-contacts O12, ... Can be arranged in the grid. Therefore, in general, in any truth table, the sub contact O
It is possible to arrange 12, ... As described above, in this embodiment, the sub-contacts O12, ... Are formed in the cells of the OR array section 2. Therefore, the area of the OR array unit 2 becomes smaller than that of the conventional PLA, and the area of the PLA can be reduced.

(Third Embodiment) FIG. 9 is a configuration block diagram of a PLA module generator showing a third embodiment of the present invention. This PLA module generator includes a logical description file 11 in which the number of PLA inputs, the number of outputs, the number of product terms, and an actual logical table, that is, a truth table, and a file reading for reading the description content of the logical description file 11 are read. And a part 12.
The output side of the file reading unit 12 is the background layout unit.
It is connected to a certain underlying layout generation unit 13. The PLA includes a layout leaf cell 14 that stores a leaf cell file necessary for creating a base layout, and the layout leaf cell 14 is connected to the base layout generating unit 13. Base layout generation unit 13
The output side of is connected to the AND array programming section 15, and the output side of the AND array programming section 15 is connected to the AND array sub-contact arrangement section 16. The output side of the AND array sub-contact arrangement section 16 is connected to the OR array programming section 17, and this OR
The output side of the array programming section 17 is connected to the OR array sub-contact arrangement section 18 .

FIG. 10 is a flow chart showing the operation of FIG. 9, and a method of constructing a PLA using the PLA module generator of FIG. 9 will be described with reference to this figure. Figure 1
In step S11 of 0, the file reading unit 12 reads parameters such as the number of inputs, the number of outputs, the number of product terms, and the truth table of the target PLA described in the logic description file 11. In subsequent step S12, the base layout generating unit 13 reads a leaf cell file prepared in advance in the layout leaf cell 14 and forms a layout of the entire base of the PLA based on the parameters. In step S13, the AND array programming unit 15
Is based on the logic described in the logic description file 11, that is, the truth table, and, for example, the NMOST1, ... Are arranged in the necessary cells in the AND array unit 1 of FIG. In step S14, the AND array sub-contact arrangement unit 16 extracts the cells in which the NMOST1, ... Are not arranged in the AND array unit 1 from the truth table given from the logic description file 11, and the extracted cells are extracted. Sub-contacts A13, ... For fixing the substrate potential are arranged with respect to. In step S15, the OR array programming unit 17 uses the truth table to generate N cells in the required cells in the OR array unit 2.
Place the MOS. In the final step S16, O
The R array sub-contact placement section 18 extracts a cell in which no NMOS is placed in the OR array section 2 from the truth table given from the logic description file 11, and fixes the substrate potential to the extracted cell. Sub contact O1
Place 2, ...

As described above, in this embodiment, the PLA module generator for automatically generating the PLA layout is provided with the NMOS in the AND array section 1 and the OR array section 2.
The AND array sub-contact arranging section 16 and the OR array sub-contact arranging section 18 having the function of extracting the squares in which the sub-contacts are not arranged and arranging the sub-contacts A13, ..., O12, ... In the extracted squares are provided. The PLA can be formed without separately providing sub-contact arrangement regions in the AND array section 1 and the OR array section 2, and the area of the entire PLA can be reduced.

(Fourth Embodiment) FIG. 11 is a block diagram showing the configuration of a PLA module generator according to a fourth embodiment of the present invention. Elements common to those in FIG. 9 are designated by common reference numerals. . P of this embodiment
The LA module generator is obtained by adding a truth value table sorting unit 20 to the third embodiment, and the other configuration is shown in FIG.
It is the same as the PLA module generator. The truth table sort unit 20 is connected between the file reading unit 12 and the base layout generating unit 13. The truth table sort unit 20 uses the PLA read from the logical description file 11.
It has the function of rearranging the order of the rows of the truth table.
The order of the rows of the truth table is rearranged by the product term lines P1 to P
It is the same as rearranging the order of 4. 12
13 (i) and 13 (ii) are diagrams showing rearrangement by the truth value table sorting unit 20 in FIG. 11, and FIGS. 13 (i) and 13 (ii) are explanatory diagrams of FIG.

Next, a method of constructing a PLA using the PLA module generator shown in FIG. 11 will be described. For example, when the logic of the truth table as shown in FIG. 12 (i) is realized in the PLA, "-" in the portion corresponding to the AND array unit 1 of the truth table, that is, the don't care is the RBI input in the sixth column. Since it is concentrated on the 18th row, which is the bottom row, the substrate potential fixing sub-contacts SC are concentrated on the right end and the bottom of the AND array section 1 as shown in FIG. Therefore, the substrate potential at the center of the AND array section 1 becomes unstable. The truth table sort unit 20 sorts the truth table as shown in FIG. 12 (ii), for example. In this example, the 18th line at the bottom is moved to the 10th line. After the truth table is rearranged, each unit after the base layout generating unit 13 performs the same operation as that of the third embodiment, so that P shown in FIG. 13 (ii) is obtained.
LA is formed. That is, the layout is such that the sub-contact SC is also arranged in the center of the AND array section 1.

As described above, in this embodiment, the PLA module generator is provided with the truth table sort section 20 for rearranging the rows of the truth table, and the PLA layout is performed after the truth table is rearranged. Since it is performed, even in the case of the truth table in which the arrangement of the sub-contacts SC is concentrated in a specific place,
The sub contacts SC can be uniformly arranged in the AND array section 1. Therefore, the potential of the substrate can be stabilized.

The present invention is not limited to the above embodiment, and various modifications can be made. The following are examples of such modifications. (1) In the second embodiment, the sub-contacts O12, ... Formed in the squares are arranged only in the squares in the OR array section 2, but only the sub-contacts in the AND array section 1 are arranged. Is also possible. (2) In the third and fourth embodiments, the AND array programming unit 15 and the OR array programming unit 17, and the AND array sub-contact arrangement unit 16 and O.
Although the R array sub-contact disposing section 18 is provided independently, the function may be included as a programming section. In this case, the AND array programming section has a function of arranging the sub-contact SC in the cell where "-"don't care should be programmed in the logic description file 11, and the OR array programming section has "0" in the logic description file 11. It has a function of arranging the sub-contact SC in the cell where "" should be programmed.

As described in detail above, according to the first invention, an array forming an AND array and an OR array is formed.
Divide the area into multiple sub-areas, and specify the predetermined value based on the truth table.
The transistor in the sub-region of the
Based on the value table, the specified
A contact for fixing the electric potential of the substrate is provided in the sub region.
It is arranged. Therefore, based on the truth table,
To fix the potential of the substrate and the sub area where the transistor is placed.
For easy identification of the sub area where the contact for
You can As a result, contact placement in PLA
The area can be reduced because it is not necessary to provide a separate storage area.
Large-scale PLA can be configured easily and at high speed.
It will be possible. According to the second invention, the content of the truth table
After performing the replacement, perform the first and second steps.
So that multiple contacts are evenly distributed in the array area.
Be done. This improves the stability of the PLA substrate potential.
To do.

According to the third invention, the array area is divided into a plurality of areas.
Sub-regions are divided into a plurality of first and first sub-layout sections.
Place the 2nd, 3rd and 4th signal lines according to the truth table.
Then, the programming unit
Place a register, and based on the truth table,
No transistor is placed by the tact placement unit
The contact is arranged in a predetermined sub-region. That
Therefore, as in the first invention, based on the truth table,
The sub area where the transistors are placed and the sub area where the contacts are placed.
It is possible to easily confirm the sub-region. By this
And a large-scale PLA layout that can reduce the area,
It becomes possible to generate easily and at high speed. According to the fourth aspect of the present invention, the truth table sorting unit sorts the contents of the truth table.
After rearranging, programming department and contacts
Since the processing is performed in the arrangement unit, the second invention
Much like the multiple contacts are evenly distributed over the array area.
Are arranged, which improves the stability of the potential of the PLA substrate.
Go up.

[Brief description of drawings]

FIG. 1 is a layout diagram of a PLA according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a conventional general PLA.

FIG. 3 is a diagram showing a layout example of FIG.

FIG. 4 is a diagram showing a truth table of FIG.

5 is an explanatory diagram of a conventional PLA module generator that automatically generates the layout of the PLA of FIG.

FIG. 6 is a diagram showing a description example of a logical description file in FIG.

FIG. 7 is a diagram showing a background layout of FIG.

FIG. 8 is a layout diagram of a PLA according to a second embodiment of the present invention.

FIG. 9 is a configuration block diagram of a PLA module generator showing a third embodiment of the present invention.

FIG. 10 is a flowchart showing the operation of FIG.

FIG. 11 is a configuration block diagram of a PLA module generator showing a fourth embodiment of the present invention.

FIG. 12 is a diagram showing rearrangement by a truth table sort unit in FIG. 11.

FIG. 13 is an explanatory diagram of FIG. 12.

[Explanation of symbols]

1 AND array section 2 OR array section 13 Underlay layout section 15, 17 Programming section 16, 18 Sub-contact arrangement section T1, T2 NMOS I1, I1 /, I2, I2 /, I3, I3 / Input line O1, O2 Output line P1 ~ P4 Product term line A13, A32, O12, O21, O41, O42 Sub contact

Claims (2)

(57) [Claims] 1. A plurality of first members each extending in a predetermined direction.
And a plurality of second signal lines each extending so as to cross the plurality of first signal lines on the front surface side of the substrate to form an AND array and each of the plurality of signal lines. A plurality of third signal lines electrically connected to corresponding ones of the plurality of first signal lines, and a plurality of fourth signals each extending across the plurality of third signal lines. And a line on the front surface side of the substrate to form an OR array, the array region forming the AND array and the OR array is defined by the plurality of first and second signal lines. It is instructed that the transistors be arranged in a plurality of sub-regions each including each of the intersections and each of the intersections of the plurality of third and fourth signal lines and a truth table representing a desired logic is arranged. Transistors in the sub-region A first step of disposing the 択的, among the sub-regions for instructing not to place a transistor in the truth table, the said AND array side O
Both or one of the sub-region that either R array side, a second step of placing a contact for fixing the potential of the substrate, which performs the first Engineering
Prior to this, a plurality of the contacts to be placed in the second step
Are arranged so that they are evenly arranged in the array area.
After rearranging the contents of the truth table,
Based on the truth table, the first step and the second step
A method for configuring a programmable logic array, characterized in that 2. A plurality of first members each extending in a predetermined direction.
Signal lines and each crosses the plurality of first signal lines.
A plurality of second signal lines extending in the direction of
To form an AND array, and each of the plurality of
Of a plurality of electrically connected to the corresponding one of the first signal lines of
A number of third signal lines and each of the plurality of third signal lines
A plurality of fourth signal lines extending transversely,
Programmable board provided on the front side of the plate to form an OR array
In the logic array module generator, the plurality of first, second, third and fourth signal lines are arranged.
Array forming the base layout section that, the AND array and the OR array
The area is defined as each intersection of the plurality of first and second signal lines.
The intersections of the plurality of third and fourth signal lines are respectively
It is divided into multiple sub-regions that contain the desired logic.
The truth table instructed that the transistors should be arranged.
Transistors are selectively arranged in the sub-region
Instruct the programming section and the fact that no transistors are placed in the truth table
Of the sub-regions, the AND array side and the O
Both or one of the sub-regions on the R array side
Contacts to fix the electric potential of the substrate.
The contact placement part to be placed, and the plurality of cores to be placed in the contact placement part.
Contacts are evenly distributed in the array area.
Then, the contents of the truth table are rearranged, and this rearrangement is performed.
Based on the obtained truth table, the programming unit and
Truth table saw for performing processing in the contact placement section
Programmable logic array characterized by comprising a preparative unit, the
A module generator.