JP3397272B2 - Method for manufacturing field effect transistor - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a field effect transistor in which channel formation is controlled by applying a voltage to a gate electrode.

[0002]

2. Description of the Related Art FIG. 7 shows a field effect transistor having a double gate structure. In this field effect transistor, n-type or p-type source / drain regions 13a and 13b are formed on both sides of an n ⁻ type, p ⁻ type or i type channel region 12 of a semiconductor layer 11, and the gate insulating layer 1 is formed.
Gate electrodes 15a and 15b are provided on both upper and lower surfaces of the channel region 12 via 4a and 14b.

In order to manufacture such a field effect transistor, conventionally, the semiconductor layer 11 is epitaxially grown on the gate insulating layer 14a by so-called lateral solid phase epitaxial growth, or the gate is formed by bonding or grinding two wafers. The semiconductor layer 11 is formed on the insulating layer 14a.

In the field effect transistor shown in FIG. 7,
Channel region 12 from both gate electrodes 15a, 15b
As compared with the single gate structure, the number of carriers induced in the channel region 12 is large, the current driving capability and the transconductance are high, and the punch-through between the source / drain regions 13a and 13b is also possible. Does not happen.

Further, the gate electrodes 15a and 15b are operated independently of each other, and for example, these gate electrodes 15a and 1b are operated.
By applying a bias to the channel region 12 on the other hand, it is possible to easily realize various characteristics without introducing impurities into the channel region 12.

[0006]

However, since the power supply voltage is also decreasing with the miniaturization of the field effect transistor, even the field effect transistor having the double gate structure shown in FIG. Is not enough.

Further, in the conventional method of forming the semiconductor layer 11 on the gate insulating layer 14a by the lateral solid phase epitaxial growth, the crystallinity of the semiconductor layer 11 is inferior, so that the carrier mobility is high and the operation speed is high. It has been difficult to manufacture field effect transistors.

On the other hand, the semiconductor layer 11 is formed on the gate insulating layer 14a by bonding or grinding two wafers.
According to the conventional method of forming the semiconductor layer 11, since the semiconductor layer 11 has excellent crystallinity, a field effect transistor having a high carrier mobility and a high operation speed can be manufactured.
The manufacturing cost was high because a single wafer was required.

[0009]

A method of manufacturing a field effect transistor according to a first aspect of the present invention relates to a first gate electrode which is in contact with each other in a depth direction of a semiconductor substrate and is embedded at a relatively deep position. Forming a first gate insulating layer buried in a shallow position by ion implantation into the semiconductor substrate, and the first gate electrode of the semiconductor substrate
A step of deleting said semiconductor body to a depth of the leaving columnar portion Ru extends through the upper first gate insulating layer, forming a second gate insulating layer on the exposed surface of the columnar portion, A step of forming a second gate electrode in contact with the second gate insulating layer on at least two surfaces of a portion on the first gate electrode in the columnar portion.

A method for manufacturing a field effect transistor according to a second aspect is the method for manufacturing a field effect transistor according to the first aspect, wherein an impurity layer formed by ion implantation of impurities into the semiconductor substrate is used as the first gate electrode. The semiconductor oxide layer formed by ion implantation of oxygen into the semiconductor substrate is used as the gate insulating layer.

A method of manufacturing a field effect transistor according to a third aspect is the method of manufacturing a field effect transistor according to the first aspect, wherein a portion of the second gate electrode facing at least one of the surfaces is a surface of the other surface. And a step of separating from a portion facing to.

[0012]

In the field effect transistor manufacturing method of the present invention, since the gate electrodes are formed on at least three surfaces of the columnar portion where the active region is to be formed, a single gate structure or a double gate structure is formed. It is possible to manufacture a field effect transistor in which the number of carriers induced in the channel region is large and the degree of freedom of wiring is large as compared with the gate structure.

Moreover, a gate electrode and a gate insulating layer embedded in the semiconductor substrate are formed by ion implantation into the semiconductor substrate, and the semiconductor substrate is removed to form a columnar portion where an active region is to be formed. Therefore, despite forming the gate electrodes on at least three surfaces of the columnar portion, it is possible to manufacture a field effect transistor having an active region with excellent crystallinity from one wafer. it can.

In the method of manufacturing a field effect transistor according to a third aspect of the present invention, since the gate electrode formed after forming the columnar portion where the active region of the field effect transistor is formed is separated into at least two, it is independent of each other. It is possible to manufacture a field effect transistor with at least three gate electrodes in operation.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The first to fourth embodiments of the present invention applied to the manufacture of MOS transistors will be described below with reference to FIGS. 1 to 3 show the first embodiment.
In the first embodiment, as shown in FIG. 1A, first, the resist 22 is processed on the Si substrate 21 into a pattern of the gate electrode to be formed under the active region.

After that, impurities 23 are ion-implanted using the resist 22 as a mask to form an impurity layer 24 embedded in the Si substrate 21. Then, the resist 22 again
Oxygen 25 is ion-implanted by using as a mask, and the Si substrate 2
1 and the SiO ₂ layer 26 is formed on the impurity layer 24.

Next, as shown in FIG. 1B, the Si substrate 2
The resist 27 is processed in the pattern of the active region on the first substrate.
Then, the Si substrate 21 using the resist 27 as a mask
In the RIE with respect to
The Si substrate 21 is etched to the depth of the O ₂ layer 26.

Next, as shown in FIG. 1C, the resist 2
7 is removed, and the columnar portion 31 having a height of about 0.1 to 0.2 μm is formed on the Si substrate 21. Then, as shown in FIG. 2 (a), after forming the SiO ₂ layer 32 by thermal oxidation on the surface of the Si substrate 21 including the columnar portion 31, to remove the SiO ₂ layer 32 other than the surface of the columnar portion 31.

Next, as shown in FIGS. 2B and 2C, the polycrystalline Si layer 33 deposited on the entire surface is patterned to form a polycrystalline Si layer only on and around the columnar portion 31. Three
Leave 3 Then, as shown in FIG.
A resist 34 is processed on the polycrystalline Si layer 33 and the Si substrate 21 in a pattern that extends over the gate electrode to be formed on the upper and side surfaces of the columnar portion 31.

Next, as shown in FIG. 3B, the resist 3
RIE using No. 4 as a mask is performed on the polycrystalline Si layer 33, and impurity layers 35a and 35b are formed in the columnar portion 31 by ion implantation of impurities with the same resist 34 being masked. afterwards,
As shown in FIG. 3C, the resist 34 is removed, and further,
This MOS transistor is completed through conventionally known steps.

In the MOS transistor manufactured in the first embodiment as described above, the columnar portion 31 is the active region,
The impurity layers 35a and 35b are source / drain regions, and the portion of the columnar portion 31 between the impurity layers 35a and 35b is a channel region. Also, Si
The O ₂ layers 26 and 32 are gate insulating layers, and the impurity layer 24 and the polycrystalline Si layer 33 are gate electrodes. Therefore, the gate electrode surrounds four surfaces around the channel region.

FIG. 4 shows a second embodiment. Also in this second embodiment, as shown in FIG.
Until the resist 34 used for patterning No. 3 and forming the impurity layers 35a and 35b is removed, substantially the same steps as those in the above-described first embodiment are performed. But this second
In the embodiment, thereafter, the resist 36 is processed on the polycrystalline Si layer 33 on the columnar portion 31 into a pattern having the width of the columnar portion 31.

Next, as shown in FIGS. 4B and 4C, RIE using the resist 36 as a mask is applied to the polycrystalline Si layer 33 to form the polycrystalline Si layer 33a on one side surface of the columnar portion 31. The polycrystalline Si layer 33 is separated into a polycrystalline Si layer 33b on the columnar portion 31 and a polycrystalline Si layer 33c on the other side surface of the columnar portion 31. After that, the MOS transistor is completed again through the conventionally known steps.

In the MOS transistor manufactured in the second embodiment as described above, the impurity layer 24 and the polycrystalline Si layer 33a are used.
.About.33c are gate electrodes, and the gate electrode surrounds four surfaces around the channel region.
The gate electrodes corresponding to the planes are all separated from each other.

FIG. 5 shows a MOS transistor manufactured in the third embodiment. In the third embodiment, the columnar portion 31
Substantially the same steps are performed as in the second embodiment described above, except that the polycrystalline Si layer 33b is not formed on the upper surface. In the third embodiment as described above, planarization of the interlayer insulating film and the like is easy because the polycrystalline Si layer 33b is not formed.

FIG. 6 shows a MOS transistor manufactured in the fourth embodiment. In this fourth embodiment, the columnar portion 31
Substantially the same steps as those of the second embodiment described above are performed except that the polycrystalline Si layer 33c is not formed on the other side surface of the. In the fourth embodiment as described above, the area occupied by the MOS transistor can be reduced by the amount that the polycrystalline Si layer 33c is not formed, and high integration can be achieved.

In any of the above-described first to fourth embodiments, the SiO ₂ layer 26 formed by ion-implanting oxygen 25 into the Si substrate 21 and the surface of the columnar portion 31 are thermally oxidized. MO with the SiO ₂ layer 32 formed as a gate insulating layer
An S transistor was manufactured. For example, the SiN layer formed by ion-implanting nitrogen into the Si substrate 21 and the columnar portion 3
It is also possible to manufacture a field effect transistor having a SiN layer formed by thermally nitriding the surface of 1 as a gate insulating layer.

[0028]

According to the method of manufacturing a field effect transistor of the first and second aspects, it is possible to manufacture a field effect transistor in which the number of carriers induced in the channel region is larger than that of a single gate structure or a double gate structure. Therefore, it is possible to manufacture a field effect transistor having high current drive capability and high transconductance.

Further, since it is possible to manufacture a field effect transistor having a greater degree of freedom in wiring than a single-gate structure or a double-gate structure, it is advantageous for forming a complicated wiring, and it is possible to manufacture a fine integrated circuit device. It is also possible to manufacture a field effect transistor which is convenient for high integration and high integration.

Moreover, even though the gate electrodes are formed on at least three surfaces of the columnar portion in which the active region is to be formed, one field effect transistor having an active region having excellent crystallinity is provided. Since it can be manufactured on a wafer, it is possible to manufacture a field effect transistor that has high carrier mobility and operates at high speed at low cost.

In the method of manufacturing the field effect transistor according to the third aspect, since it is possible to manufacture the field effect transistor having at least three gate electrodes that operate independently of each other, the degree of freedom in controllability of the gate voltage is large, It is possible to fabricate field effect transistors which are advantageous for the formation of integrated circuit devices which require complex control.

[Brief description of drawings]

FIG. 1 is a front sectional view sequentially showing an initial step in a first embodiment of the present invention for manufacturing a MOS transistor.

2A to 2C sequentially show a middle-stage process in the first embodiment, wherein FIGS. 2A and 2B are front sectional views and FIG. 2C is a plan view of the state of FIG. 2B.

FIG. 3 is a sequential view showing the final step in the first embodiment, in which (a) and (b) are plan views and (c) is a front sectional view.

FIG. 4 sequentially shows a part of the process in the second embodiment of the present invention for manufacturing a MOS transistor,
(A) (b) is front sectional drawing, (c) is a top view of the state of (b).

FIG. 5 is a front sectional view of a MOS transistor manufactured according to a third embodiment of the present invention.

FIG. 6 shows a MOS transistor manufactured according to a fourth embodiment of the present invention, in which (a) is a front sectional view and (b) is a plan view.

FIG. 7 is a side sectional view of a MOS transistor manufactured according to a conventional example of the present invention.

[Explanation of symbols]

21 Si substrate 23 Impurity 24 Impurity layer 25 Oxygen 26 SiO ₂ layer 31 Columnar portion 33 Polycrystalline Si layer 33a Polycrystalline Si layer 33b Polycrystalline Si layer 33c Polycrystalline Si layer

Claims (3)

(57) [Claims] 1. A semiconductor substrate comprising a first gate electrode which is in contact with each other in a depth direction of a semiconductor substrate and which is embedded in a relatively deep position and a first gate insulating layer which is embedded in a relatively shallow position. forming by ion implantation into the substrate, it passes through the first gate electrode on among the semiconductor body
A step of deleting said semiconductor body to a depth of said first gate insulating layer while leaving the columnar portion Ru extends, forming a second gate insulating layer on the exposed surface of the columnar portion, the columnar portion Forming a second gate electrode in contact with the second gate insulating layer on at least two surfaces of the portion on the first gate electrode. Method. 2. The impurity layer formed by ion implantation of impurities into the semiconductor substrate is used as the first gate electrode, and the semiconductor oxide layer formed by ion implantation of oxygen into the semiconductor substrate is used as the gate insulation. 2. The method for manufacturing a field effect transistor according to claim 1, wherein the layer is a layer. 3. The electric field according to claim 1, further comprising the step of separating at least one portion of the second gate electrode facing the surface from another portion facing the surface. Effect transistor manufacturing method.