JP3397944B2 - Display device driver circuit and display device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device driver circuit and a display device.

[0002]

2. Description of the Related Art In recent years, thin film transistors (TFTs)
Active Matrix Liquid Crystal Display (LCD; Liquid Crystal Displ) using Film Transistor
ay) is attracting attention as a display device with high image quality.

Dot matrix LCDs for displaying dots (dots) arranged in a matrix include a simple matrix system and an active matrix system. The simple matrix method is a method in which the liquid crystal of each pixel cell arranged in a matrix is directly driven from the outside in synchronization with a scanning signal, and a pixel section (liquid crystal panel) which is a display section of the LCD is composed only of electrodes and liquid crystal. Has been done. Therefore, when the number of scanning lines is increased, the driving time (duty) assigned to one pixel cell is reduced, and there is a drawback that the contrast is lowered.

On the other hand, in the active matrix system, a pixel drive element (active element, switch element, pixel control element) and a signal storage element (pixel capacitance) are integrated in each pixel cell arranged in a matrix, and each pixel cell is integrated. This is a method of quasi-statically driving the liquid crystal by performing a kind of memory operation. That is, the pixel driving element functions as a switch that is switched between the on / off state according to the scanning signal. Then, the video signal (data signal, display signal) sent from the outside is transferred to a wiring (data line) inside the LCD via a drive circuit (data driver circuit). The transferred video signal (more accurately, the image signal separated from the video signal) is transmitted to the pixel cell via the pixel drive element in the ON state, and the liquid crystal is driven. After that, when the pixel driving element is turned off, the video signal applied to the pixel cell is stored in the signal storage element in a charged state, and the liquid crystal is continuously driven until the pixel driving element is turned on next time. Therefore, even if the number of scanning lines increases and the driving time assigned to one pixel cell decreases, the driving of the liquid crystal is not affected and the contrast does not deteriorate. Therefore, according to the active matrix system, it is possible to display a much higher image quality than the simple matrix system.

The active matrix system is roughly classified into a transistor type (three-terminal type) and a diode type (two-terminal type) depending on the pixel driving element. Although the transistor type is more difficult to manufacture than the diode type, it is easy to increase the contrast and resolution and has a characteristic that a high quality LCD comparable to a CRT can be realized. A TFT is generally used as the transistor type pixel driving element.

FIG. 9 is a block circuit diagram of a conventional active matrix type LCD. The active matrix LCD 50 is composed of a drive circuit section 51 and a liquid crystal display module 52. The video signal input from the outside is separated into a sync signal and an image signal by the sync separation circuit 53 of the drive circuit unit 51, and the sync signal is output to the timing controller 54 and the image signal is output to the video signal processing circuit 55. . Timing controller 5
Reference numeral 4 denotes clock signals CK1 and CK2 necessary for driving the liquid crystal display module 52 based on the input synchronizing signal.
, Start pulse signals SP1, SP2, etc. are generated and output to the liquid crystal display module 52 via the drive circuit 56.

The image signal is input to the video signal processing circuit 55. The video signal processing circuit 55 receives a timing signal from the timing controller 54 and converts the input image signal based on the timing signal into two image signals Vd1 and Vd2 having different polarities. As shown in FIG. 11, the image signals Vd1 and Vd2 are generated as signals whose polarities are inverted around the video center voltage Vc. The generated image signal Vd1 is output to the liquid crystal display module 52 via the drive circuit 57, and the generated image signal Vd2 is output to the liquid crystal display module 52 via the drive circuit 58.

The power supply circuit 59 receives an external power supply,
Operating power is supplied to each of the circuits 53 to 58 in the drive circuit unit 51 and the liquid crystal display module 52. As shown in FIG. 10, the liquid crystal display module 52 includes a pixel cell array 6 including pixel cells GC arranged two-dimensionally.
0 is provided. The pixel cell array 60 is provided with scanning lines (gate wirings) G1 to Gn and data lines (drain wirings) D1, D2, D3 ... Which are orthogonal to each other. Each pixel cell GC is connected to the intersections of the scanning lines G1 to Gn and the data lines D1, D2, D3 ...

Each pixel cell GC has a T as a pixel driving element.
It is composed of an FT (for example, N-channel TFT) 102, a liquid crystal cell LC as a signal storage element, and an auxiliary capacitance CS.

The scanning lines G1 to Gn are connected to the gate driver 61. The data lines D1 and D3 are connected to a first sample-hold circuit 63 that constitutes a first data driver 62, and the data line D2 is connected to a sample-hold circuit 65 that constitutes a second data driver 64. Has been done.

The image signal Vd1 input to the liquid crystal display module 52 is input from the amplifier 66 to the first sample and hold circuit 63 via the video line VL1. First
The sample-and-hold circuit 63 of the first shift register 67 uses the clock signal CK1 and the start pulse signal.
The image signal Vd1 is sampled and held by being sequentially controlled based on SP1. Then, the first sample and hold circuit 63 outputs the held image signal Vd1 to the data lines D1 and D1.
Supply to the pixel cell GC connected to 3.

On the other hand, the image signal Vd2 is input from the amplifier 68 to the second sample and hold circuit 65 via the video line VL2. Second sample and hold circuit 65
Is a clock signal CK generated by the second shift register 69.
2 and the start pulse signal SP2, the image signal Vd2 is sampled and held. Then, the second sample and hold circuit 65 supplies the held image signal Vd2 to the pixel cell GC connected to the data line D2.

At this time, since the image signals Vd1 and Vd2 are signals having different polarities, the image signals Vd1 and Vd2 having different polarities are applied to the adjacent pixel cells GC. For example, in one horizontal period, when the image signal Vd1 having a voltage higher (plus) than the video center voltage Vc is applied to the pixel cells GC connected to the data lines D1 and D3, the pixel cells GC are connected to the data line D2 and are adjacent to each other. An image signal Vd2 having a voltage (minus) lower than the video center voltage Vc is applied to the pixel cell GC. And in the next one horizontal period,
The negative image signal Vd1 is applied to the pixel cell GC connected to the data lines D1 and D3, and the positive image signal Vd2 is applied to the pixel cell GC connected to the data line D2. The liquid crystal cell LC of each pixel cell GC has a transmittance according to the voltage of the applied image signals Vd1 and Vd2, and an image is displayed.

As described above, the plus and minus image signals Vd1 and Vd2 are added to the adjacent pixel cells GC every horizontal period.
Are alternately applied to suppress flicker and prevent deterioration of the liquid crystal cell. A method of applying the image signals Vd1 and Vd2 having different polarities to the adjacent pixel cells GC is called a dot inversion driving method. By this dot inversion drive, the liquid crystal cell LC is AC-driven to suppress deterioration of performance.

[0015]

By the way, the image signal V
d1 and Vd2 are the video signal processing circuit 55 of the drive circuit unit 51.
Since it is generated by the above and supplied to the liquid crystal display module 52 via the drive circuits 57 and 58, respectively, one of the voltages of the image signals Vd1 and Vd2 may fluctuate or the phases may shift. When the voltages of the image signals Vd1 and Vd2 fluctuate, the liquid crystal cells LC have different transmittances depending on the voltages of the applied image signals Vd1 and Vd2, so that the adjacent pixel cells GC have different transmittances. The displayed image becomes uneven and the image quality deteriorates.

This problem becomes more serious as the liquid crystal display module 52 becomes larger. That is, as the liquid crystal display module 52 becomes larger, each video line VL
1, the wiring length of VL2 and each of the lines G1 to Gn, D1, D2, D3 ... Increases, and the wiring resistance and wiring capacitance increase. As a result, a large difference occurs in the delay times of the image signals Vd1 and Vd2 applied to the liquid crystal cell LC, causing a phase shift and a large voltage fluctuation.

Further, in the liquid crystal display module 52, the first and second data drivers 6 are provided on both sides of the pixel cell array 60.
Since 2 and 64 must be provided respectively,
There is a problem that the area occupied by the second data drivers 62 and 64 becomes large and the liquid crystal display module 52 becomes large.

The present invention has been made to solve the above problems and has the following objects. 1] To provide a driver circuit of a display device capable of generating an image signal with little phase shift and voltage fluctuation.

2) To provide a high quality display device.

[0020]

According to a first aspect of the present invention, there is provided a first image signal whose polarity is inverted with respect to a predetermined voltage every horizontal period or every frame, and the image signal. In a driver circuit of a display device in which a pixel cell driven based on a second image signal whose polarity is inverted with respect to the voltage is formed, the first image signal is input and the first image signal is input. A generation circuit that includes a subtraction circuit that generates a second image signal based on
From the voltage twice the predetermined voltage to the first image signal.
A table adapted to subtract the signal to generate the second image signal.
The gist is that the driver circuit of the display device is provided.

[0021]

According to a second aspect of the present invention, the pixel cells are connected to a plurality of data lines provided in a pixel cell array composed of pixel cells arranged two-dimensionally, and display is made in each pixel cell array through the data lines. In a driver circuit of a display device for applying a voltage according to an image, a first video line for transmitting a first image signal for displaying the image and a first image signal with respect to a video center voltage are provided. A second video line for transmitting a second image signal of opposite polarity, and a plurality of data lines respectively connected to the first and second video lines alternately, the first, The first transmitted to the second video line,
A plurality of sample and hold circuits that sample and hold a second image signal; a shift register that inputs a clock signal and a start pulse signal and sequentially controls the sample and hold circuits based on both signals; The second image signal is generated by subtracting the first image signal transmitted to the first video line from the voltage connected to the second video line and inputting twice the video center voltage. And a driver circuit for the display device, which comprises a subtraction circuit for transmitting to the second video line.

[0023]

[0024]

[0025]

[0026]

The invention described in claim 3 is the invention according to claim 1 or 2.
In the driver circuit of the display device described in the above 1, the gist is that the driver circuit of the display device is configured by a thin film transistor having a polycrystalline silicon film as an active layer.

[0028]

Therefore, according to the invention described in claim 1,
The generation circuit generates a first image from a voltage twice the predetermined voltage.
The image signal is subtracted to generate a second image signal whose polarity is inverted with respect to the predetermined voltage.

[0030]

According to the second aspect of the invention, the first video signal for displaying an image is transmitted to the first video line, and the first video signal is transmitted to the second video line with respect to the video center voltage. A second image signal having a polarity opposite to that of the image signal is transmitted. The sample and hold circuit is connected to each of the plurality of data lines of the pixel cell array, is alternately connected to the first and second video lines, and is transmitted to the connected video lines. Image signal is sampled and held. The shift register receives a clock signal and a start pulse signal and sequentially controls the sample and hold circuit based on both signals. The subtraction circuit is connected to the first and second video lines, inputs a voltage twice the video center voltage, subtracts the first image signal transmitted to the first video line from the voltage, and outputs the second image signal. Image signal is generated and transmitted to the second video line.

[0032]

[0033]

[0034]

In the invention described in claim 3 , the thin film transistor having a polycrystalline silicon film as an active layer has high mobility and high driving ability. Therefore, the driver circuit of the display device can have high performance, and the display device can have high image quality.

[0036]

[0037]

DETAILED DESCRIPTION OF THE INVENTION

(First Embodiment) A first embodiment of the present invention will be described below with reference to FIGS.

FIG. 5 is a block circuit diagram of the active matrix type LCD of this embodiment. The active matrix LCD 1 is composed of a drive circuit unit 2 and a liquid crystal display module 3.

The drive circuit section 2 is provided with a sync separation circuit 4, a timing controller 5, a video signal processing circuit 6, a power supply circuit 7 and drive circuits 8 and 9. The sync separation circuit 4 separates a video signal input from the outside into an image signal and a sync signal. Then, the sync separation circuit 4
The separated image signal is output to the video signal processing circuit 6 and the synchronization signal is output to the timing controller 5.

The timing controller 5 inputs a synchronizing signal, generates timing signals such as a clock signal CK and a start pulse signal SP necessary for driving the LCD on the basis of the synchronizing signal, and drives the liquid crystal through the drive circuit 8. The output is made to the display module 3.

The video signal processing circuit 6 includes a sync separation circuit 4
The image signal is input from and the image signal is amplified. The video signal processing circuit 6 also receives the timing signal output from the timing controller 5. And
The video signal processing circuit 6 outputs the amplified image signal to the video center voltage V based on the input timing signal.
An image signal Vd1 whose polarity is inverted every one horizontal period with respect to c is generated. Then, the video signal processing circuit 6 outputs the generated image signal Vd1 to the liquid crystal display module 3 via the drive circuit 9.

The power supply circuit 7 receives an external power supply, generates the voltages required for the circuits 4 to 6, 8 and 9 in the drive circuit section 2 and the liquid crystal display module 3, and supplies the respective circuits 4 to 6 and 8. , 9 and the liquid crystal display module 3. In addition, the power supply circuit 7
Is the voltage 2Vc which is twice the video center voltage Vc.
Is generated and output to the liquid crystal display module 3.

The liquid crystal display module 3 is a capacitive load input, and the drive circuits 8 and 9 input the respective input signals to the signals (voltage) necessary for driving the liquid crystal display module 3.
It is designed to be converted to and output.

1 and 2 show a liquid crystal display module 3
3 is a block circuit diagram of FIG. The liquid crystal display module 3 has
A pixel cell array 11, a gate driver circuit 12 and a data driver circuit 13 are provided.

In the pixel cell array (pixel portion) 11, each scanning line (gate wiring) G1 to Gn and each data line (drain wiring)
D1 to D2m are arranged. Note that n and m are integers. Each scanning line Gn and each data line D2m are orthogonal to each other, and a pixel GC is provided in the orthogonal portion. And
Each scanning line Gn is connected to the gate driver circuit 12, and a scanning signal (gate signal) is applied. Each data line D2m is connected to a data driver (drain driver) circuit 13 so that an image signal is applied. The peripheral drive circuit unit 101 is configured by these driver circuits 12 and 13. The liquid crystal display module 3 in which at least one of the driver circuits 12 and 13 is formed on the same substrate as the pixel cell array 11 is generally called a driver integrated type (driver built-in type) LCD. In the driver integrated LCD, the wiring length of each of the lines G1 to Gn and D1 to D2m is shortened, so that the wiring resistance and the wiring capacitance can be reduced and the image quality can be improved.

The pixel cell GC is a TF as a pixel driving element.
It is composed of T102, a liquid crystal cell LC, and a storage capacitor CS. The gate of the TFT 102 is connected to the scanning line Gn, and the drain of the TFT 102 is connected to the data line D2m. The source of the TFT 102 is the liquid crystal cell LC.
The display electrode (pixel electrode) and the auxiliary capacitance (storage capacitance or additional capacitance) CS are connected. The liquid crystal cell LC and the auxiliary capacitance CS form the signal storage element. The voltage Vcom is applied to the common electrode of the liquid crystal cell LC (the electrode on the opposite side of the display electrode). On the other hand, in the auxiliary capacitance CS, a constant voltage VR is applied to the electrode opposite to the electrode connected to the source of the TFT 102.
The common electrode of the liquid crystal cell LC is literally a common electrode to all the pixel cells GC. An electrostatic capacitance is formed between the display electrode and the common electrode of the liquid crystal cell LC. In the auxiliary capacitance CS, the TFT1
The electrode on the opposite side of the electrode connected to the source of 02 is
It may be connected to the adjacent scanning line.

In the pixel cell GC configured as described above, when the scanning line Gn is set to a positive voltage and a positive voltage is applied to the gate of the TFT 102, the TFT 102 is turned on. Then, with the image signal applied to the data line D2m, the liquid crystal cell L
The electrostatic capacity of C and the auxiliary capacity CS are charged. Conversely,
When the scanning line Gn is set to a negative voltage and a negative voltage is applied to the gate of the TFT 102, the TFT 102 is turned off, and the voltage applied to the data line D2m at that time is changed by the electrostatic capacity of the liquid crystal cell LC and the auxiliary capacity CS. Retained. In this way, the image signal to be written to the pixel cell GC is transferred to the data line D2.
By controlling the voltage of the scanning line Gn by giving it to m, an arbitrary image signal can be held in the pixel cell GC. The transmittance of the liquid crystal cell LC changes according to the image signal held by the pixel cell GC, and an image is displayed.

Here, the write characteristics and the retention characteristics are important as the characteristics of the pixel cell GC. What is required for the writing characteristic is that the signal storage element (the liquid crystal cell L) is formed within a unit time determined from the specifications of the pixel cell array 11.
The point is whether or not a desired image signal voltage can be sufficiently written to C and the auxiliary capacitance CS.
Further, what is required of the holding characteristic is whether or not the image signal voltage once written in the signal storage element can be held for a required time.

The auxiliary capacitance CS is provided in order to increase the electrostatic capacitance of the signal storage element and improve the writing characteristic and the holding characteristic. That is, the liquid crystal cell L
Due to the structure of C, there is a limit to the increase in capacitance. Therefore, the auxiliary capacitance CS compensates for the shortage of the electrostatic capacitance of the liquid crystal cell LC.

The gate driver circuit 12 includes the drive circuit section 2
Timing signals and drive voltages are input from the drive circuit 8 and the power supply circuit 7, respectively, and scanning signals (gate signals) are applied to the scanning lines G1 to Gn based on the timing signals.

The data driver circuit 13 comprises sample and hold circuits SH1 to SH2m and a shift register SR. The sample and hold circuits SH1 to SH2m are connected to the data lines D1 to D2m, respectively. The odd-numbered sample-hold circuits SH1, SH3, to SH2m-1 are connected to the video line VL1, and the even-numbered sample-hold circuits SH2, SH4, to SH2m are connected to the video line VL2.

The image signal Vd1 from the drive circuit section 2 is transmitted to the video line VL1 via the amplifier AMP.
The video line VL1 is connected to the video line VL2 via the subtraction circuit 14.

The subtraction circuit 14 is a known circuit composed of an operational amplifier and a resistor, and is a voltage 2Vc which is twice the video center voltage Vc from the power supply circuit 7 of the drive circuit unit 2.
You are typing. Then, the subtraction circuit 14 has a voltage of 2Vc.
To subtract the image signal Vd1 transmitted to the video line VL1 to generate an image signal Vd2. As shown in FIG. 4, since the polarity of the image signal Vd1 is inverted around the video center voltage Vc, the image signal Vd2 generated by the subtraction circuit 14 is the same as the image signal Vd1. Is a signal whose polarity is inverted with respect to. Further, the image signal Vd2 becomes a signal that is 180 degrees out of phase with the image signal Vd1 (the polarity is inverted). The image signal Vd1 is supplied to the odd-numbered sample / hold circuits SH1, SH3, to SH2m-1 via the video line VL1, and the image signal Vd2 is supplied to the even-numbered sample / hold circuits SH2, SH2, via the video line VL2. It is supplied to SH4, ~ SH2m.

The shift register SR receives the clock signal CK and the start pulse signal SP from the timing controller 5 of the drive circuit section 2. And the shift register SR
Is the input clock signal CK and start pulse signal
Operates based on SP and sample and hold circuits SH1 ~
It is designed to control the SH2m sequentially.

As shown in FIG. 3, the sample and hold circuit SH1 includes capacitors C1 and C2, an operational amplifier OP, analog switches SW1 to SW6, a constant current power supply 15 and a TF.
It is composed of a T (for example, N-channel TFT) 103. One ends of the capacitors C1 and C2 are connected to the video line VL1 via the analog switches SW1 and SW2.

The analog switches SW1 and SW2 are switches for sampling, and are alternately on / off controlled by the shift register SR every horizontal period. That is, the shift register SR controls the analog switch SW1 to be turned on and the analog switch SW2 to be turned off in a certain one horizontal period. Then, the image signal Vd1 is output to the analog switch.
It is held in the capacitor C1 via SW1.

In the next one horizontal period, the shift register SR
Controls the analog switch SW1 to be off and the analog switch SW2 to be on. Then, the image signal Vd1 is held in the capacitor C2 via the analog switch SW2. The polarity of the image signal Vd1 is inverted with respect to the video center voltage Vc every horizontal period. Therefore, the image signals Vd1 having opposite polarities are held in the capacitors C1 and C2. For example, the video center voltage Vc
On the other hand, the positive image signal Vd1 is applied to the capacitor C1 and the negative image signal Vd1 is applied to the video center voltage Vc.
Are held in the capacitor C2. With this configuration, the charging / discharging time of the capacitor with respect to the image signal Vd1 is shortened to increase the speed.

The capacitors C1 and C2 are connected to the non-inverting input terminal of the operational amplifier OP via the analog switches SW3 and SW4. The analog switches SW3 and SW4 are switches for transmitting the image signal Vd1 held in the capacitors C1 and C2 to the operational amplifier OP, and are on / off controlled by the write signal generated by the timing controller 5. Then, the image signal Vd1 sampled in one horizontal period and held in the capacitors C1 and C2
Are alternately output to the operational amplifier OP.

The operational amplifier OP is an output buffer amplifier, and the image signal Vd1 is input to its non-inverting input terminal. The inverting input terminal of the operational amplifier OP is connected to the drain of the MOS transistor (for example, N-channel MOS transistor) TR, and the output terminal is connected to the gate of the MOS transistor TR. The source of the MOS transistor TR is connected to the low potential side power source Vss (0 V in this embodiment), and the drain is connected to the high potential side power source V through the constant current power source 15.
Connected to _DD . The drain of the MOS transistor TR is connected to the pixel cell GC via the data cell line D1.

Further, both input terminals of the operational amplifier OP are connected to the high potential side power source V _DD through the analog switches SW5 and SW6, respectively. The analog switches SW5 and SW6 are
The high-potential-side power supply V _DD is input to both input terminals of the operational amplifier OP to reset the output terminal of the operational amplifier OP when not related to display.

The even-numbered sample and hold circuit SH
The configuration of 2 to SH2m is the same as the sample and hold circuit SH1. The sample and hold circuits SH2 to SH2m are connected to the video line VL2 and input the image signal Vd2, as described above. And the sample and hold circuit SH2
Is controlled by the shift register SR, samples the input image signal Vd2, and holds the sampled image signal Vd2. And the sample and hold circuit SH
2 to SH2m outputs the held image signal Vd2 to the data line D2 to
It is designed to be transmitted to D2m.

In addition, odd-numbered sample and hold circuits
The configurations and connections of SH3 to SH2m-1 are the same as those of the sample and hold circuit SH1, and therefore their explanations are omitted. Next, the operation of the image display device 1 configured as described above will be described.

The image signal Vd1 generated by the video signal processing circuit 6 based on the input video signal is output to the liquid crystal display module 3 via the drive circuit 9.
The image signal Vd1 input to the liquid crystal display module 3 is transmitted to the video line VL1 via the amplifier AMP of the data driver circuit 13. Further, the image signal Vd1 is applied to the subtraction circuit 1
4 is input. The subtraction circuit 14 subtracts the image signal Vd1 from the voltage of 2Vc, which is twice the video center voltage Vc input from the power supply circuit 7 of the drive circuit unit 2, and transmits the subtracted result to the video line VL2 as the image signal Vd2. .

Since the generated image signal Vd2 does not pass through the conventional drive circuit 58, there is no voltage fluctuation with respect to the image signal Vd1. Odd-numbered sample and hold circuit SH
1 to SH2m-1 are controlled by the shift register SR, the image signal Vd1 transmitted to the video line VL1 is input, and the image signal Vd1 is sampled and held. The even-numbered sample and hold circuits SH2 to SH2m are shift registers.
The image signal Vd2 controlled by SR and transmitted to the video line VL2 is input, and the image signal Vd2 is sampled and held.

The sample and hold circuits SH1 to SH2m transfer the voltage of the held image signal Vd1 or image signal Vd2 to each data line D1 to D2m. That is, the voltage of the image signal Vd1 is transmitted to the odd-numbered data lines D1 to D2m-1, and the voltage of the image signal Vd2 is transmitted to the even-numbered data lines D2 to D2m. Then, the voltage transmitted to each data line D1 to D2m is
The voltage is applied to each pixel cell GC connected to the scanning line selected by the gate driver circuit 12, for example, the scanning line G1. Each pixel cell GC has a transmittance corresponding to the applied voltage, and an image is displayed.

At this time, the image signal Vd2 is a signal obtained by subtracting the image signal Vd1 from the voltage 2Vc which is twice the video center voltage Vc. Therefore, the image signal Vd1 and the image signal Vd2 are 180 degrees out of phase with each other. That is, when the image signal Vd1 is positive with respect to the video center voltage Vc, the image signal Vd2 is
It is negative with respect to c and has the opposite polarity. Then, the sampled voltages of the image signal Vd1 and the image signal Vd2, that is, the voltages of opposite polarities are alternately applied to the adjacent pixel cells GC connected to the same scanning line, and the dot inversion drive is performed.

As described above, in the active matrix type LCD 1 of this embodiment, only the video signal Vd1 whose polarity is inverted every horizontal period with respect to the video center voltage Vc in the video signal processing circuit 6 of the drive circuit unit 2 is used. Is generated and output to the liquid crystal display module 3 via the drive circuit 9. The power supply circuit 7 has a video center voltage Vc.
The voltage 2Vc, which is twice as high as the above voltage, is generated and output to the liquid crystal display module 3.

The data driver circuit 13 of the liquid crystal display module 3 is provided with a subtraction circuit 14, and the subtraction circuit 1
The video line VL2 is connected via 4 to the video line VL1. The image signal Vd1 input from the drive circuit unit 2 is transmitted to the video line VL1. The subtraction circuit 14
Input the voltage 2Vc from the drive circuit unit 2 and input the voltage 2Vc
The image signal Vd1 is subtracted from c to obtain the video center voltage V
A voltage having a polarity opposite to that of the image signal Vd1 is generated with respect to c, and the voltage is transmitted to the video line VL2 as the image signal Vd2.

The sample and hold circuits SH1 to SH2m are alternately connected to the video lines VL1 and VL2, and sample and hold the voltages of the image signals Vd1 and Vd2 transmitted to the video lines VL1 and VL2, respectively. Then, the sample and hold circuits SH1 to SH2m are connected to the held image signal Vd.
The voltages of 1 and Vd2 are applied to the adjacent pixel cells GC via the data lines D1 to D2m so that dot inversion drive is performed. As a result, according to this embodiment, the following actions and effects can be obtained.

Since the drive circuit unit 2 only needs to be provided with the circuits 6 and 9 for generating and transmitting only the image signal Vd1, the drive circuit unit 2 is smaller than the drive circuit unit 51 of the conventional image display device 50. can do.

Since the circuit for generating the conventional clock signal CK2 and start pulse signal SP2 is also unnecessary, the drive circuit unit 2 can be made smaller than that of the drive circuit unit 51.

Since the data driver circuit 13 may be provided only on one side of the pixel cell array 11 of the liquid crystal display module 3, the liquid crystal display module 3 can be downsized. Each video line VL1, VL2 and each line G1-Gn, D1, D2,
Even when the wiring length of D3 ... Is long and the wiring resistance and wiring capacitance are large, the respective image signals Vd1 and Vd2 applied to the liquid crystal cell LC.
It is possible to avoid the phase shift and the voltage fluctuation. Therefore, even when the liquid crystal display module 3 is upsized, it is possible to suppress the unevenness of the displayed image and improve the image quality. (Second Embodiment) A second embodiment of the present invention will be described below with reference to FIGS.

In this embodiment, the same components as those in the first embodiment are designated by the same reference numerals, and detailed description thereof will be omitted. FIG. 6 is a block circuit diagram of the liquid crystal display module 20 of this embodiment.

The liquid crystal display module 20 is connected to the drive circuit unit 2 shown in FIG. 5, and receives the clock signal CK, the start pulse signal SP, the image signal Vd1, the voltage 2Vc, etc. from the drive circuit unit 2.

The liquid crystal display module 20 is provided with a data driver circuit 21. Note that the pixel cell array 11 and the gate driver circuit 12 provided in the liquid crystal display module 20 are the same as those in the first embodiment, so description thereof will be omitted.

The data driver circuit 21 includes a sample
A hold circuit 22 and an inverted image signal generation circuit (hereinafter, simply referred to as an inversion circuit) 23 are provided. The sample hold circuit 22 and the inverting circuit 23 are provided for the respective data lines D1 to D2m of the pixel cell array 11,
It is connected to each of the data lines D1 to D2m. Also,
Each sample and hold circuit 22 is connected to one video line VL via an inverting circuit 23. In the video line VL, the image signal Vd1 generated by the video signal processing circuit 6 of the drive circuit unit 2 shown in FIG.
Supplied via P.

As shown in FIG. 7, the inverting circuit 23 is composed of a subtracting circuit 23a and a switch 23b as a switching circuit. The sampling analog switches SW1 and SW2 forming the sample-hold circuit 22 are commonly connected and also connected to the switch 23b. The configuration of the sample and hold circuit 22 is the same as that of the sample and hold circuits SH1 to SH2m of the first embodiment, and the description thereof will be omitted.

The switch 23b is a two-pole switch having a terminal A, a terminal B and a common terminal C, and the common terminal C is connected to the sample and hold circuit 22. The terminal A of the switch 23b is connected to the video line VL via the subtraction circuit 23a, and the terminal B is directly connected to the video line VL.
It is connected to VL. The subtraction circuit 23a receives the voltage 2Vc which is twice the video center voltage Vc. Then, the subtraction circuit 23a generates a voltage by subtracting the image signal Vd1 transmitted to the video line VL from the voltage 2Vc, and the generated voltage is used as the image signal Vd2 in the switch 2
Output to 3b.

The common terminal C of the switch 23b is connected to the terminals A and B every other data line D1 to D2m. That is, the common terminal C of the switch 23b connected to the data line D1 is connected to the terminal B, and the common terminal C of the switch 23b connected to the data line D2 is connected to the terminal A. Then, the switch 23b connected to the data line D3
The common terminal C of is connected to the terminal B. Therefore, the sample and hold circuit 22 is connected to the data lines D1, D3, ... D2m-1.
The voltage of the image signal Vd1 sampled and held by is transmitted, and the voltage of the image signal Vd2 sampled and held by the sample and hold circuit 22 is transmitted to the data lines D2, D4, ... D2m. There is.

That is, the voltage of the image signal Vd1 and the voltage of the image signal Vd2 are alternately transmitted to the data lines D1 to D2m by the sample and hold circuit 22. Then, the sampled voltages of the image signal Vd1 and the image signal Vd2, that is, the voltages of opposite polarities are alternately applied to the adjacent pixel cells GC connected to the same scanning line, and the dot inversion drive is performed.

Further, the liquid crystal display module 20 can be applied to other than the dot inversion drive. That is, the common terminal C of all the switches 23b of the generation circuit 23 is connected to the terminal B.
Connect to. Then, the voltage of the image signal Vd1 sampled and held by the sample and hold circuit 22 is transmitted to each of the data lines D1 to D2m. The gate driver circuit 12 sequentially selects the scanning lines G1 to Gn for each horizontal period. Since the polarity of the image signal Vd1 is inverted every horizontal period, it is possible to perform the gate inversion drive in which the voltage of the image signal Vd1 whose polarity is inverted is applied to each of the scanning lines G1 to Gn in the pixel cell GC. .

As described above, in this embodiment, each data line is
The sample and hold circuit 22 connected to D1 to D2m is connected to the video line VL via the switch 23b and the subtraction circuit 23a.
Connected to. Then, the sample and hold circuit 22
In each of the data lines D1 to D2m, an image signal generated by subtracting the image signal Vd1 from the voltage of the image signal Vd1 alternately transmitted to the video line and the voltage 2Vc which is twice the video center voltage Vc in the subtraction circuit 23a. The voltage of Vd2 is sampled and held. The held voltages of the image signals Vd1 and Vd2 are applied to the pixel cells GC connected to the data lines D1 to D2m so that dot inversion drive is performed.

As a result, according to this embodiment, it is possible to obtain the same operation and effect as the first embodiment. In addition, by changing the connection of the switch 23b, it is possible to support not only the dot inversion drive but also the gate inversion drive.

By the way, as the TFT 102, a TFT using a polycrystalline silicon film formed on a transparent insulating substrate as an active layer (hereinafter referred to as a polycrystalline silicon TFT) is under development.

The polycrystalline silicon TFT has an advantage of higher mobility and higher driving capability than a thin film transistor using an amorphous silicon film as an active layer (hereinafter referred to as an amorphous silicon TFT). Therefore, polycrystalline silicon T
The FT can be used not only as a pixel driving element but also as an element forming a logic circuit. Therefore, if the polycrystalline silicon TFT is used, not only the pixel cell array 11 but also the peripheral drive circuit section 10 arranged in the periphery thereof is used.
1 (gate driver circuit 12, data driver circuit 1
A driver integrated LCD can be obtained by integrating up to 3, 21) on the same substrate. That is, each M that constitutes an internal element of each driver circuit 12, 13, 21
The OS transistor is formed by a polycrystalline silicon TFT.
Then, the polycrystalline silicon TFT 102 as a pixel driving element arranged in the pixel cell array 11 and the polycrystalline silicon TFT 1 constituting each of the driver circuits 12, 13 and 21.
03 is formed in the same process.

Further, since the polycrystalline silicon TFT has large mobility and high driving ability, the polycrystalline silicon TFT 103
If each driver circuit 12, 13, 21 is configured by the above, each driver circuit 12, 13, 21 can have high performance. Then, each driver circuit 12, 13, 21
If the performance becomes higher, LCD (liquid crystal display module 3, 2
The image quality of 0) can be improved.

FIG. 8 shows a planar type polycrystalline silicon TF.
1 shows a schematic cross section of a liquid crystal display module 3 or 20 of the present embodiment having a driver-integrated and transmissive configuration using T. FIG. 8A shows a partial schematic cross section of the pixel cell array 11.
FIG. 8B shows the pixel cell array 11 and each driver circuit 1.
2 (c) shows a schematic cross section of a wiring portion between the driver circuits 12, 13, 21 and FIG. 8 (c) shows a schematic cross section of each driver circuit 12, 13, 21.

As shown in FIG. 8A, a liquid crystal layer 203 filled with liquid crystal is formed between the transparent insulating substrates 201 and 202 facing each other. The transparent insulating substrate 201 is provided with the display electrode 204 of the liquid crystal cell LC, and the transparent insulating substrate 202 is provided with the common electrode 205 of the liquid crystal cell LC. The electrodes 204 and 205 face each other with the liquid crystal layer 203 interposed therebetween. ing.

Liquid crystal layer 203 in transparent insulating substrate 201
A polycrystalline silicon film 206, which becomes an active layer of the polycrystalline silicon TFT 102, is formed on the side surface. A gate insulating film 207 is formed on the polycrystalline silicon film 206. A gate electrode 208 forming the scanning line Gn is formed on the gate insulating film 207. The polycrystalline silicon film 206 has a drain region 209 and a source region 21.
0 is formed to form the polycrystalline silicon TFT 102.

Polycrystalline silicon T is formed on the transparent insulating substrate 201 at a portion adjacent to the polycrystalline silicon TFT 102.
The auxiliary capacitance CS is formed in the same step at the same time when the FT 102 is formed. The storage electrode 211 of the auxiliary capacitance CS is formed on the polycrystalline silicon film 206, and
102 is connected to the source region 210. A dielectric film 212 is formed on the storage electrode 211, and the dielectric film 21 is formed.
A counter electrode 213 of the auxiliary capacitance CS is formed on the second electrode 2. The dielectric film 212 is on the extension of the gate insulating film 207 and has the same structure as the gate insulating film 207 and is formed in the same step. Further, the counter electrode 213 is the gate electrode 208.
Are formed in the same process with the same structure as the above. Counter electrode 213
An insulating film 219 is formed on the side wall of the gate electrode 208, and an insulating film 214 is formed on the counter electrode 213 and the gate electrode 208.

An interlayer insulating film 215 is formed on the entire surfaces of the polycrystalline silicon TFT 102 and the auxiliary capacitor CS. The source region 210 and the drain region 209 are respectively connected to the source electrode 216 and the drain electrode 217 forming the data line D2m via the contact holes formed in the interlayer insulating film 215. Drain electrode 217
An insulating film 218 is formed on the entire surface of the device including the source electrode 216. The source electrode 216 is the insulating film 2
Display electrode 2 through the contact hole formed in 18
It is connected with 04. An aluminum alloy is generally used as the material of the drain electrode 217 and the source electrode 216, and ITO is generally used as the material of the display electrode 204.
(Indium Tin Oxide) is used. In addition, each electrode 20
A sputtering method is generally used for forming 4, 217 and 218.

As described above, the source region 210 and the display electrode 204 are connected to each other through the source electrode 216 in order to establish ohmic contact between the source region 210 and the display electrode 204. That is, the source electrode 2
When 16 is omitted, the source region 210 made of the polycrystalline silicon film 206 and the display electrode 204 made of ITO are directly connected. As a result, the source region 210 and the display electrode 20
Due to the heterojunction with No. 4, an energy gap is generated due to the band gap difference, and good ohmic contact cannot be obtained. If the ohmic contact between the source region 210 and the display electrode 204 is not established, the data line D2
The image signal applied to m cannot be written correctly in the pixel cell GC, and the image quality of the LCD is degraded.

As shown in FIG. 8B, the transparent insulating substrate 2
On 01, the scanning line Gn or the data line D2m is formed via the insulating film 215, and the insulating film 218 is formed on the entire surface of the device including the wirings Gn and Dn. Like the pixel cell array 11, a liquid crystal layer 203, a common electrode 205, and a transparent insulating substrate 202 are formed on the insulating film 218.

As shown in FIG. 8C, the transparent insulating substrate 2
The planar type polycrystalline silicon TFT 103 forming each of the driver circuits 12, 13 and 21 is formed on the surface of the liquid crystal display layer 01 on the liquid crystal layer 203 side. Polycrystalline silicon T
The FT 103 is formed in the same step as the polycrystalline silicon TFT 102 is formed. It should be noted that each member constituting the polycrystalline silicon TFT 103 is given the same reference numeral as the polycrystalline silicon TFT 102. An insulating film 218 is formed on the entire surface of the device including the polycrystalline silicon TFT 103. The pixel cell array 1 is formed on the insulating film 218.
Similar to 1, the liquid crystal layer 203, the common electrode 205, and the transparent insulating substrate 202 are formed.

By the way, each polycrystalline silicon TFT 10
The method of forming the polycrystalline silicon film 206 to be the active layers 2 and 103 is as follows. Method for directly forming polycrystalline silicon film 206; CVD
Method or PVD method is used. Atmospheric pressure CVD for the CVD method
Method, low pressure CVD method, plasma CVD method, photo-excited CVD method and the like. In addition, the PVD method includes a vapor deposition method and an EB (Electr
on Beam) evaporation method, MBE (Molecular Beam Epitaxy)
Method and sputtering method.

Among them, the reduced pressure CV utilizing the thermal decomposition of monosilane (SiH ₄ ) or disilane (Si ₂ H ₆ ).
The D method is general and the highest quality polycrystalline silicon film 2
06 can be formed. In the low-pressure CVD method, the processing temperature is amorphous at 550 ° C. or lower, and polycrystalline at 620 ° C. or higher.

Further, a plasma CVD method utilizing thermal decomposition of monosilane or disilane in plasma is also used. The processing temperature of the plasma CVD method is about 300 ° C. When hydrogen is added, the reaction is accelerated and an amorphous silicon film is formed. Then, when an inert gas (helium, neon, argon, krypton, xenon, radon) is added, plasma is excited and a polycrystalline silicon film is formed even at the same processing temperature.

A method of forming a polycrystalline silicon film 206 by polycrystallizing after forming an amorphous silicon film; a solid phase growth method or a melt recrystallization method is used. The solid phase growth method is
This is a method in which an amorphous silicon film is subjected to heat treatment at about 600 ° C. for a long time of about 20 hours to polycrystallize it in a solid state to obtain a polycrystalline silicon film.

In the melt recrystallization method, only the surface of the amorphous silicon film is melted for recrystallization, and the substrate temperature is set to 60.
This is a method of keeping the temperature below 0 ° C.
(Rapid Thermal Annealing) method. The laser annealing method is a method in which the surface of an amorphous silicon film is irradiated with a laser to be heated and melted. The RTA method is a method in which the surface of an amorphous silicon film is irradiated with lamp light to be heated and melted.

The conventional polycrystalline silicon TFT is formed by using a high temperature process of about 1000 ° C. (called a high temperature process). The high temperature process follows the LSI technology which has a sufficient technical accumulation for many years. Therefore, a polycrystalline silicon TFT formed by a high temperature process
(High temperature polycrystalline silicon TFT) has excellent device characteristics, reliability and reproducibility. However, since the high temperature process has a high process temperature, there is no choice but to use quartz glass for the transparent insulating substrate. The size of the transparent insulating substrate is limited because quartz glass becomes extremely expensive as it grows in size, and the size of quartz glass is limited at present. Therefore, the panel size of the liquid crystal display modules 3 and 20 commensurate with the cost is 3 inches or less, and although it can be sufficiently used for a viewfinder of a video camera or a liquid crystal projector, the panel size is too small for a direct view. Can not.

On the other hand, since an amorphous silicon TFT can be formed by using a low temperature process of 400 ° C. or lower, ordinary glass can be used for the transparent insulating substrate. Normal glass is about 1/10 the price of quartz glass and there are no restrictions on size, but LC
High heat resistant glass commercially available for D (for example, Corn in the United States)
ing Inc.'s "7059") has only a heat resistant temperature of about 600 ° C.

Therefore, a polycrystalline silicon TFT is used so that ordinary glass (high heat resistant glass) can be used for the transparent insulating substrate.
It is required to be formed using a low temperature process of about 600 ° C or less (called a low temperature process). A polycrystalline silicon TFT formed by a low temperature process is called a low temperature polycrystalline silicon TFT.

Therefore, in order to inexpensively provide an LCD (liquid crystal display module 3, 20) having a large panel size by using a high heat resistant glass for the transparent insulating substrate 201, a low temperature process (described above) is performed when the polycrystalline silicon film 206 is formed. As described above, the solid-phase growth method or the melt recrystallization method is used, and the manufacturing of the polycrystalline silicon TFTs 102 and 103 includes the formation of the gate insulating film 207 and the formation of the source region 210 and the drain region 209. A low-temperature process may be adopted for all the steps.

The present invention is not limited to the above embodiment, but may be carried out as follows. (1) In each of the above embodiments, the liquid crystal display module integrated with the driver circuit is embodied, but it may be embodied in the liquid crystal display module not integrated with the driver. Also,
It may be embodied in a liquid crystal display module using TAB and COG.

(2) In each of the above embodiments, the TFT-LC
Although embodied in D, MIM-LC using a diode
It may be embodied in a D, STN-LCD or the like. (3) In each of the above embodiments, the sample and hold circuits SH1 to SH2m, 22 may be implemented in other circuit configurations.

(4) In each of the above embodiments, the N-channel TFT is used as the TFT 102 constituting each pixel cell GC, but a P-channel TFT may be used. In addition, the MO that constitutes the sample and hold circuits SH1 to SH3
Although an N-channel MOS transistor is used as the S transistor TR, a P-channel MOS transistor may be used instead.

(5) In the second embodiment, the sample
The inverting circuit 23 is connected to the hold circuit 22, and the switch 23b of the inverting circuit 23 is switched to change the data lines D1 to D2.
Although the image signal Vd1 and the image signal Vd2 are alternately transmitted to m, the image signal Vd2 is provided without the switch 23b.
Alternatively, only the subtraction circuit 23a may be connected to the sample and hold circuit 22 connected to the data line for transmitting. With this configuration, although only dot inversion drive can be performed, the number of inversion circuits 23 can be reduced and the circuit area of the data driver circuit 21 can be reduced.

(6) The TFTs 102 and 103 are replaced with amorphous silicon TFTs instead of polycrystalline silicon TFTs. (7) The low temperature polycrystalline silicon TFTs 102 and 103 are replaced with the high temperature polycrystalline silicon TFTs 102 and 103.

(8) The TFTs 102 and 103 are replaced with TFTs having a structure other than the planar type (inverted planar type, staggered type, inverted staggered type, etc.). (9) The present invention is applied not to the liquid crystal display modules 3 and 20 having the transmissive structure but to the liquid crystal display module having the reflective structure.

[0110]

[0111]

[0112]

[0113]

【The invention's effect】

1] It is possible to provide a driver circuit of a display device capable of generating an image signal with little phase shift and voltage fluctuation.

2] It is possible to provide a high quality display device.

[Brief description of drawings]

FIG. 1 is a partial block circuit diagram of a liquid crystal display module of a first embodiment.

FIG. 2 is a block circuit diagram of the liquid crystal display module of the first embodiment.

FIG. 3 is a circuit diagram of a sample and hold circuit according to the first embodiment.

FIG. 4 is a waveform diagram of a video signal.

FIG. 5 is a block circuit diagram of an active matrix type LCD.

FIG. 6 is a partial block circuit diagram of a liquid crystal display module of a second embodiment.

FIG. 7 is a circuit diagram of a sample and hold circuit according to a second embodiment.

FIG. 8 is a schematic cross-sectional view of a liquid crystal display module.

FIG. 9 is a block circuit diagram of a conventional active matrix LCD.

FIG. 10 is a partial block circuit diagram of a conventional liquid crystal display module.

FIG. 11 is a waveform diagram of a conventional video signal.

[Explanation of symbols] 1 ... Active matrix LCD 2 ... Drive circuit 3 ... Liquid crystal display module as display device 4 ... Synchronous separation circuit 5 ... Timing controller 6 ... Video signal processing circuit 7 ... Power supply circuit 8 ... Drive circuit (for timing signal) 9 ... Drive circuit (for video signal) 11 ... Pixel cell array 12 ... Gate driver 13, 21 ... Data driver 14 ... Subtraction circuit as generation circuit 23 ... Inverted image signal generation circuit 23a ... Subtraction circuit as generation circuit 23b ... Switch as switching circuit 101 ... Peripheral drive circuit section 102, 103 ... Polycrystalline silicon TFT 206 ... Polycrystalline silicon film D1 to D2m… Data line SR ... Shift register SH1-SH2m, 22 ... Sample and hold circuit Vc ... Video center voltage 2Vc ... Voltage Vd1 ... (first) image signal Vd2 ... (second) image signal GC ... Pixel cell

─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-60-156095 (JP, A) JP-A-62-116924 (JP, A) JP-A-7-319432 (JP, A) JP-A-5- 313614 (JP, A) JP 64-16088 (JP, A) JP 3-153178 (JP, A) JP 5-328267 (JP, A) JP 6-348229 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) G09G 3/00-3/38 G02F 1/133 505-580

Claims (3)

(57) [Claims] 1. A first image signal, the polarity of which is inverted every horizontal period or every frame with respect to a predetermined voltage,
In the driver circuit of the display device in which a pixel cell driven based on the image signal and a second image signal whose polarity is inverted with respect to the voltage is formed, the first image signal is input, A generation circuit that includes a subtraction circuit that generates a second image signal based on the first image signal is provided, and the generation circuit has a voltage that is twice the predetermined voltage.
The second image signal is obtained by subtracting the first image signal from the voltage.
A driver circuit for a display device adapted to generate a signal. 2. A voltage corresponding to an image displayed on each pixel cell array is connected to a plurality of data lines provided in a pixel cell array composed of pixel cells arranged two-dimensionally. In the driver circuit of the display device, the first video line for transmitting the first image signal for displaying the image and the second video line having the opposite polarity to the first image signal with respect to the video center voltage are used. A second video line for transmitting an image signal and each of the plurality of data lines are connected to the first and second video lines alternately and are transmitted to the first and second video lines. A plurality of sample and hold circuits for sampling and holding the first and second image signals, a clock signal and a start pulse signal are inputted, and the sample A first image that is connected to the first and second video lines and that receives a voltage twice the video center voltage and that voltage is transmitted to the first video line. A driver circuit for a display device, comprising: a subtraction circuit that subtracts signals to generate a second image signal and transmits the second image signal to a second video line. 3. The driver circuit of the display device according to claim 1 , wherein the driver circuit of the display device is a thin film transistor having a polycrystalline silicon film as an active layer.