JP3399010B2 - Digital mobile phone demodulator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [0001] BACKGROUND OF THE INVENTION The present invention relates to a 1 / 4.pi.DQPSK
It relates to digital cellular phones, especially DPLL
1 symbol delay while maintaining clock extraction resolution
For demodulator of digital mobile phone that simplifies the configuration
Related. [0002] 2. Description of the Related Art A demodulator for a digital cellular phone of this kind.
, The phase of the phase-modulated digital input signal
After delaying the value by one symbol, compare this with the input phase value
Then, when the absolute value of the comparison result is equal to or more than 1 / 2π,
Therefore, supply a detection signal of 1 / 2π or more to the DPLL unit.
And demodulated symbol clock and demodulated data clock
The demodulated symbol clock and demodulated clock
To the demodulation section to obtain demodulated data.
are doing. In such a demodulator, one symbol is delayed.
Extension part is composed of D type flip-flop, for example
This flip-flop is a symbol
The number of stages corresponding to the resolution of clock extraction is required. Ma
Also, lower the clock frequency of the shift register to shift
By reducing the number of register stages, this shift register
When the one-symbol delay unit is configured, the clock extraction
The output resolution will be low. [0004] SUMMARY OF THE INVENTION The present invention
In particular, the problem in the DPLL section
One symbol delay without sacrificing lock extraction resolution
Digit that can simplify the configuration of the extension
To provide demodulators for mobile phones.
You. [0005] SUMMARY OF THE INVENTION The present invention provides a phase modulated signal.
One-symbol delay hand supplied with a digital input signal
Stage and the one-symbol delay meansThe phase value of the signal,
Detecting a phase difference from the phase value of the digital input signal
Phase difference detecting means,The phase from the phase difference detection means
A decoding unit for decoding the difference using a symbol clock;
Having. AlsoThe phase difference detecting meansThe position detected in
Detect the absolute value of the phase differenceAn absolute value detecting means;Said detected
Detection signal in the range of values whose absolute value is equal to or greater than 1 / 2π
Get1 / 2π or more detecting means,The above 1 / 2π detection
Based on the phase of the midpoint of the detection signal from the means.
Obtaining the symbol clock for phase demodulation for demodulation
Supplied to the decoding unitAnd a DPLL unit.
Here, the one-symbol delay means is configured to
Shift register to which the phase value of the
Counter that supplies the shift clock to the
This counter divides the master clock.
Phase differs at the timing of an integral multiple of one symbol.
Is to create multiple clocks, each counting cycle
And counts for one clock of the master clock
The operation is stopped. [0006] [Function] Demodulation of a digital cellular phone constructed in this way
According to the device, the shift register constituting the one-symbol delay unit is provided.
By reducing the number of stages, the resolution of the DPLL section can be increased.
The change in the phase of the shift register clock
The clock extraction resolution of the DPLL section
To be compensated, especially for one symbol delay
Even if the configuration of
A clock for demodulation data and a clock for demodulated data are obtained.
Effective in forming demodulated data in the decoding unit
Can be used. [0007] BRIEF DESCRIPTION OF THE DRAWINGS FIG.
explain. FIG. 1 shows the configuration of a demodulation device, in which a phase change is performed.
Phase values P1 to Pn of the tuned digital input .theta.
Indicating the sampling resolution of the phase value θ)
Are input to the one-symbol delay unit 11.
You. The output phase values LP1 to LP1
LPn is supplied to the phase difference detector 12 together with the phase values P1 to Pn.
The phase value from the phase difference detector 12
Phase difference value DP1 between P1 to Pn and phase values LP1 to LPn
ＤＰDPn are supplied to the absolute value detection unit 13. The absolute value output AB from the absolute value detector 13
P1 to ABPn are supplied to the detection unit 14 by 1 / 2π or more,
The detection signal DT equal to or more than 1 / 2π is supplied to the DPLL unit 15.
The DPLL unit 15 demodulates the 21 KHz symbol.
Clocks C21K and 42KHz for demodulated data
A lock C42K is formed. The phase difference detection signal from the phase difference detection section 12 is
The upper two bits DPn and DPn-1 in the
The output LD of the shift register 16
Pn and LDPn-1 are input to the decoding unit 17. De
The code section 17 includes the demodulated 21K extracted by the DPLL section 15.
Hz symbol clock C21K and 42KHz demodulation data
Data clock C42K is input and the demodulated data DAT
A is output. The one-symbol delay unit 11^KStep shift cash register
Having a counter 111 and an m + L + 1 bit counter 112
The output SCK from the QL terminal of the counter 112 is
Is supplied to the shift register 111 as a shift clock.
I'm trying. Also, the carry-out of counter 112
The power CO is supplied to a D-type flip-flop (DFF) 113
The output from the DFF 113 is
Input to CE. And this counter 112 is the master
-Driven by the clock MCK. this
The master clock MCK is supplied to the DPLL unit 15 and the shift register.
The data is also supplied to the star 16 and the decoding unit 17. The operation of the demodulation circuit thus configured will be described.
Will be explained. Here, the resolution n for representing the phase θIs
“5” (phase θ = P1 to P5) and the symbol
Master clock for wave number (here 21 KHz)
Increase the frequency of MCK to 32 times (= 2^m= 2⁵, M =
5). First, extraction of the 21 KHz symbol clock
The basic principle of the timing chart of FIG.
When 3 / 4π is received from the port, the phase values P1 to P5 become
From "0" to "12", specifically "0" "3"
It changes like "6" "9" "12". Then 1
When / 2π is input, “12” and “1” are obtained until the phase difference becomes “−4”.
1 ”,“ 10 ”,“ 9 ”, and“ 8 ”.
The same applies to every / 4π and −1 / 4π input. An output from the one-symbol delay unit 11 is supplied.
In the phase difference comparing section 12, the input phase value P shown in FIG.
1 to P5 and LP1 to LP5 are compared.
The phase differences DP1 to DP5 are "12" "-
The values of “12” and “4” like “4” “12” “-4”
It will be taken out. So from this
Timing to extract "12" and "-4"
Extracts and decodes 21 KHz symbol clock
, It can be predicted that demodulation can be performed. In the absolute value detection unit 13, the phase comparison unit 12
Absolute values ABP1 to ABP5 of these phase values DP1 to DP5
Is obtained, and is ππ or more of the absolute value of the phase difference,
That is, “8” or more is detected by the 1 / 2π or more detection unit 14.
And its detection output DT is as shown in FIG.
In the middle of the range where the output DT of
Phase difference value "12"
Become. Therefore, the detection unit 14 has a phase difference
In addition to detecting a section where the logarithmic value is 1 / 2π or more,
A DPLL is applied to the middle of the detection signal DT to demodulate 21 KH.
z Symbol clock C21K and 42KHz demodulated data
Data clock C42K to extract the phase value "12"
And "-4" to enable demodulation.
You. Here, the decoding method is based on the phase differences DP1 to DP5.
Predetermined decoding of upper 2 bits (DP5 and DP4)
42Kb by decoating based on the truth table
The ps demodulated data DATA can be output. That is, the phase values P1 to P5 and one symbol
Data LP1 to LP5 shifted by one symbol in delay section 11
The phase differences DP1 to DP5 with respect to
The absolute value ABP1 of the phase differences DP1 to DP5 is detected by the pair value detector 13.
ＡABP5 is calculated, and the detection unit 14 calculates the phase difference
A detection signal DT having an absolute value of 1 / 2π or more is created. Soshi
The DPLL unit 15 calculates the intermediate point of the detection signal DT and
Key 21KHz Symbol clock C21K and 42KH
z The demodulation clock C42K is extracted and
Upper 2 bits of DP1 to DP5 (DP5, DP3)
The demodulated data is extracted from the data. In the demodulation device configured as described above,
Clock frequency for sampling phase values P1 to P5
Divides the master clock MCK by 4 (= 2^L= 2^Two,
L = 2), this clock is the first
1 clock of master clock MCK
CK0 to CK3 shown in FIG.
Phase is possible. Further, the sampling frequency is set to a master clock.
Clock CK0 set to 1/4 (L = 2) of lock MCK
If CK3 is a shift clock, 2^KStep shift cash register
The number of shift stages of the star 111 (2^K) To normal 32 stages (master
-The clock MCK is 32 times the symbol frequency
The master clock MCK as the shift clock.
A 32-stage system is used to delay the phase values P1 to P5 by one symbol.
8 registers (K = 3).
Here, m, L, and K have a relationship of “m = L + K”. As shown in FIG. 3, the master clock MC
K is divided by 4 and the shift clock of the 1 symbol delay unit 11 is
When created, the shift clock is shifted from the initial state as described above.
There are four types of clocks CK0 to CK3. Now the phase
The signal DT (phase value) that detects 1 / 2π or more of the absolute value of the difference
P1 to P5 are sampled by the master clock MCK.
CK0 to CK3 (phase values P1 to P3)
5 by dividing the master clock MCK by 4
CK0 to Ck3).
Focusing on the position of the midpoint of the signal DT,
Intermediate point between DT0 to DT3 in CK0 to CK3
The error with the position of "+3" (=
2^L-1 = 2^Two-1). For this reason, with respect to the intermediate point between DT0 and DT3,
And apply DPLL to 21 KHz symbol clock C21
When K is to be extracted, the decoding unit 17
21KHz symbol clock C21K and phase difference value
The maximum phase error between the upper two bits of DP1 to DP5 is
“+3” (= 2^L-1 = 2^Two-1). In order to solve such a problem, FIG.
As shown in FIG.
Change from CK0 to CK3 at the timing of integral multiple of the symbol
Creates a shift clock SCK
Sampled phase values P1 to P5 by SCK
The detection signal DT (this 以上 or more)
In the case shown in the figure, the signal including all of DT0 to DT3)
And apply DPLL in the DPLL unit 15 to 21 KHz symbol
If the clock C21K is created, the error is averaged.
After that, the difference is quantitatively calculated as “+1.5” １ = [1+
2 + ... + (2^L-2) + (2^L-1)] / 2^L= [1+
2 + 3] / 2^TwoIt becomes｝. This error depends on the level input to the decoding unit 17.
Phase difference values, that is, outputs DP1 to DP from the phase difference detection unit 12
The upper two bits DP5 and DP4 of P5 are
One stage or two stages with star 16 $ 2^L-1-1 or 2^L-1This
Here 2^2-1Or 2^2-1シ フ ト by shifting
Thus, the error can be "± 0.5". Specifically, as shown in FIG.
The m + L + 1 bit counter 112 counts up
Time of the carry-out CO of this counter 112.
Of the master clock MCK by the DFF113
The counting operation is stopped for one clock, and the shift register 111 is stopped.
To delay each clock by one clock
From all the clock phases CK0 to CK3 in 8 symbols.
To start out. That is, the DFF 113
One or two clocks of the master clock MCK
Phase adjustment with the 21 KHz symbol clock
You will be Therefore, the thus constructed 1 / 4π
According to the DQPSK demodulator, its performance is sacrificed.
By reducing the number of shift stages in the one-symbol delay section.
As a result, the gate size can be reduced. FIG. 6 shows the configuration of a demodulator according to another embodiment.
The output of the m + L + 1 bit counter 112 is +
The output from the DFF 113 is supplied to the
When the signal is input to the terminal CE of the
Causes the output from 4 to be loaded. Such a configuration
By doing, 2^KShift of stage shift register 111
The phase of the clock SCK is one clock of the master clock MCK.
It can be advanced by the amount of the lock. Eight symbols represent all clocks.
So that phases CK0 to CK3 can be taken out.
You. FIG. 7 shows the operation of the one-symbol delay unit 11 in this embodiment.
It is a timing chart which shows a working state. [0026] As described above, the digital signal according to the present invention is
According to the demodulator of the mobile phone, there is no
By reducing the number of shift stages in the 1-symbol delay section,
Gate size can be reduced and its configuration
This has a significant effect on simplification.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit diagram illustrating a demodulator of a digital mobile phone according to an embodiment of the present invention. FIG. 2 is a timing chart illustrating the operation of the demodulation device. FIG. 3 is a timing chart illustrating a general operation of the demodulation device. FIG. 4 is a timing chart illustrating characteristics of the operation of the demodulation device. FIG. 5 is a timing chart for explaining the operation of the one-symbol delay unit of the embodiment. FIG. 6 is a circuit diagram illustrating another embodiment of the present invention. FIG. 7 is a timing chart for explaining the operation of this embodiment. [Explanation of Signs] 11 1-symbol delay unit, 111 ^2K- stage shift register,
112 ... m + L + 1 bit counter, 113 ... DFF, 12 ...
Phase difference detection unit, 13: absolute value detection unit, 14: 1 / 2π or more detection unit, 15: DPLL unit, 16: shift register, 17: decoding unit.

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04L 27/00

Claims (1)

(57) Claims: 1. One-symbol delay means to which a phase-modulated digital input signal is supplied; a phase value of a signal from the one-symbol delay means;
Phase difference detection means for detecting a phase difference from the phase value of the digital input signal; and a symbol clock for detecting the phase difference from the phase difference detection means.
A decoding unit for decoding using the phase difference, and an absolute value of the phase difference detected by the phase difference detection unit.
An absolute value detecting means for detecting, and a range of values in which the detected absolute value is equal to or more than 1 / 2π
Ππ or more detecting means for obtaining the detection signal of, and an intermediate point of the detection signal from the ππ or more detecting means.
The demodulation system for performing demodulation based on the phase of
DP to obtain the symbol clock and supply it to the decoding unit
An LL section, wherein the one-symbol delay means is constituted by a shift register to which a phase value of the input digital signal is inputted, and a counter for supplying a shift clock to the shift register, and the counter divides a master clock. And generating a plurality of clocks having different phases at a timing of an integral multiple of one symbol, wherein the counting operation is stopped by one clock of the master clock in each counting cycle. Demodulator for digital mobile phones.